UVM Advanced Code Snippet Quiz - Semi Design
Q1. What is the correct way to override a UVM component using type override?
uvm_factory::get().set_type_override_by_type(
original_type, override_type
);
A) set_type_override(original_type, override_type)
B) set_type_override_by_name("original_type", "override_type")
C) uvm_factory::get().override_type(original_type, override_type)
D) uvm_factory::get().set_type_override_by_type(original_type, override_type)
Q2. What will the following sequence do?
`uvm_do_with(req, {addr == 16'hA5A5;})
A) Creates and sends `req` without any constraint
B) Applies a constraint that addr equals A5A5
C) Declares a new variable addr
D) Overrides the req object type
Q3. What is the purpose of the following override?
factory.set_inst_override_by_type(
base_seq::get_type(), override_seq::get_type(),
"*.seq1"
);
A) Globally overrides all sequences of base_seq
B) Overrides instances named seq1 only
C) Overrides component construction in the top module
D) Causes compile-time error
Q4. Which UVM phase is best suited for starting sequences on virtual sequencers?
A) build_phase
B) connect_phase
C) run_phase
D) main_phase
Q5. Identify the issue in this code:
task run_phase(uvm_phase phase);
super.run_phase(phase);
`uvm_info("TEST", "Running...", UVM_LOW)
endtask
A) super.run_phase() cannot be called
B) Missing uvm_phase import
C) Missing semicolon after uvm_info macro
D) run_phase is not a valid UVM phase
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UVM Advanced Code Snippet Quiz - Semi Design
Q6. Which UVM macro properly registers a component?
class my_agent extends uvm_agent;
`uvm_component_utils(my_agent)
endclass
A) uvm_utils_component(my_agent)
B) uvm_object_utils(my_agent)
C) uvm_component_utils(my_agent)
D) uvm_register(my_agent)
Q7. What does set_config_int do in this context?
uvm_config_db#(int)::set(this, "[Link]*", "active", UVM_ACTIVE);
A) Sets an integer variable at run-time
B) Assigns a static variable
C) Replaces all active agents with UVM_PASSIVE
D) Passes configuration via constructor
Q8. Which method is mandatory in UVM sequences?
A) body()
B) run()
C) connect()
D) main()
Q9. Why is uvm_declare_p_sequencer used in a sequence?
A) To bind it to a sequencer of any type
B) For hierarchical test execution
C) To access sequencer fields directly
D) To override a sequence at run-time
Q10. Which factory override will affect only a specific path instance?
A) set_type_override_by_type
B) set_inst_override_by_type
C) set_global_override()
D) register_override_path()
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UVM Advanced Code Snippet Quiz - Semi Design
Q11. What is the result of this transaction recording?
`uvm_record_field("addr", addr)
A) Records addr as a string
B) Logs addr to the database
C) Records addr for transaction-level debugging
D) Creates a coverpoint
Q12. In a sequence, how is a sequence item sent to the driver?
A) [Link]()
B) start_item(req); finish_item(req);
C) uvm_do(req)
D) send(req)
Q13. What is wrong with this configuration line?
uvm_config_db#(int)::get(this, "", "max_val", max_val);
A) The context handle is incorrect
B) "" should be replaced with "uvm_test_top"
C) "max_val" must be an object, not int
D) No error - this is valid
Q14. What happens if set_report_verbosity_level(UVM_HIGH) is used?
A) All messages are filtered out
B) Only fatal errors are shown
C) More verbose logs are shown
D) Simulation stops early
Q15. How do you define a UVM field macro for a queue?
`uvm_field_queue_int(data_queue, UVM_ALL_ON)
A) uvm_queue_field(data_queue, ON)
B) uvm_field_queue(data_queue, UVM_ALL_ON)
C) uvm_field_queue_int(data_queue, UVM_ALL_ON)
D) uvm_field_array(data_queue)
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UVM Advanced Code Snippet Quiz - Semi Design
Q16. In UVM, what does this macro expand to?
`uvm_info("ID", "Message", UVM_MEDIUM)
A) Calls display() with "Message"
B) Displays a formatted message based on verbosity
C) Ignores the message unless severity is fatal
D) Routes message to a log file only
Q17. What is the use of uvm_object_wrapper?
A) For transaction conversion
B) For cloning UVM components
C) For factory registration and override
D) For printing UVM objects
Q18. Identify the issue in this UVM factory override:
factory.set_type_override_by_name("base_seq", "override_seq");
A) Needs to be in run_phase()
B) Class names should be in lowercase
C) Classes must be registered using uvm_object_utils
D) This syntax is not supported in UVM
Q19. What is the role of start_item() in UVM?
A) Creates a sequence
B) Starts a UVM test
C) Initiates a transaction with the driver
D) Declares a phase
Q20. Which of the following is TRUE about uvm_component and uvm_object?
A) Both support factory registration
B) Only uvm_object supports hierarchy
C) Only uvm_component has phases
D) Neither supports configuration
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