EE477L

CMOS Digital Integrated Circuits

Combinational Logic Circuits
Spring 2025

Instructors: Mehdi Kamal, Shahin Nazarian, Massoud Pedram

University of Southern California
Dept. of Electrical and Computer Engineering

Original Slides by Massoud Pedram

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 (Fully Complementary Static)
CMOS Logic Circuits
VDD

VA
pMOS
VB network

Vout

VA
nMOS
network
VB

nMOS network ON, pMOS network OFF

or
nMOS network OFF, pMOS network ON

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 Example: CMOS NAND2 Gate

• The NAND2 gate can be modelled as an appropriately-sized

inverter under multiple-identical-input-change assumption.

CMOS NAND2 gate and its inverter equivalent

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 AOI and OAI Gates

• AOI (AND-OR-INVERT)
- for SUM-of-PRODUCTS realization.
• The pull-down net of the AOI gate consists of parallel branches
of series-connected nMOS driver transistors.

An AND-OR-INVERT gate and the

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 AOI & OAI Gates (Cont’d)

• OAI (OR-AND INVERT)

- for PRODUCT-of-SUMS realization.
• The pull-down net of the OAI gate consists of series branches
of parallel-connected nMOS driver transistors.

An OR-AND-INVERT gate and the

corresponding pull-down net.
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 Reduction of Complex Static CMOS
Gates to Inverters
VDD
W  W  1
  =   +
B  L equivalent , Z  L  D 1 1
+
W  W  W 
A     + 
C Reduction under multiple-identical-  L  A  L  B  L C
input-change assumption!

D
OUT = D + A• (B+C)
A
D
Reduction under worst-case single-
B C input-change assumption!

 
 
 
W   W  1 1
  = MIN    , , 
 L  worstcasedelay , Z   L D 1 1 1 1 
 + +
W  W  W  W  
         
  L  A  L  B  L  A  L C 
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M. Pedram USC/EE 6
 Transistor Sizing for Fast Complex Logic
Cells
• Do transistor sizing for (a)
symmetrical tpHL and tpLH
response, (b) maximizing the
switching speed, i.e., • for symmetrical response (dc, ac)
• for performance
MinMax(tpHL, tpLH) VDD
- Make pMOS transistors bigger to
B 12
account for electron-hole mobility A 6
Input Dependent
differences C 12
Focus on worst-case
- Focus on worst-case input D 6

combination A 2
F

- Assume the switching speed of D 1

2 C 2
min-size NMOS transistor is 3 B

times that of a min-size PMS

transistor

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 Transistor Sizing (Cont’d)
• One should use
• Transistor progressive sizing as shown below to
Sizing:
switching
Asspeed of Fan-out
long as the logicCapacitance
cell dominates
- M1 has to carry discharge current of C1+C2+…+CL whereas MN has to
• carry
Progressive Sizing:
only the discharge current for CL
Out
InN MN CL
Out
M1 > M2 > M3 > MN
In3
In3 C3
M3
Distributed RC-line In2
In2 M2 C2
In1
Gnd
In1 M1 C1
Can
The Reduce Delaysizing
progressive with more
can than
result30%!
in up to 30%
propagation delay reduction!
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 Transistor Topology Optimization for Fast
Complex Logic Cells
• Place the node connected to least number of parallel-connected transistors
closer to the output terminal (unless we have timing information about the
relative arrival times of input signals). For example, consider the following:

(3)
Layout 1 is the
preferred layout
since fewer
diffusion caps will
have to be
discharged during
an output high to
(2)
low transition e.g.,
consider output (3) (2) (1)
(1)
falling in response
to ABCD: (3)
01-- →11--

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 Transistor Ordering for Fast Complex
Logic Cells
• Assign the late-arriving (timing-critical) signal to the transistor
which is closest to
• Transistor the output of the logic cell since this signal-
Ordering
to-pin assignment minimizes the propagation delay thru the cell.
critical path critical path

CL CL
In3 M3 In1 M1

In2 M2 C2 C2
In2 M2
Delay(b) ≤ Delay(a)
In1 M1 C1 C3
In3 M3

(a) (b)
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 Good Practices for Fast Complex Logic
Cells
• Avoid largeLogic
• Improved fanin gates
Design

• Buffering: Isolate Fan-in from Fan-out

• Buffer large fanout loads

CL CL

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 First-Order Logic Design Trade-offs

• General Guidelines:
– Use NAND structures where possible.
– Place inverters or small fan-in NAND gates at high fan-out nodes.
– Avoid NOR structures in high-speed circuits, particularly with a fan-in
greater than four and where fan-out is large.
– Use a fan-out below 5-10.
– Use minimum-sized receiver gates on high fan-out nodes to minimize
load.
– Size up the driver gate for high fan-out scenarios.
– Keep rising and falling edges sharp for example by adding a large-size
gate (strong drive capability) on the path of transitions which slope has
degraded.

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 Logic Design Trade-offs (Cont’d)

• Guidelines to improve delay:

– Size transistors when routing and gate capacitance contributes
significantly to total load capacitance.
– Sizing transistors along series paths can improve delay. In this case,
increase the size of transistors proportional to their distance from the
output node.
– Order transistors so that the transistor closest to the output is the
transistor that receives its input signal last.
– Manipulate logic expressions to replace large fan-in gates with
equivalent circuits composed of gates with smaller fan-ins.
– Insert buffers (i.e. an inverter) on the output of large fan-in gates in
order to reduce the output load capacitance.
– Use other styles of logic (to be discussed).

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 CMOS Transmission Gates

• The CMOS transmission gate (TG) consists of one nMOS and

one pMOS transistor, connected in parallel.
• The CMOS TG operates as a bidirectional switch between
nodes A and B, which is controlled by signal C.

Four different representations of the CMOS transmission gate.

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 CMOS Transmission Gates (Cont’d)

• If the control signal C is logic-high, then both transistors are

turned on and provide a low-resistance current path between
the nodes.
• If the control signal C is logic-low, then both transistors are
turned off and the path between the node A and B will be an
open circuit.
• We consider the following bias condition for detailed DC
analysis.

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 CMOS Transmission Gates (Cont’d)
• The input node (A) is connected to a constant logic-high voltage.
• The output node (B) may be connected to a capacitor, which
represents capacitive loading of the subsequent logic stages that
are driven by the transmission gate.
- The drain-to-source and the gate-to-source voltages of the nMOS
transistors are, VDS= VDD − Vout VGS= VDD − Vout
,n ,n

- Thus, the nMOS transistor will be turned off for Vout > VDD – VT,n and will
operate in the saturation mode for Vout < VDD – VT,n .
- The VDS and VGS voltages of the pMOS transistors are,
VDS=
,p Vout − VDD VGS , p = −VDD
- The pMOS transistor is in saturation for Vout < |VT,p|, and it operates in the
linear region for Vout >|VT,p|.
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 CMOS Transmission Gates (Cont’d)
• We can identify three operating regions for the CMOS
transmission gate, depending on the output voltage level.

• The total current flowing through the transmission gate is the

sum of the nMOS drain and the pMOS drain current:
I D I DS ,n + I SD , p
=
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 CMOS Transmission Gates (Cont’d)
• In region 1, Vout < |VT,p|.
- pMOS and nMOS transistors are in the saturation region.
2(VDD − Vout ) 2(VDD − Vout )
Req,n = Req,p =
kn (VDD − Vout − VT ,n ) 2 k p (VDD − | VT , p |) 2

- The source-to-substrate voltage of the nMOS transistor is equal to the

output voltage, while the source-to-substrate voltage of the pMOS transistor
is equal to zero, thus the substrate-bias effect for the nMOS transistor must
be taken into account.
• In region 2, |VT,p| < Vout < VDD -VT,n.
- pMOS transistor is in the linear region
- nMOS transistor is in the saturation region.

2(VDD − Vout ) 2
Req,n = Req,p =
kn (VDD − Vout − VT ,n ) 2 k p [2(VDD − | VT , p |) − (VDD − Vout )]
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 CMOS Transmission Gates (Cont’d)
• In region 3, the output voltage is Vout > VDD - VT,n.
- pMOS transistor is in the linear region
- nMOS transistor is turned off.
2
Req,n =
∞ Req,p =
k p [2(VDD − | VT , p |) − (VDD − Vout )]

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Equivalent resistance of the CMOS transmission gate. 19
 CMOS Transmission Gates (Cont’d)

• A CMOS pass gate which is turned on by a logic-high control

signal can be replaced by its simple equivalent resistance for
dynamic analysis (details omitted).

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 CMOS Transmission Gates (Cont’d)

• Multiplexers 2:1 MUX 4:1 MUX using 2:1 MUX’s

• XOR

Eight-transistor CMOS TG implementation. Six-transistor CMOS TG implementation.

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 CMOS Transmission Gates (Cont’d)

• Using the generalized multiplexer approach, each Boolean

function can be realized with a TG logic circuit.

- Input variables and their inverses must be used to control the CMOS
transmission gates.
- Exactly one conducting TG network should always be provided between
the output node and one of the inputs.
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 Complementary Pass-Transistor Logic

• The complexity of full CMOS pass-gate logic circuits can be

reduced by adopting Complementary Pass-transistor Logic (CPL).
• Use a purely nMOS pass-transistor network for the logic
operations.
• All inputs are applied in complementary form.

CPL NAND2 gate CPL NOR2 gate 2:1 MUX gate

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 Complementary Pass-Transistor Logic
(Cont’d)
• The elimination of pMOS transistors from the pass-gate
network reduces the parasitic capacitance associated with
each node in the circuit. Thus, the operation speed is higher
compared to a full CMOS counterpart.
– In CPL, the threshold voltages of the nMOS transistors in the pass-
gate network must be reduced to about 0V through threshold-
adjustment implants in order to eliminate the threshold-voltage drop.
– This reduces the overall noise immunity and causes higher
subthreshold conduction in the off mode.
– The CPL design style is highly modular. However, it does not always
offer a marked advantage over conventional CMOS in terms of area.

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 Complementary Pass-Transistor Logic
(Cont’d)
• CPL-based XOR gate
– The cross-coupled pMOS pull-up transistors are used to speed up the
output response. Transistor widths are given in lambda units.

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 Complementary Pass-Transistor Logic
(Cont’d)
• CPL full adder (comprising of 32 transistors)

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 Gate Diffusion Input Logic (Optional)

GDI gates may suffer from threshold voltage drops,

which reduce current drive and therefore affect the
performance of the gate. It has been shown that
𝑝𝑝 = 𝑎𝑎 𝑥𝑥𝑥𝑥𝑥𝑥 𝑏𝑏
these effects can be significantly reduced by using
swing-restoration buffers with a multiple VTH
approach, herein named MVT. This approach 𝑔𝑔 = 𝑎𝑎 𝑏𝑏
suggests using low threshold transistors in all paths
where a voltage drop is expected. This way, the
voltage drop at the output will be minimal.
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 Gate Diffusion Input Logic (Cnt’d)
(Optional)
One can also design full-swing (FS) GDI cells. The technique utilizes a single swing
restoration (SR) transistor to improve the output swing of F1 and F2 GDI gates. Figure
below shows the structure of full-swing F1 and F2 cells. As can be seen, the SR transistor
is activated only in cases when the VTH drop may occur at the output. Since in F1 and F2
gates, the output VTH drop can occur only at one of the logical levels (VTH instead of 0V
in F1, and VDD–VTH instead of VDD in F2), only a single SR transistor is required to
ensure the full-swing operation.

FS GDI F1 cell FS GDI F2 cell

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 CMOS Schmitt Trigger Circuit (Optional)
The circuit shown below is a CMOS Schmitt-Trigger circuit. Let VDD=2.5V,
Vtn=0.5V, (W/L)M1 = 1/0.25 and (W/L)M2 = 2/0.25. Switching threshold of the
symmetric inverter INV is 1.25V. Determine (W/L)M3 = 1/0.25 and (W/L)M4 so that
VM+=1.5V and VM-=1.0 V.

𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂
𝑉𝑉𝐷𝐷𝐷𝐷

INV

0 𝑉𝑉𝐼𝐼𝐼𝐼
𝑉𝑉𝑀𝑀− 𝑉𝑉𝑀𝑀+ 𝑉𝑉𝐷𝐷𝐷𝐷

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 Schmitt Trigger Circuit Analysis (Optional)

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 Another CMOS Schmitt Trigger Circuit
(Optional)

M4 M6

M3

M2

M5 𝑉𝑉𝑀𝑀+
M1 𝑉𝑉𝑀𝑀−

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