Problems 93
FETs operating in saturation) for all transistors. If the drain of a device is connected to a high impedance
(e.g., the drain of another), then add r O to its model. At this point, the basic properties of most circuits
can be determined by inspection. In a second, more accurate iteration, the body effect of devices whose
source or bulk is not at ac ground can be included as well.
For bias calculations, it is usually adequate to neglect channel-length modulation and body effect
in the first pass. These effects do introduce some error, but they can be included in the next iteration
step—after the basic properties are understood.
In today’s analog design, simulation of circuits is essential because the behavior of short-channel
MOSFETs cannot be predicted accurately by hand calculations. Nonetheless, if the designer avoids a
simple and intuitive analysis of the circuit and hence skips the task of gaining insight, then he/she cannot
interpret the simulation results intelligently. For this reason, we say, “Don’t let the computer think for
you.” Some say, “Don’t be a SPICE monkey.”
Problems
Unless otherwise stated, in the following problems, use the device data shown in Table 2.1 and assume that
V D D = 3 V where necessary. All device dimensions are effective values and in microns.
3.1. For the circuit of Fig. 3.13, calculate the small-signal voltage gain if (W/L)1 = 50/0.5, (W/L)2 = 10/0.5,
and I D1 = I D2 = 0.5 mA. What is the gain if M2 is implemented as a diode-connected PMOS device
(Fig. 3.16)?
3.2. In the circuit of Fig. 3.18, assume that (W/L)1 = 50/0.5, (W/L)2 = 50/2, and I D1 = I D2 = 0.5 mA when
both devices are in saturation. Recall that λ ∝ 1/L.
(a) Calculate the small-signal voltage gain.
(b) Calculate the maximum output voltage swing while both devices are saturated.
3.3. In the circuit of Fig. 3.4(a), assume that (W/L)1 = 50/0.5, R D = 2 k, and λ = 0.
(a) What is the small-signal gain if M1 is in saturation and I D = 1 mA?
(b) What input voltage places M1 at the edge of the triode region? What is the small-signal gain under this
condition?
(c) What input voltage drives M1 into the triode region by 50 mV? What is the small-signal gain under this
condition?
3.4. Suppose the common-source stage of Fig. 3.4(a) is to provide an output swing from 1 V to 2.5 V. Assume that
(W/L)1 = 50/0.5, R D = 2 k, and λ = 0.
(a) Calculate the input voltages that yield Vout = 1 V and Vout = 2.5 V.
(b) Calculate the drain current and the transconductance of M1 for both cases.
(c) How much does the small-signal gain, gm R D , vary as the output goes from 1 V to 2.5 V? (Variation of
small-signal gain can be viewed as nonlinearity.)
3.5. Calculate the intrinsic gain of an NMOS device and a PMOS device operating in saturation with W/L = 50/0.5
and |I D | = 0.5 mA. Repeat these calculations if W/L = 100/1.
3.6. Assuming a constant L, plot the intrinsic gain of a satuated device versus the gate-source voltage if (a) the
drain current is constant, (b) W is constant.
3.7. Assuming a constant L, plot the intrinsic gain of a saturated device versus W/L if (a) the gate-source voltage
is constant, (b) the drain current is constant.
3.8. An NMOS transistor with W/L = 50/0.5 is biased with VG = +1.2 V and VS = 0. The drain voltage is
varied from 0 to 3 V.
(a) Assuming the bulk voltage is zero, plot the intrinsic gain versus V DS .
(b) Repeat part (a) for a bulk voltage of −1 V.
3.9. For an NMOS device operating in saturation, plot gm , r O , and gm r O as the bulk voltage goes from 0 to −∞
while other terminal voltages remain constant.
94 Chap. 3 Single-Stage Amplifiers
3.10. Consider the circuit of Fig. 3.13 with (W/L)1 = 50/0.5 and (W/L)2 = 10/0.5. Assume that λ = γ = 0.
(a) At what input voltage is M1 at the edge of the triode region? What is the small-signal gain under this
condition?
(b) What input voltage drives M1 into the triode region by 50 mV? What is the small-signal gain under this
condition?
3.11. Repeat Problem 3.10 if body effect is not neglected.
3.12. In the circuit of Fig. 3.17, (W/L)1 = 20/0.5, I1 = 1 mA, and I S = 0.75 mA. Assuming λ = 0, calculate
(W/L)2 such that M1 is at the edge of the triode region. What is the small-signal voltage gain under this
condition?
3.13. Plot the small-signal gain of the circuit shown in Fig. 3.17 as I S goes from 0 to 0.75I1 . Assume that M1 is
always saturated, and neglect channel-length modulation and body effect.
3.14. The circuit of Fig. 3.18 is designed to provide an output voltage swing of 2.2 V with a bias current of 1 mA
and a small-signal voltage gain of 100. Calculate the dimensions of M1 and M2 .
3.15. Sketch Vout versus Vin for the circuits of Fig. 3.78 as Vin varies from 0 to V D D . Identify important transition
points.
VDD VDD V DD
RD RD RD
RF
Vout Vout Vout
M1
Vin M1
Vb RF Vin M1
V in RS
(a) (b) (c)
VDD VDD
RD Vin M1
Vin RF
M1 Vout
Vout
RS
RS
(d) (e)
Figure 3.78
3.16. Sketch Vout versus Vin for the circuits of Fig. 3.79 as Vin varies from 0 to V D D . Identify important transition
points.
3.17. Sketch Vout versus Vin for the circuits of Fig. 3.80 as Vin varies from 0 to V D D . Identify important transition
points.
3.18. Sketch I X versus V X for the circuits of Fig. 3.81 as V X varies from 0 to V D D . Identify important transition
points.
3.19. Sketch I X versus V X for the circuits of Fig. 3.82 as V X varies from 0 to V D D . Identify important transition
points.
Problems 95
VDD VDD
Vb RD V in RD
M2 M2
Vout Vout
Vin M1 Vb M1
(a) (b)
VDD VDD
R1
Vb2 M2
M2
R2 Vout
Vout
Vb1 M1
Vin M1
V in
RS
(c) (d)
Figure 3.79
VDD
VDD
V b2 M3
V in M1 Vout
V b1 M2
Vout
Vb M2 V in M1
(a) (b)
VDD VDD
V in M3 V in M3
Vout
V b1 M2
V b1 M2
Vout
V b2 M1 V b2 M1
(c) (d)
Figure 3.80
