Introduction to PNR

• Object of PNR: To place standard cells/hard macros on the die and the nets based
on connectivity we have to follow the rules provided by foundry while placing
standard cells & routing nets.
• Also along with above rules, we need to meet PPA.
• Stages:
• Floor Planning: Die area, port placement, macro placement, power grid, boundary
cells, tap cells(pre placed cells)
• Placement: Placing standard cells in core region (clock is ideal)
• Clock Tree Synthesis (CTS): Buffering the clock nets
• Post CTS Optimization: To fix violations due to clock skew
• Routing: Routing is a fundamental step in VLSI physical design that transforms
logical connectivity into physical layouts using metal interconnects
• Post Route Optimization: Fix additional violations due to cross talk or RC
mismatch
• ECO(Engineering change order): To fix the sign off related violations.
• Signoff checks:
• Timing(STA)
• Physical verification(PV)
Clean Tapeout
• IR drop
• LEC(Logical Equivalence check )

• Tools Used:
• PNR: Synopsys: IC Compiler/Fusion compiler
• Candence: Innovus
• Timing(STA): Synopsys: Prime time (pt_shell)
• Cadence: Tempus
• Physical verification(PV): Synopsys: IC Validator
• Cadence: Reqasus
• Mentor Graphics: Calibre(widely used)
• IR Drop: Synopsys: Primerail
• Cadence: Voltas
• Ansys: Redhawk
• LEC: Synopsys: Formality(fm_shell)
• Cadence: Conformal
Index

• Gate Level Netlist • Power Intent

• Logical Libraries • Power Specification file
• Physical Libraries • ScanDEF
• Technology Files • Optimization Directives
• TLU+ file • IO information files
• Synopsys Design Constraints • Sanity Checks
• CTS spec file
• MMMC view file
Inputs to PD (File Format)
Technology Design Specific Inputs
Specific Inputs

Physical
Optional Inputs
Libraries Mandatory Inputs
(.lef)

Technology Gate Level Netlist Multi-Mode Multi-

(.v) Corner (.tcl)
File (.tf)

Common Power
TLU + File Synopsis Design Format/Unified
(.TLUP) Constraints (.SDC) Power Format
(.cpf/.upf)

Logical
Libraries SCANDEF (.def)
(.lib/.db)
Gate Level Netlist (.v) -----> Given by Synthesis
• This is a synthesized netlist. This file contains all the instances of design and their
connections.
• Textual description of circuit components (like logic gates, combinational circuits,
sequential circuits), So netlist is a collection of gates.
• Gate level netlist contains logical connectivity of the cells.
• It can also be a collection of resistors capacitors or transistors.
Synopsys Design constraints (.sdc) -----> Given by Synthesis
• SDC is a common format for constraining the design which is supported by
almost all synthesis, PNR, and other tools. Generally, timing, power, and area
constraints of design are provided through the SDC file, and this file has an
extension .sdc.
• SDC file syntax is based on TCL format and all commands of sdc file follow the
Tcl syntax.
• In sdc file '#' is used to comment a line and “ is used to break the line.
• SDC file can be generated by synthesis tool and the same can be used in for PNR.
• SDC is a common format for constrainting the design which is supported by almost
all synthesis, PNR and other tools.
• Generally,timing, power and area and constraints of design are provided through
the SDC file and this file has extension(.sdc)
Logical Libraries (.lib/.db) -----> Given by Vendors
• The logical libraries is also called a Timing Library, functional library or power
library As it contains the functionality, time, and power information of cells
• This file contains the following information about standard cells or macros.
• Timing information of Standard cells,soft macros and hard macros. (Delay, Transition).
• It also contains the functionality information of standard cells and soft macros.
• Timing information like cell delays,setup,hold,recovery and removal timings are there.
• Area of standard cells/macros.
• Pin directions and Capacitance.
• Leakage power of standard cells/macros.

• The logical libraries could be in Liberty format (.lib) file for Cadence Tool (or) in
the form of (.db) file for Synopsys Tool.
• Cell delays are calculated by using CCS and NLDM models
• In CCS (composite current source) current source is used for driver modeling, CCS has 20
variables to account input slew and output load data.
• Where as, NLDM uses the voltage source for driver modeling and it has only 2 variables
which are not sufficient for modeling the nonlinearity of any circuit.
• So CCS is more accurate than NLDM. Because of the difference in number of variables
used in both the models.
• Also the run time for CCS is more when compared to NLDM.
• file size is more in CCS compared to NLDM model
• The design needs to be tested for certain PVT (process voltage and temperature) corners.
But for every PVT corner, the timing of the cells are different. Hence there is a .lib file for
every PVT corner.
Unit attributes Each cell attributes
• Time unit • Area of the cell
• Current unit • Leakage power
• Voltage unit • Rise & Fall capacitance
• Capacitance load unit
• Leakage power unit
• Slew rates
• Input threshold at rise and fall time
• Output threshold at rise and fall time
Example
Physical Libraries (.lef) ------> Given by Vendors
• The physical library contains the abstract view of the layout for standard cells and
macros.
• LEF file contains:
• Size of the cell (height and width).
• Pin name, direction, use, shape, layer.
• Pins location.

• Physical libraries are in library exchange format(.lef) for the cadence tools and
.CELL and FRAM form for the Synopsys tool.
• It has mainly two parts:
• Technology LEF
• Cell LEF
• Technology LEF
• The Technology LEF part contains information regarding all the metal
interconnections, via information and related design rules whereas the cell LEF part
contains information related to the geometry of each cell.
• The Technology LEF part contains the following information
• LEF Version (like 57 or 5-8)
• units (for database, time, resistance, capacitance)
• Manufacturing grids
• Design rules and other details of BEOL (Back End of layers)
• Layer name (like poly, contact, via 1, metal 1, etc)
• Layer type (like routing, masterslice, cut, etc)
• preferred direction (like horizontal or vertical)
• Pitch
• minimum width
• Spacing
• Sheet
• Cell LEF
• Cell LEF contains the information related to each cell present in the standard cell
library in separate sections
• Cell LEF contains the following information:
• Cell name (like AND2x2, CLKBUF 1, etc)
• Class (like CORE or PAD)
• origin oo
• Size (width x height)
• symmetry (like XY, X, Y, etc.)
• Antenna ratio
• Pin Information:
• Pin name (like A, B, Y, etc.)
• Direction (like input, output, inout, etc)
• Use (like signal, clock, power etc)
• shape (Abutment in case of power pin)
• Layer (like Metal 1, Metals, etc)
• The rectangular coordinate of pin (||x||y urx ury)
Technology file (.tf)------> Given by Fabrication
• The Technology library is the most important critical input to the physical design tool.
• The technology library contains detailed information about all the metal layers, vias, and their
design rules.
• This file is in ASCII format and contains the following information:
• Manufacturing grid
• Layers name (poly)contact/metal 1/vias)
• Types and the direction of the metals.
• Pitch
• Width
• Spacing
• Resistance per square unit

• The technology file used by the cadence tool is (.techlef) format and (.tf) by Synopsys tool.
• Maximum current density is also present in the tech file.
 TLU + File ---------------------> Given by Fabrication

• It contains RC parasitic of metal per unit length and spacing

• This info is used to calculate Net delays
• If .tlup is not given then the .itf file is used. tlu+ file is derived from .itf file
• Tlu+file is a system-readable file and is in binary format.
• The TLU+ models enable accurate RC extraction results by including the effect of width,
space, density and temperature on the resistance coefficients.
• The main functions of this file can be given as finding:
• R,C parasitics of metal per unit length.
• These parasitics are used for calculation Net delays.
• If TLU+ files are not given, then these are extracted from .ITF file.
• For loading TLU+ files, we have to load three files Max TLU+, Min TLU+ and Map file.
- Map file maps the .ITF file & .tf file of the layer and via names.
CTS Spec file
• Clock specification file which contains:
Insertion delay
Skew
Clock transition
Clock cells
NDR
CTS tree type
CTS exceptions
list of buffers/inverters etc.
MMMC View File (.tcl)------> Given by Top Level
• Multi-Mode Multi-corner file is used to generate different analysis views based on
different delay corners and constraints modes. Delay corners are defined on
library sets and RC corners.
• There are various library set files based on voltage and temperature Values (like
ss, ff, typical)
• The above set of files is needed to initiate all the physical designs.
• some file formats are different from the Cadence tool and Synopsys Tool.
• some optional files might be required especially for block-level pnr
implementation.
• Block partition
• pin def
• power plan script
Creating Scenarios
1. We need to create mode
2. We need to create PVT corners
3. Create RC corners
4. Crreate scenario using above modes & corners
Eg: func_slowm40_cworst
create_mode func
create_corner slowm40
read_parasitic_tech –name cworst –tlup <cworst tluplus file>
set_voltage 0.72
set_temperature -40
set_process_number 1.0
• Set_parasitic_parameters –late_spec cworst -early_spec cworst –corner
[get_corners slowm40]
• Current_mode func
• Current_scenario func_setup_ssg0p81vm40c_cw
• Set_scenario_status –setup true –hold false [get_scenarios “setup”]
• Report_corners
• Report_scenarios
Power Intent (.cpf/.upf file) ---> Given By Top Level
• The power intent file describes which power rails should be routed to individual
blocks and when the block should be powered on or shut down.
• Unified power format (.upf) and common power format (.cpf) are two different
formats of power intent files.
• CPF format is used by the cadence tool and UPF format is used by other tools.
• we must need this file if the block has a multi-voltage domain.
• Power switching info
• Isolation cells
• Retenstion regesters
• Level shifters
create_power_domain command to define power domains and
include design elements in each domain
Power Specification File:
• Power Modes & Power Domains
• Tie up supply & Tie Low supply
• Power Nets &GND nets.
SCANDEF (.scandef) -----------> Given by Synthesis
• Design to describe the scan chains and scan test architecture of a digital
integrated circuit. It provides essential information for implementing scan-based
testing, which is a technique used to facilitate the testing and debugging of digital
chips during manufacturing and in-field operation.
• Scan chains are group of flip-flops that are serially connected through SI/SO pins.
Scan chain paths are active only during test mode. Scan chain is a technique used
in Design For Testing (DFT).
Optimization Directives:
• Don’t use
Cells that are not supposed to optimize
• Size only/use only
Upsizing/Downsizing only with this list of cells.
IO Information File:
• Pin/Pad locations
• Edge and order for IO placement
• .tdf , .io are common formats.
 SANITY CHECKS
• We need to perform some sanity checks before we start our physical design flow, to
ensure that inputs received from various team such as synthesis team, library team etc
are correct.
• If we missed this checks than it can create problem in later stage.
• Below are input files which we are mainly checking
1. Library Checks
2. Design/Netlist Checks
3. SDC Checks
• ICC Command: check_library
• This command shows the name of the library, name of the file, library type &
version, time unit, capacitance unit, leakage power unit, current unit
• It shows the no of cells missing, no of metals or pins missing in physical and
logical library.
• Tool will check by this command
check_library (ICC2)
Check_design -all (INNOVUS)

• It will check both the libraries

• Tool will check the cells across the libraries same or not.
• All cells have timing and power libraries.
• All cells have physical libraries.
2. Design/Netlist Checks:
• It checks the current design for consistency. It checks the internal representation of
the current design for consistency and issues error and warning messages as
appropriate.
• It checks the quality of netlist and identifies:
- Floating pins
- Multi-driven nets
- Black box module
- Undriven input ports
- Unloaded output ports
- Unconstrained pins
- Pin direction mismatches.
ICC Command: check_design

INNOVUS Command: Check_design -netlist

This command shows the particular i/p port is connected to o/p ports and vice-versa and o/p
port is connected to logic 0 and a pin on submodule is connected to logic 1 or logic 0.
3. SDC Checks:
• PNR tool wont optimize the paths which are not constrained. So, we have to check
if any unconstrained paths are exist in the design. This checks:
- Clock reaching all the clock pins of flops or not
- Ports missing input/output delay
- Ports missing slew/load constraints
- Multiple clocks driving same register
- Unconstrained end points
- Combinational loops.
ICC Command: check_timing
• This command reports unconstrained paths. If there are any unconstrained paths in
the design, run the report_timing_requirements command to verify that the
unconstrained paths are false path.
How To Import The Design
• So there are mainly two companies who provide (EDA) Electronic Design
Automation tools for PNR, they are….
1. Synopsys.
• IC Compiler II (icc2_shell).
• Fusion Compiler (fc_shell).
1. Cadence.
• Innovus
• So, By using these EDA tools we will work on PNR, which tool we use in project
will be depending upon client and depending upon project.
How to invoke IC compiler II Tool
As soon as we invoke the tool first we have to create a
New Design Library using command create_lib.
Read Gate Level Netlist by using command
read_Verilog.
• Read_Verilog
• Read_sdc
• Load_upf
• Read_def