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Top 20 Tough & Tricky RTL Interview
Questions & Answers
Asked in top Semiconductor companies
Question 1
Write a Verilog module that implements a 4-to-1 multiplexer with parameterized data
width.
Concept Tested:
Parameterized modules, multiplexing, combinational logic.
Detailed Answer:
A 4-to-1 multiplexer selects one of four input data lines based on a 2-bit select signal.
Parameterizing the data width allows the mux to handle any data size. Use a
combinational always block or continuous assignments.
Verilog Code:
module mux4to1 #(parameter WIDTH = 8) (
input wire [WIDTH-1:0] in0, in1, in2, in3,
input wire [1:0] sel,
output reg [WIDTH-1:0] out);
always @(*) begin
case (sel)
2'b00: out = in0;
2'b01: out = in1;
2'b10: out = in2;
2'b11: out = in3;
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default: out = {WIDTH{1'b0}};
endcase
end
endmodule
Tricky Aspects / Common Mistakes:
• Forgetting default case, which can infer latches.
• Using blocking vs non-blocking assignments incorrectly (use blocking = for
combinational).
• Incorrect bit-width handling in parameterization.
Why MNCs Ask This:
Multiplexers are basic building blocks; demonstrating parameterization and clean RTL
coding shows a solid foundation in combinational design.
Question 2
Explain the difference between blocking (=) and non-blocking (<=) assignments in Verilog
with examples.
Concept Tested:
Procedural assignment semantics, simulation vs synthesis behavior.
Detailed Answer:
• Blocking (=): Executes statements sequentially, used in combinational logic inside
always @(*).
• Non-blocking (<=): Executes all RHS evaluations first, then updates LHS at the end
of the timestep, used in sequential logic (always @(posedge clk)).
Example:
Verilog Code:
always @(*) begin
a = b;
c = a; // with blocking, c gets old value of a, careful ordering needed
end
always @(posedge clk) begin
a <= b;
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c <= a; // with non-blocking, c gets previous cycle's a, simulates flip-flop behavior
end
Tricky Aspects:
• Mixing blocking and non-blocking assignments incorrectly can cause simulation
mismatches and synthesis errors.
• Using blocking assignments in sequential logic can lead to race conditions.
Why MNCs Ask This:
Shows understanding of RTL coding discipline, crucial for predictable hardware behavior.
Question 3
Write a parameterized synchronous FIFO with full and empty flags in Verilog.
Concept Tested:
Synchronous FIFO design, pointer management, flag logic, parameterization.
Detailed Answer:
A synchronous FIFO uses separate read and write pointers incremented on clock edges.
Full and empty flags are derived from pointer comparisons including wrap-around
detection using an extra bit.
Verilog Code:
module fifo_sync #(parameter DATA_WIDTH=8, parameter DEPTH=16) (
input clk,
input rst_n,
input wr_en,
input rd_en,
input [DATA_WIDTH-1:0] data_in,
output reg [DATA_WIDTH-1:0] data_out,
output full,
output empty
);
reg [DATA_WIDTH-1:0] mem [0:DEPTH-1];
reg [$clog2(DEPTH):0] wr_ptr, rd_ptr;
wire [$clog2(DEPTH):0] wr_ptr_next = wr_ptr + 1;
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wire [$clog2(DEPTH):0] rd_ptr_next = rd_ptr + 1;
assign full = (wr_ptr_next == rd_ptr);
assign empty = (wr_ptr == rd_ptr);
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
wr_ptr <= 0;
rd_ptr <= 0;
data_out <= 0;
end else begin
if (wr_en && !full) begin
mem[wr_ptr[$clog2(DEPTH)-1:0]] <= data_in;
wr_ptr <= wr_ptr_next;
end
if (rd_en && !empty) begin
data_out <= mem[rd_ptr[$clog2(DEPTH)-1:0]];
rd_ptr <= rd_ptr_next;
end
end
end
endmodule
Tricky Aspects:
• Pointer wrap-around can be confusing without the extra bit for full detection.
• Forgetting to use non-blocking assignments in sequential logic.
• Mixing full and empty logic can cause deadlock.
Why MNCs Ask This:
FIFO design is a key skill for data buffering and flow control in hardware.
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Question 4
How do you model a clock gating cell in Verilog and explain its power benefits?
Concept Tested:
Power optimization, clock gating, RTL design impact on synthesis.
Detailed Answer:
Clock gating disables the clock to registers when they are idle, reducing dynamic power
consumption. Typically modeled by ANDing clock with an enable signal, but synthesis
tools infer specialized clock gating cells if coded properly.
Verilog Code:
module clock_gating (
input clk,
input en,
output gated_clk
);
assign gated_clk = clk & en;
endmodule
Tricky Aspects:
• Improper gating can cause glitches and timing issues.
• Using combinational logic in the clock path is risky; proper sync cells or tool
inference recommended.
Why MNCs Ask This:
Shows understanding of low-power design techniques critical in modern chips.
Question 5
Design a parameterized ALU supporting addition, subtraction, AND, OR, XOR operations.
Concept Tested:
Parameterized modules, arithmetic and logic operations, control signals.
Detailed Answer:
Use a case statement inside an always block selecting operation based on an opcode, with
width parameterization for scalability.
Verilog Code:
module alu #(parameter WIDTH=8) (
input wire [WIDTH-1:0] a, b,
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input wire [2:0] op_code,
output reg [WIDTH-1:0] result
);
always @(*) begin
case(op_code)
3'b000: result = a + b;
3'b001: result = a - b;
3'b010: result = a & b;
3'b011: result = a | b;
3'b100: result = a ^ b;
default: result = 0;
endcase
end
endmodule
Tricky Aspects:
• Missing default case causing inferred latches.
• Using blocking assignments incorrectly.
• Incorrect opcode mapping.
Why MNCs Ask This:
Shows knowledge of datapath components and clean RTL coding.
Question 6
Explain the difference between wire and reg in Verilog.
Concept Tested:
Data types and assignment semantics.
Detailed Answer:
• wire: Used for continuous assignment, driven by combinational logic.
• reg: Holds value assigned in procedural blocks (always, initial).
Example:
Verilog Code
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wire a;
reg b;
assign a = b & c;
always @(posedge clk) b <= d;
Tricky Aspects:
• Misusing reg in continuous assignments or wire inside procedural blocks.
• Thinking reg always implies hardware registers (it doesn't).
Why MNCs Ask This:
Fundamental understanding of Verilog coding styles.
Question 7
Design a parameterized priority arbiter.
Concept Tested:
Priority encoding, parameterization, combinational logic.
Detailed Answer:
Grant the highest priority request among multiple inputs, using a for loop to check
requests from highest to lowest priority.
Verilog Code:
module priority_arbiter #(parameter WIDTH=4) (
input wire [WIDTH-1:0] req,
output reg [WIDTH-1:0] grant
);
integer i;
always @(*) begin
grant = 0;
for (i = WIDTH-1; i >= 0; i = i - 1) begin
if (req[i]) begin
grant[i] = 1;
disable for_loop;
end
end
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end
endmodule
Tricky Aspects:
• Forgetting to reset grant before assignment.
• Confusing MSB vs LSB priority.
• Risk of inferred latches if not careful.
Why MNCs Ask This:
Arbiters are essential in resource sharing and bus control logic.
Question 8
Explain clock domain crossing (CDC) and how to design safe CDC circuits.
Concept Tested:
Metastability, synchronizers, FIFO usage, handshake protocols.
Detailed Answer:
Crossing signals between different clocks risks metastability. For single-bit signals, use
double flip-flop synchronizers. For multi-bit data, asynchronous FIFOs or handshake
protocols are used to ensure data integrity.
Example:
Verilog Code:
module sync_flop (
input wire clk_dst,
input wire async_in,
output reg sync_out
);
reg sync_mid;
always @(posedge clk_dst) begin
sync_mid <= async_in;
sync_out <= sync_mid;
end
endmodule
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Tricky Aspects:
• Using single flip-flop synchronizer can cause metastability.
• Multi-bit data requires handshake or FIFO.
• Not considering timing constraints on synchronizers.
Why MNCs Ask This:
CDC handling is critical in complex SoCs with multiple clock domains.
Question 9
Explain the difference between blocking and non-blocking assignments with respect to
synthesis and simulation.
Concept Tested:
Simulation semantics vs synthesis behavior.
Detailed Answer:
Blocking (=) executes sequentially in simulation and is best for combinational logic
modeling. Non-blocking (<=) schedules assignments to occur at the end of the time step,
modeling registers and sequential logic. Most synthesis tools infer flip-flops only on non-
blocking assignments inside clocked always blocks.
Verilog Code:
module blocking_vs_nonblocking;
reg a, b, c;
always @(posedge clk) begin
a = b;
b = c;
end
endmodule
// Corrected version
always @(posedge clk) begin
a <= b;
b <= c;
end
Tricky Aspects:
• Using blocking assignments inside sequential always blocks can cause mismatches
between simulation and synthesis results.
• Simulation races due to incorrect usage.
• Not understanding evaluation order leading to logic bugs.
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Why MNCs Ask This:
Verilog assignment semantics are foundational to RTL coding and simulation
correctness. Misunderstanding leads to subtle bugs, incorrect synthesis, and timing
issues. Demonstrates your grasp of design best practices.
Question 10
Describe and write Verilog code for a synchronous reset and an asynchronous reset flip -
flop.
Concept Tested:
Reset types and their implementation.
Detailed Answer:
• Synchronous Reset: Reset happens on clock edge, so the reset signal is sampled by
the clock.
• Asynchronous Reset: Reset affects output immediately, independent of clock.
Verilog Code:
// Synchronous Reset Flip-Flop
always @(posedge clk) begin
if (rst) q <= 0;
else q <= d;
end
// Asynchronous Reset Flip-Flop
always @(posedge clk or posedge rst) begin
if (rst) q <= 0;
else q <= d;
end
Tricky Aspects:
• Using async reset can cause reset release metastability if not synchronized.
• Synchronous resets increase critical path delay but are easier to manage timing.
Why MNCs Ask This:
Understanding reset strategies impacts reliability and design timing.
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Question 11
Write a Verilog module to implement an 8-bit barrel shifter that can shift left or right by a
variable amount (0 to 7) based on a control signal.
Concept Tested:
Bitwise operations, shift operations, multiplexers, combinational logic, variable shifts.
Detailed Answer:
A barrel shifter shifts input bits by a variable number of positions in a single clock cycle.
The shift amount is controlled by a 3-bit signal (0–7), and the direction is controlled by a
1-bit signal (left or right). This is typically implemented using multiplexers arranged
hierarchically to reduce logic depth.
Verilog Code:
module barrel_shifter_8bit (
input wire [7:0] data_in,
input wire [2:0] shift_amt,
input wire dir, // 0 = left, 1 = right
output wire [7:0] data_out
);
wire [7:0] stage1, stage2, stage3;
// Stage 1: Shift by 1 bit
assign stage1 = dir ?
(shift_amt[0] ? {1'b0, data_in[7:1]} : data_in) : // right shift by 1
(shift_amt[0] ? {data_in[6:0], 1'b0} : data_in); // left shift by 1
// Stage 2: Shift by 2 bits
assign stage2 = dir ?
(shift_amt[1] ? {2'b00, stage1[7:2]} : stage1) :
(shift_amt[1] ? {stage1[5:0], 2'b00} : stage1);
// Stage 3: Shift by 4 bits
assign stage3 = dir ?
(shift_amt[2] ? {4'b0000, stage2[7:4]} : stage2) :
(shift_amt[2] ? {stage2[3:0], 4'b0000} : stage2);
assign data_out = stage3;
endmodule
Tricky Aspects / Common Mistakes:
• Confusing direction control (left vs right) with shift amount bits.
• Forgetting to zero-fill the shifted-in bits (should not rotate unless specified).
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• Not considering variable shifts in stages, resulting in incorrect outputs or
combinational loops.
• Assuming shifts by more than 7 bits on 8-bit data.
Why MNCs Ask This:
Tests your ability to implement efficient variable logic shifts, a common operation in
datapath design. Barrel shifters appear in ALUs, DSPs, and network processing hardware,
so mastery signals strong RTL design and combinational logic skills.
Question 12
Explain the purpose of $finish and $stop in testbenches.
Concept Tested:
Simulation control commands.
Detailed Answer:
• $stop pauses simulation and gives control to the simulator debugger.
• $finish terminates the simulation completely.
Tricky Aspects:
• Forgetting $finish in testbenches can cause simulators to run indefinitely.
• $stop can be useful for interactive debugging.
Why MNCs Ask This:
To check your familiarity with simulation environment control.
Question 13
Design a simple 2-bit Gray code counter in Verilog.
Concept Tested:
Sequential logic, coding counters, Gray code generation.
Detailed Answer:
Gray code counters change only one bit at a time, reducing transition glitches.
Verilog Code:
module gray_counter(
input clk,
input rst,
output reg [1:0] gray_out
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);
reg [1:0] bin_count;
always @(posedge clk or posedge rst) begin
if (rst)
bin_count <= 0;
else
bin_count <= bin_count + 1;
end
always @(*) begin
gray_out = (bin_count >> 1) ^ bin_count;
end
endmodule
Tricky Aspects:
• Remember to reset binary counter.
• Correct Gray code conversion logic.
Why MNCs Ask This:
Demonstrates understanding of encoding techniques and sequential logic design.
Question 14
What is the difference between initial and always blocks? Can you use initial blocks in
synthesis?
Concept Tested:
Simulation vs synthesis constructs.
Detailed Answer:
• initial: Runs once at simulation start, used for testbenches and simulation
initialization. Not synthesizable in most synthesis tools for hardware.
• always: Runs continuously, synthesizable for hardware logic.
Tricky Aspects:
• Trying to use initial blocks for RTL registers causes synthesis warnings or failures.
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• Use initial for reset in testbenches only.
Why MNCs Ask This:
To ensure you can differentiate between simulation constructs and hardware design.
Question 15
Explain the concept of signal driving strength in Verilog — wire, tri, wand, and wor.
Concept Tested:
Net types and resolution functions.
Detailed Answer:
• wire: Default net, resolved with wired-AND by default.
• tri: Like wire but indicates tri-state bus.
• wand: Wired AND net; multiple drivers ANDed together.
• wor: Wired OR net; multiple drivers ORed together.
Tricky Aspects:
• Using resolved nets for buses with multiple drivers.
• Confusing wand and wor in bus contention scenarios.
Why MNCs Ask This:
Understanding of bus structures and net resolution in complex designs.
Question 16
Describe how you would write a Verilog assertion to check that a signal valid is never high
when ready is low.
Concept Tested:
SystemVerilog assertions, design verification.
Detailed Answer:
Assertions validate design behavior. Use SystemVerilog immediate or concurrent
assertions for properties.
Verilog Code:
assert property (@(posedge clk) disable iff (!reset_n) (valid |-> ready));
Meaning: On every clock edge, if valid is high, then ready must also be high.
Tricky Aspects:
• Assertions require simulation and verification tool support.
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• Proper use of disable iff to avoid false positives during reset.
Why MNCs Ask This:
Shows ability to write robust verification constructs.
Question 17
Explain the use of generate and for loops in Verilog for parameterized hardware
generation.
Concept Tested:
Code reuse, scalability.
Detailed Answer:
Generate blocks and loops allow repetitive hardware instantiation and parameterization,
improving modularity and reducing manual errors.
Example:
Code:
genvar i;
generate
for (i=0; i<8; i=i+1) begin : gen_loop
assign out[i] = in[i] & enable;
end
endgenerate
Tricky Aspects:
• Mixing generate blocks and procedural for loops (only generate used for hardware
replication).
• Naming each generate block instance for easier debugging.
Why MNCs Ask This:
Shows modern coding practices and scalable design.
Question 18
How do you implement a synchronous reset in a register and what are the pros and cons?
Concept Tested:
Reset strategy and timing.
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Detailed Answer:
Synchronous reset is sampled by the clock, avoiding asynchronous reset release issues but
potentially increasing critical path.
Verilog Code:
always @(posedge clk) begin
if (rst) q <= 0;
else q <= d;
end
Tricky Aspects:
• Reset adds to logic delay path.
• Easier timing closure compared to async reset.
Why MNCs Ask This:
To evaluate knowledge of reset design and timing tradeoffs.
Question 19
What is the difference between case and if-else statements in Verilog? When to use each?
Concept Tested:
Control flow in RTL design.
Detailed Answer:
• case: Good for multi-way selection based on a signal value. Synthesizes into
multiplexers or decoder logic.
• if-else: Good for conditional logic and priority encoding.
Tricky Aspects:
• Incomplete case statements may infer latches. Always use default.
• Nested if-else can be less readable.
Why MNCs Ask This:
To assess clarity of RTL control flow and best practices.
Question 20
Explain Static Timing Analysis (STA) and its importance in RTL design.
Concept Tested:
Timing closure and verification.
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Detailed Answer:
STA checks timing paths in the design without simulation, ensuring no timing violations
(setup, hold) occur for all paths. Critical for verifying clock frequency feasibility and design
robustness.
Tricky Aspects:
• Defining proper clock constraints (SDC).
• Understanding false paths and multi-cycle paths.
Why MNCs Ask This:
STA knowledge is crucial for design signoff and manufacturability.
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