Faculty of Engineering and Architecture

ElectricalDeparment
and Electronics Eng. Dept.
of Computer & Computer Eng. Dept.
Engineering

EXPERIMENT 9

REGISTERS

EQUIPMENT:

1- Y-0016 main unit.

2- Integrated Circuits (ICs): Y-0016, Y-0016-006D

3. Connection wires.

DIGITAL DESIGN LABORATORY MANUAL – Experiment 9 9_1

Prof. Dr. Murat UZAM 2015
 Faculty of Engineering and Architecture
ElectricalDeparment
and Electronics Eng. Dept.
of Computer & Computer Eng. Dept.
Engineering

74LS194 UNIVERSAL SHIFT REGISTER

OBJECTIVES:
1- Learning different shift register operation principals.
2- Getting to know the 74LS194 shift register IC.
3- Observing its operation and obtaining its truth table.

PRELIMINARY INFORMATION:

The shift registers can be composed of separate ICs or they can be implemented in a single IC. The
74LS194 is a single IC universal shift register. Fig. 9.7 shows the pin definitions of the 74LS194. The
logic diagram and the truth table of the 74LS194 shift register are shown in Fig. 9.8 and in Table 9.5
respectively. When MR = 0, regardless of the all inputs the register is cleared and therefore all outputs
are forced to 0. When master reset input is not active, i.e. when MR = 1, S1 and S0 inputs are used to
select the operation mode. As can be seen from Table 9.5 there are 4 types of modes: hold, shift left,
shift right and parallel load.

When inputs S1 and S0 are 00, the outputs (Q0, Q1, Q2 and Q3) hold their previous values (Hold).

When inputs S1 and S0 are 10, the data stored in the register is shifted left with the rising edge of the
clock signal (Shift left). In this case the serial input is taken from DSL input.

When inputs S1 and S0 are 01, the data stored in the register is shifted right with the rising edge of the
clock signal (Shift right). In this case the serial input is taken from DSR input.

When inputs S1 and S0 are 11, the data in the parallel inputs P0, P1, P2, and P3 are loaded in the register
(i.e. in the flip-flops Q0, Q1, Q2 and Q3 respectively) with the rising edge of the clock signal (Parallel
load).

Fig. 9.7. Pin definitions of the 74LS194 4 bit universal shift register.

DIGITAL DESIGN LABORATORY MANUAL – Experiment 9 9_11

Page 267
Prof. Dr. Murat UZAM 2015
 Faculty of Engineering and Architecture
ElectricalDeparment
and Electronics Eng. Dept.
of Computer & Computer Eng. Dept.
Engineering

Fig. 9.8. Logic diagram of the 74LS194 shift register.

Table 9.5. The truth table of the 74LS194 shift register IC.

DIGITAL DESIGN LABORATORY MANUAL – Experiment 9 9_12

Page 268
Prof. Dr. Murat UZAM 2015
 Faculty of Engineering and Architecture
ElectricalDeparment
and Electronics Eng. Dept.
of Computer & Computer Eng. Dept.
Engineering

EXPERIMENT NO: 9.3

EXPERIMENT NAME: EXAMINATION OF THE 74LS194 UNIVERSAL SHIFT REGISTER
Equipment:
1. Y-0016 main unit.
2. Integrated Circuit (IC):
74LS194 4 bit universal shift register 1 IC
3. Connection wires.

Fig. 9.9.(a). The 74LS194 4 bit universal shift register circuit (74LS194_IC).

Note: Do not forget to connect the Vcc pin to +5 V and the GND pin to ground (GND) connection.
Fig. 9.9.(b). The 74LS194 4 bit universal shift register – application circuit.

DIGITAL DESIGN LABORATORY MANUAL – Experiment 9 9_13

Page 269
Prof. Dr. Murat UZAM 2015
 Faculty of Engineering and Architecture
ElectricalDeparment
and Electronics Eng. Dept.
of Computer & Computer Eng. Dept.
Engineering

Procedure:

1. Construct the circuit [as given in Fig. 9.9.(a) and] as drawn by you in Fig. 9.9.(b) and apply the
power.

2. Set the select inputs as S1=0 and S0=1 (the register is ready to shift right the stored data). In this
mode the data will be shifted from Q0 to Q3.

3. Set the MR input to the logic 0 state temporarily. Then set the MR input to the logic 1 state
permanently. This will clear all the outputs.

4. Set the shift right input DSR to the logic 1 state.

5. Press the PULSE button four times to generate 4 clock signals and observe the outputs Q0, Q1, Q2,
Q3.

6. Note down your observations in Table 9.6.(a).

INPUTS OUTPUTS
CLOCK MR P0 P1 P2 P3 S1 S0 DSR DSL Q0 Q1 Q2 Q3
0 0 × × × × 0 1 1 ×
1 1 × × × × 0 1 1 ×
2 1 × × × × 0 1 1 ×
3 1 × × × × 0 1 1 ×
4 1 × × × × 0 1 1 ×
×: Don’t care.
Table 9.6.(a).

7. Set the select inputs as S1=1 and S0=0 (the register is ready to shift left the stored data). In this mode
the data will be shifted from Q3 to Q0.

8. Set the MR input to the logic 0 state temporarily. Then set the MR input to the logic 1 state
permanently. This will clear all the outputs.

9. Set the shift left input DSL to the logic 1 state.

10. Press the PULSE button four times to generate 4 clock signals and observe the outputs Q0, Q1, Q2,
Q3.

11. Note down your observations in Table 9.6.(b).

INPUTS OUTPUTS
CLOCK MR P0 P1 P2 P3 S1 S0 DSR DSL Q0 Q1 Q2 Q3
0 0 × × × × 1 0 × 1
1 1 × × × × 1 0 × 1
2 1 × × × × 1 0 × 1
3 1 × × × × 1 0 × 1
4 1 × × × × 1 0 × 1
×: Don’t care.
Table 9.6.(b).

DIGITAL DESIGN LABORATORY MANUAL – Experiment 9 9_14

Page 270
Prof. Dr. Murat UZAM 2015
 Faculty of Engineering and Architecture
ElectricalDeparment
and Electronics Eng. Dept.
of Computer & Computer Eng. Dept.
Engineering

12. Set the select inputs as S1=1 and S0=1 (the register is ready to parallel load). In this mode the data
present in parallel data inputs P0, P1, P2, and P3 will be loaded to flip-flops Q0, Q1, Q2, and Q3
respectively with the rising edge of the clock signal.

13. Set the parallel data inputs as P0 = 1, P1 = 1, P2 = 0, P3 = 0.

14. Press the PULSE button once and observe the outputs Q0, Q1, Q2, Q3. Are the outputs Q0, Q1, Q2,
Q3 the same as the parallel data inputs P0, P1, P2, and P3?

15. Repeat the steps 13 and 14 for the parallel data input values provided in Table 9.6.(c) and then note
down the output values in the Table.

INPUTS OUTPUTS
CLOCK MR P0 P1 P2 P3 S1 S0 DSR DSL Q0 Q1 Q2 Q3
1 1 1 1 0 0 1 1 × ×
2 1 1 1 0 0 1 1 × ×
3 1 0 1 1 0 1 1 × ×
4 1 0 1 1 0 1 1 × ×
5 1 1 1 1 1 1 1 × ×
6 0 1 1 1 1 1 1 × ×
×: Don’t care.
Table 9.6.(c).

DIGITAL DESIGN LABORATORY MANUAL – Experiment 9 9_15

Page 271
Prof. Dr. Murat UZAM 2015