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Digital Electronic Circuits
Assignment- Week 1
TYPE OF QUESTION: MCQ/MSQ
Number of questions: 15 Total mark: 15 X 1 = 15
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QUESTION 1:
Which of the following statements are FALSE about CMOS logic?
(i) CMOS has very high input resistance and hence ∑draws very low current.
(ii) CMOS has high fan-out as compared to TTL.
(iii) CMOS is generally faster than TTL.
(iv) CMOS has low packing density.
(v) CMOS exhibits low power consumption.
a. (i), (iii), (iv)
b. (i), (ii), (iii), (v)
c. (i), (ii), (v)
d. (iii), (iv)
Correct Answer: d)
Detailed Solution:
CMOS circuit generally have higher propagation delay that TTL circuits.
CMOS circuits have higher packing density than TTL circuits.
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QUESTION 2:
Consider the following circuit. What is the output Y (1 or 0) if all the inputs (A, B, C and D) are at
logic LOW (0)?
Q5
C D
A B
Correct Answer: 1 (Logic HIGH)
Detailed Solution:
The given circuit is a combination of two multi-emitter transistors with the totem pole
configuration. When any of Q3 or Q4 is ON (i.e., both of the input to multi-emitter transistor Q1
or Q2 is HIGH), output Y is OFF (low potential). Hence, when all inputs are at logic 0 (LOW)
transistors Q3 and Q4 are both OFF which keeps transistor Q5 at ON state and Q6 at OFF state.
This will connect the output Y to Vcc through transistor Q5 providing 1 (HIGH) at the output.
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QUESTION 3:
Which of the following statements are TRUE?
1) In TTL circuits, the rise time (tr) should be low but fall time (tf) can be high
2) In CMOS circuits, the fall time should be low but the rise time can be high
3) Both rise time and fall time of a DTL circuit should be as high as possible
4) The figure of merit (F) of a TTL circuit should be as low as possible
5) The average power dissipation of any logic family circuit should be as low as possible
a) 1, 2, 4 and 5
b) 1, 2 and 5
c) 3, 4 and 5
d) 4 and 5
Correct Answer: d)
Detailed Solution:
Refer Lecture 03 (Slide 3 and 4) of Digital Electronic Circuits, NPTEL Online Certification Course
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QUESTION 4:
In the following circuit, why is the resistor (R3) used across base emitter junction? Also, what
should be the ideal value of resistor R3?
a) R3 increases the output resistance of the transistor circuit; R3 should be as high as
possible
b) R3 only performs proper biasing of transistor; R3 should be as low as possible
c) R3 is used to reduce propagation delay and proper biasing of transistor; R3 should be as
low as possible
d) R3 is used as a level-shifter; R3 should be as high as possible
Correct Answer: c)
Detailed Solution:
Refer Lecture 03 (Slide 8) of Digital Electronic Circuits, NPTEL Online Certification Course
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QUESTION 5:
In the following circuit, find the value of voltage at the collector terminal when both the input A
and B are at HIGH voltage (+5V). Consider current amplification factor of transistor to be equal
to 100. Voltage drop across diode is 0.7V, 𝑉CC = 5𝑉, 𝑅1 = 1KΩ, 𝑅2 = 500Ω, 𝑅3 = 10Ω and
𝑉𝐶𝐸(𝑠𝑎𝑡) = 0.2𝑉..
a) -24V
b) 5V
c) 0.2V
d) 0.7V
Correct answer: c)
Detailed Solution:
The given circuit is a DTL NAND gate. When all inputs are high, current flows through the
transistor base making it ON since no current flows through the diode
Let us assume that the transistor is operating in the active region.
𝑉𝑐𝑐 − 0.7 − 0.7 − 𝑉𝐵𝐸 5 − 2.1
𝐼𝐵 = = = 2.9 𝑚𝐴.
𝑅1 1
𝐼𝐶 = 𝛽𝐼𝐵 = 100 × 2.9 = 290 𝑚𝐴. 𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐶 𝑅2 = 5 − 290 × 0.5 < 𝑉𝐶𝐸(𝑠𝑎𝑡) .
Hence, the transistor will operate in saturation region with 𝑉𝐶𝐸 = 0.2 such that it operates in
saturation region. Hence correct option is c
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Note: IC=β*IB does not hold true in saturation region (the relation in saturation region is more
close to IC<β *IB).
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QUESTION 6:
Consider the following circuit: The input output pairs are A, B and X, Y. Suppose X and Y are
passed through another ‘unknown gate’ as shown below. Which gate should the ‘unknown
gate’ be such that output Z = A⨁B.
X Unknown
Z
Y Gate
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a) OR/XOR gate
b) AND gate
c) OR/XNOR gate
d) NAND gate
Correct Answer: a)
Detailed Solution:
Here, X = A’B and Y = AB’. Hence, when unknown gate is OR gate or XOR gate, we get, X⨁Y.
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QUESTION 7:
In the given circuit, 𝑉𝐶𝐸(𝑆𝑎𝑡) = 0.2 V, 𝛽𝐹 = 50, 𝑉𝐵𝐸(𝑂𝑁) = 𝑉𝐵𝐸(𝑆𝑎𝑡) = 0.7 V, 𝑉𝐼𝐻 = 1.5 V. Compute the
fan-out when (i) noise margin high (𝑁𝑀𝐻 ) = 0 V and (ii) noise margin high (𝑁𝑀𝐻 ) = 0.8 V.
a) 43 and 16
b) 42 and 15
c) 40 and 10
d) 44 and 17
Correct Answer: a)
Detailed Solution:
When 𝑉𝑖𝑛 is HIGH, driver-transistor is saturated and 𝑉𝑜𝑢𝑡 will be LOW. With 𝑉𝐶𝐸(𝑆𝑎𝑡) = 0.2V all
the load transistors will be in the OFF state.
When 𝑉𝑖𝑛 is LOW, driver-transistor will be OFF and 𝑉𝑜𝑢𝑡 will be at HIGH level. A limit in the fan-
out is set when the voltage at 𝑉𝑜𝑢𝑡 is insufficient to saturate load gate transistors.
(i) When 𝑉𝐼𝐻 = 1.5 V with noise margin=0,
𝑉𝑜𝑢𝑡 = 𝑉𝑂𝐻 = 𝑉𝐼𝐻 + 𝑁𝑀𝐻 =1.5+0 = 1.5V
𝐼𝐶 (Driver)= (𝑉𝐶𝐶 –𝑉𝑜𝑢𝑡 )/ 𝑅𝐶 = (5 -1.5)/1K = 3.5mA
𝐼𝐵 (Load)= (𝑉𝑜𝑢𝑡 –𝑉𝐵𝐸(𝑆𝑎𝑡) )/ 𝑅𝐵 = (1.5 -0.7)/10K = 0.08mA
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𝐼𝐶 (Driver) 3.5
N= = =43.75 ≈ 43
𝐼𝐵 (Load) 0.08
(ii) When Noise margin high (𝑁𝑀𝐻 ) = 0.8V
𝑉𝑜𝑢𝑡 = 𝑉𝑂𝐻 = 𝑉𝐼𝐻 + 𝑁𝑀𝐻 = 1.5+0.8=2.3V
𝐼𝐶 (Driver)= (𝑉𝐶𝐶 –𝑉𝑜𝑢𝑡 )/ 𝑅𝐶 = (5 -2.3)/1=2.7mA
𝐼𝐵 (Load)= (𝑉𝑜𝑢𝑡 –𝑉𝐵𝐸(𝑆𝑎𝑡) )/ 𝑅𝐵 = (2.3 -0.7)/10=0.16mA
𝐼𝐶 (Driver) 2.7
N= = = 16.87≈ 16
𝐼𝐵 (Load) 0.16
Hence, fan-out decreases with increase in noise margin.
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QUESTION 8:
For the given TTL circuit shown in the figure below, find the current flowing through the
collector of transistor Q4, when Vo=0.2 volts. Assume VCE(sat)=0.2 volts, β= 100 and
VBE(sat)=0.7 volts. The α of Q1 in its reverse active mode is 0.01.
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a) 0.205mA
b) 2.05mA
c) 205mA
d) 20.5mA
Correct Answer: a)
Detailed Solution:
Q1 is operating in the inverse active mode. Base-Emitter junction is reverse bias and base-
collector junction is active bias. No current flows through base-emitter junction. Entire current
flows through base-collector junction which makes Q4 in ON condition hence making Q3 in ON
condition. The output side is totem pole configuration so when Q3 is ON, Q2 will be in OFF
condition.
IC of Q4= I(through 20k)-IB of Q2 (IB of Q2 =0 as Q2 is off )
Collector voltage of Q4=0.2 (VCE(sat))+0.7(VBE of Q3)= 0.9 V
Voltage drop=5-0.9=4.1 V.
Ic of Q4=4.1/20K= 0.205 mA.
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QUESTION 9
Consider the following circuit diagram. Which of the following correspond to the proper choice
of the inputs A and B, so that the light is turned ON?
(i) A=1; B=1
(ii) A=1; B=0
(iii) A=0; B=1
(iv) A=0; B=0
Choose the correct option.
a) (i) and (ii)
b) (ii) and (iii)
c) (iii) and (i)
d) (iv) and (i)
Correct Answer: d)
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Detailed Solution:
From the circuit diagram, it is clear that the LED will glow when Z = LOW and Z will be LOW only
when X or Y or both will be HIGH. Now, we consider the different input conditions as,
1. If A= B = 1 X = 1 and Y = 0 Z = 0; LED glows.
2. If A= B= 0 X = 0 and Y = 1 Z = 0; LED glows.
3. If A = 0, B = 1 X = 0 and Y = 0 Z = 1; LED doesn’t glow.
4. For A = 1, B = 0 X = 0 and Y = 0 Z = 1; LED doesn’t glow.
QUESTION: 10
In Schottky TTL logic, the Schottky diode registers ________ voltage drop in forward bias,
resulting in __________ propagation delay for logic circuits.
a. Lower, Lower
b. Lower, Higher
c. Higher, Lower
d. Higher, Higher
Correct Answer: a)
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Detailed Solution:
The voltage across a conducting Schottky diode is only 0.4 V, compared with 0.7 V in a
conventional diode. The presence of a Schottky diode between the base and collector prevents
the transistor from going into saturation. This results in a reduction in propagation
delaybecause the time needed for a transistor to come out of saturation delays the switching of
the transistor from the ON to the OFF condition. Hence, the use of Schottky transistors in a TTL
decreases the propagation delay, without sacrificing power dissipation.
(Pg. 504, Digital Design, Mano &Ciletti, 4th Edition)
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QUESTION 11:
Which logic operation is described by the following circuit?
a. NOT gate
b. NAND gate
c. AND gate
d. No logic operation (Input=Output)
Correct Answer: b)
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Detailed Solution:
In the given circuit, current will flow through the two NMOS transistors only when the input to
both the transistors is HIGH. If input to any of the NMOS is LOW, the corresponding transistor is
OFF and no current flows through transistors keeping output at HIGH voltage value.
QUESTION 12:
The role of level-shifter diodes in DTL is to:
a. Increase VIL
b. Increase VIH
c. Decrease VIL
d. Decrease VIH
Correct Answer: a)
Detailed Solution: The role of level-shifter diodes in DTL is to increase low input voltage.
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QUESTION 13:
When the emitter of the input transistor (T1) of a TTL NOT gate is at HIGH logic, the transistor
(T1) operates in:
a. Saturation mode
b. Cutoff mode
c. Active mode
d. Inverse active mode
Correct Answer: d)
Detailed Solution:
When the emitter of transistor is at HIGH logic, the transistor operates in reverse active mode.
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QUESTION 14:
If power dissipation and propagation delay in a logic circuit are estimated to be 50 mW and
25ns respectively, what will be its figure of merit?
a. 0.5 pJ
b. 1.25 pJ
c. 1.25 nJ
d. 2 nJ
Correct Answer: c)
Detailed Solution: Figure of merit: Power dissipation* propagation delay
FOM = 50mW * 25ns = 1.25 nanojoule.
Lower the Figure of merit the better is the circuit.
QUESTION 15:
For a given logic family, consider VOL=0.9 Vand VOH= 4.5 V. For a given circuit, VIL= 1.2 Vand VIH=
3.2 V. Find the noise margins (NML and NMH). Is it functionally better than a circuit with VIL=1.5
V and VIH= 3 V? (Yes/No)
a. 𝑁𝑀𝐿 = 0.24 𝑉, 𝑁𝑀𝐻 = 1.25𝑉, 𝑌𝑒𝑠
b. 𝑁𝑀𝐿 = 1.75 𝑉, 𝑁𝑀𝐻 = 4.76 𝑉, 𝑌𝑒𝑠
c. 𝑁𝑀𝐿 = 1.3 𝑉, 𝑁𝑀𝐻 = 3 𝑉, 𝑁𝑜
d. 𝑁𝑀𝐿 = 0.3𝑉, 𝑁𝑀𝐻 = 1.3 𝑉, 𝑁𝑜
Correct Answer: d)
Detailed Solution:
Given, VOL= 0.9 Vand VOH= 4.5 V
For 1st circuit, VIL= 1.2 Vand VIH= 3.2 V
NML = VIL – VOL= 1.2 – 0.9 = 0.3 V
NMH= VOH – VIH = 4.5 – 3.2 = 1.3 V
For 2nd circuit, VIL= 1.5 Vand VIH= 3 V
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NML = VIL – VOL= 1.5 – 0.9 = 0.6 V
NMH= VOH – VIH = 4.5 – 3 = 1.5 V
No, the 2nd circuit is functionally better than the 1st circuit due to its higher noise margins.
QUESTION 16:
Consider the following CMOS circuit and identify the output 𝑉𝑂𝑈𝑇 .
a) ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅ + 𝐸)(𝐴 + 𝐵)
(𝐶𝐷
b) ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅
(𝐶 + 𝐷 )𝐸 + 𝐴𝐵
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
c) (𝐶 + 𝐷)𝐸 + 𝐴𝐵
d) ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅ + 𝐸)(𝐴 + 𝐵)
(𝐶𝐷
Correct Answer: c
Detailed Solution
This is a complementary PMOS and NMOS structure.
Considering the NMOS part,
𝐴 and 𝐵 are in series which represent 𝐴𝑁𝐷 operation, i.e. 𝐴𝐵.
𝐶 and 𝐷 are in parallel which represent 𝑂𝑅 operation, i.e. (𝐶 + 𝐷).
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Also, (𝐶 + 𝐷) and 𝐸 are joined by 𝐴𝑁𝐷 operation and (𝐶 + 𝐷)𝐸 is joined by 𝑂𝑅 with 𝐴𝐵. The
resultant will be complemented by the 𝑁𝑂𝑇 operation due to the complementary nature of the
CMOS configuration. Hence,
𝑽𝑶𝑼𝑻 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
(𝐶 + 𝐷)𝐸 + 𝐴𝐵
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