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Digital Electronic Circuits
Assignment- Week 4
TYPE OF QUESTION: MCQ/MSQ
Number of questions: 15 Total mark: 15 X 1 = 15
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QUESTION 1:
How many 2:1 multiplexers are required to generate 256:1 multiplexer?
a. 127
b. 128
c. 255
d. 256
Correct Answer: c
Detailed Solution:
For example, Number of 2:1 MUX requires implementing 256:1 MUX is:
𝑅𝑒𝑞𝑢𝑖𝑟𝑒𝑑 𝑛𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑖𝑛𝑝𝑢𝑡𝑠 256
: = 128 (1st stage)
𝐺𝑖𝑣𝑒𝑛 𝑛𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑖𝑛𝑝𝑢𝑡𝑠 2
128
= 64 (2nd stage)
2
64
= 32 (3rdstage)
2
32
= 16 (4th stage)
2
16
= 8 (5th stage)
2
8
= 4 (6th stage)
2
4
= 2 (7th stage)
2
2
= 1 (Final stage)
2
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Total number of 2:1 MUX is required to generate 256:1 MUX is: 128+64+32+16+8+4+2+1=255
Similarly, 2n-1number of 2:1 multiplexer is required to generate 2n:1multiplexer.
(Refer to NPTEL online certification course, Lecture 16, slide-9, Multiplexer: 1, Higher order
MUX from lower order).
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QUESTION 2:
Number of select lines required in 1: 8192 DEMUX is _____
a. 8192
b. log(8192)
c. log(213)
d. 13
Correct Answer: d
Detailed Solution:
A de-multiplexer having m select lines and n output lines satisfy the relation 2m = n or m =
log2n=13
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QUESTION 3:
Find the canonical POS expression of Y for the given figure.
a. π M(0, 1, 4, 6, 10, 11, 13, 14, 15)
b. π M(0, 1, 4, 7, 9, 11, 13, 14, 15)
c. π M(2, 3, 5, 7, 8, 9, 12)
d.π M(2, 3, 6, 8, 9, 10, 12)
Answer: a
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Detailed Solution:
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QUESTION 4:
The following circuit diagram, the propagation delay of the multiplexer, NOR gate, and inverter
are 1.5ns, 2ns, and 1ns respectively. If all the inputs P, Q, R, S, and T are applied at the same
time, calculate the maximum possible propagation delay (in ns) to the output Y.
a. 4 ns
b. 5 ns
c. 6 ns
d. 7ns
Correct Answer: c
Detailed Solution:
When T=0,
propagation delay = delay in NOR gate + delay in 1st MUX + delay in 2nd MUX
= (2+1.5+1.5) = 5ns
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When T=1,
propagation delay = delay in NOT gate + delay in 1st MUX + delay in 2nd NOR gate + delay in 2nd
MUX
= (1+1.5+2+1.5) = 6ns
Maximum propagation delay is 6ns.
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QUESTION 5:
Considering the following pin configuration of IC, If A=0, and B=C=0 then what will be the
function of the IC?
a. 1-to-4 DEMUX with outputs on Y0 to Y4
b. 1-to-4DEMUX with output on Y16 to Y19
c. 1-to-16 DEMUX with outputs on Y0 to Y15
d. 1-to-16DEMUX with output on Y16 to Y31
Correct Answer: a
Detailed Solution:
If A = 0 and B=C=0, select inputs will steer the DATA input to one of Y0 and Y4
Output: 1-to-4 DEMUX.
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(Refer to De-multiplexer/ Decoder, lecture 18, slide no.7, NPTEL online certification courses)
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QUESTION 6:
Determine the inputs of the given 4 : 1 multiplexer to make the output Q = A+B+C, where A is
MSB and C is LSB. Use A and B as select lines and C as input variable.
a. D0= C, D1 = 1, D2 =1, D3 = 1
b. D0= C’, D1 = 1, D2 =1, D3 = 1
c. D0= C, D1 =C’, D2 =1, D3 = 1
d. D0= C’, D1 = C, D2 =1, D3 = 1
Correct Answer: a
Detailed Solution:
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QUESTION 7:
Which of the following statements are not true?
1. For more than 2-input Ex-NOR gate, output is 1 if there are odd no. of 1s at input.
2. Even parity refers to presence of even no. of 1s in bit patterns and odd parity refers to odd
no. of 1s.
3. Parity generation and checking involve single-input Ex-OR gate circuit.
4. Parity check is useful in detection of error when a group of bits is transmitted.
a. 1 and 4
b. 2 and 3
c. 2 and 4
d. 1 and 3
Correct answer: d
Detailed Solution:
For more than 2-input Ex-OR gate, output is 1 if there are odd no. of 1s at input.
Parity generation and checking involve multi-input Ex-OR gate circuit.
(Refer slide 12, Lecture 20,NPTEL online certification courses)
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QUESTION 8:
Realize the following Boolean expression F (A,B,C,D)= ∏M (4,8,9,10,11,14) using 4:1
multiplexer, where C,D are select lines.
a. I0 = AB+A’B’, I1 = A+B’, I2 = A’, I3 =I0
b. I0 = AB+A’B’, I1 = A’+B, I2 = A’, I3 =I1
c. I0 = A’B+AB’, I1 = A+B’, I2 = A, I3 =I1
d. I0 = A’B+AB’, I1 = A’+B, I2 = A, I3 =I0
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Correct Answer: b
Detailed Solution:
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QUESTION 9:
What should be the value of D0, D1,…, D7 so that the minimized output F= A+BC:
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a) 0,1,1,0,1,1,0,1
b) 0,0,0,1,1,1,1,1
c) 1,1,0,1,0,1,0,1
d) 1,0,1,1,0,1,0,1
Correct Answer: b
Detailed Solution:
The given MUX arrangement can be written in SOP form as,
F=A’B’C’D0+A’B’CD1+A’BC’D2+A’BCD3+AB’C’D4+AB’CD5+ABC’D6+ABCD7.
The output for three inputs, A, B and C can be given as,
A B C F = A+BC
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
Hence, min-term expression which follows A+BC is,
F=A’BC+AB’C’+AB’C+ABC’+ABC
To implement the given min-term expression,
D0=0, D1=0, D2=0, D3=1, D4=1, D5=1, D6=1, D7=1
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(Refer to NPTEL online certification course, Lecture 16, Multiplexer: part 1, Shanon’s
Expansion Theorem and MUX).
QUESTION 10:
If the input to the circuit X3,X2,X1,X0 are in 8-4-2-1 BCD numbers then the output Y3,Y2,Y1,Y0 are in
which of the following options? Consider Y3,Y2,Y1,Y0 as output of OR gate whose input is given by
'X' (cross sign).
a) Grey code number
b) 2-4-2-1 BCD number
c) Excess-3 code number
d) Binary number
Correct Answer: b
Detailed Solution:
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The output is in 2-4-2-1 BCD format.
QUESTION 11:
An even-parity checker indicates a parity error for which of the following received data and
parity bit? Choose the correct option.
i. Data = 1111111 Parity = 1
ii. Data = 1001001 Parity = 0
iii. Data = 1110000 Parity = 1
iv. Data = 0000000 Parity = 1
v. Data = 1100111 Parity = 1
vi. Data = 1111110 Parity =0
a) (ii) and (vi)
b) (i), (iii), (iv) and (v)
c) (ii) and (iv)
d) (i), (iii), (v) and (vi)
Correct Answer: c
Detailed Solution:
The data is transmitted with even parity. So, the data and parity bits received at circuit must
have an even number of 1’s
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i. Received data = 11111111; Even number of 1’s –No Parity Error
ii. Received data = 10010010; Odd number of 1’s –Parity Error
iii. Received data = 11100001; Even number of 1’s –No Parity Error
iv. Received data = 00000001; odd number of 1’s – Parity Error
v. Received data = 11001111; Even number of 1’s –No Parity Error
vi. Received data = 11111100; Even number of 1’s –No Parity Error
QUESTION 12:
Find the correct expression for the outputs (Consider Q0 : LSB Q2 : MSB)
a. Q0 = D6’(D4’D2’D1 + D4’D3 + D5 ) + D7
Q1 = D4 + D5 + D6 + D7
Q2 = D5’D4’ (D2 + D3) + D6 + D7
b. Q0 = D6’(D4’D2’D1 + D4’D3 + D5 ) + D7
Q1 = D5’D4’ (D2 + D3) + D6 + D7
Q2 = D4 + D5 + D6 + D7
c. Q0 = D6(D4’D2’D1 + D4D3 + D5 ) + D7
Q1 = D5’D4’ (D2 + D3) + D6 + D7
Q2 = D4 + D5 + D6 + D7
d. Q0 = D6(D4’D2’D1 + D4D3 + D5 ) + D7
Q1 = D4 + D5 + D6 + D7
Q2 = D5’D4’ (D2 + D3) + D6 + D7
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Correct Answer: b
Detailed Solution:
Digital Inputs Binary Output
D7 D6 D5 D4 D3 D2 D1 D0 Q2 Q1 Q0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 X 0 0 1
0 0 0 0 0 1 X X 0 1 0
0 0 0 0 1 X X X 0 1 1
0 0 0 1 X X X X 1 0 0
0 0 1 X X X X X 1 0 1
0 1 X X X X X X 1 1 0
1 X X X X X X X 1 1 1
Q0 = ∑m (1, 3, 5, 7) = D7’ D6’D5’ D4’D3’D2’D1 + D7’ D6’D5’ D4’D3 + D7’ D6’D5 + D7
= D6’ D4’D2’D1 + D6’D4’D3 + D6’D5 + D7
= D6’(D4’D2’D1 + D4’D3 + D5 ) + D7
Q1 = D5’D4’ (D2 + D3) + D6 + D7
Q2 = D4 + D5 + D6 + D7
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QUESTION 13:
What should be the min-term expression at the output of the given circuit?
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a) F = Σ m(0,2,3,4,6,7,8,9,10,11,12,13,14,15)
b) F = Σ m(0,1,2,3,4,6,7,8,9,10,11,12,13,14,15)
c) F = Σ m(1,4,11)
d) F = Σ m(0,2,5)
Correct Answer: b
Detailed Solution:
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QUESTION 14:
From the given circuit shown below, find out the correct option for the output Y2.
a) Y2 = PQ’
b) Y2 = (PQ)’
c) Y2 = P’
d) Y2 = P’Q
Correct Answer: c
Detailed Solution:
D0 = I1I0 = (P’+Q)’.(PQ)’
= (P.Q’).(PQ)’
= (PQ’).(P’+Q’) = PQ’
D2 = I1.I0’ = (P’+Q).(PQ)’
= (P’+Q).(P’+Q’)
= P’+P’Q’+P’Q’+0
= P’[1+Q’+Q]
= P’
Y1 = D0+D2
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= (PQ’)+P’ = (P’+Q’) = (PQ)’
The second decoder is active low decoder, hence,
D5 = I3+I2
= ((PQ)’+P’)
= P’+Q’
D7 = I3’ +I2’
= (PQ)’’+P’=PQ+P’ = P’+Q
Y2 = (P’+Q’).(P’+Q) = P’
QUESTION 15:
Correct Answer: c
Detailed Solution:
NAND gate:
NOR gate:
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(A+B)’
EX-OR gate:
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