Full custom design + In Full-Custom ASIC, all the logic cells, circuits and layouts are designed specifically for that particular ASIC from the ground up. + Chosen iff, either the existing libraries are not fast enough or the logic cells are not small or the power consumption is high. » Advantage : it delivers the highest possible performance at the smallest possible die size. * Disadvantage: High performance and small size comes at a price of increased design time, complex design and overall cost of the IC itself. *Examples : Microprocessors, Memories, Analog Processors, Analog/ Digital Communication devices, Sensors, Transducers, high- voltage ICs for Automobiles, etc.Semi custom Design : Gate Arrays + In Gate Array based ASICs, p and n types transistors are predefined on a silicon wafer as arrays. + Based on the design from the customer and the interconnections obtained from the design, the silicon vendor provides these base wafers. + Thus , the base wafer is specific to the customer as it is designed based on the customer provided connections between the transistors of the gate array. + The gate arrays are again divided into two types called the Channelled Gate Array and the Channel-less Gate Array. + In channelled gate arrays, the interconnections between the logic cells are performed within the predefined channels between the rows of the logic cells. + In case of channelless gate arrays, the connections are made on an upper metal layer on top of the logic cells.Semi custom Design : Cell Based +A Standard Cell based ASIC uses predesigned logic cells like Gates, Multiplexers, Flip-flops, Adders etc. + These logic cells are known as Standard Cells that are already designed and stored in a library. + This library is imported into the CAD tool and the design can performed using the Components of the library as inputs. + Typically, Standard Cell based designs are organised as rows of constant height cells on the chip, just like a row of bricks. + When combined with logic-level components, standard cell-based designs gan be used to implement complex functions like Multipliers and Memory rays. * The standard cell design may also contain a larger and more complex predesigned cells like Microcontrollers or Microprocessors. These larger cells are called as Megacells. NM cH | =Full Custom Vs Semi Custom (1/2) Full Custom Semi CustomFull Custom Vs Semi Custom (2/2) Full-custom Design longer design time until “maturity” Semi-custom Design More Opportunities . Less Opportunities for performance Shorter design for performance improvement time until y improvement “maturity” Circuit PerformanceASIC Design Flow Gees Pile) | EE _ eed Packaging & testing HULL raFront End Design Design Entry: |n the step, the logic design is created using a Hardware Description Language (HDL) like VHDL or Verilog HDL or with the help of Schematic entry. RTL verification :In this step conformance of RTL Design to specification is verified. * To answer the question "Does this proposed design do what is intended?“ * RTL verification is a complex task, and takes the majority of time and effort in most VLSI Projects + Itis complex because of the sheer volume of > test-cases that exist in even a simple design. ( <<Back End Design Steps (1/4) + Logic synthesis: The RTL is mapped into a gate-level netlist in the target technology of the chip. + DFT: The technique which facilitates a design to become testable after production. + Extra logic is along with the design logic during implementation process which helps post production process. * The DFT will make the testing easy at post production process Floor planning: The process of determining the macro placement, power grid generation and I/O placement. + Places blocks/macros in the chip/core area there by determining routing areas between them. + It determines the size of the die and creates wire tracks for placement of standard cells. + It also determines the I/O, pin/pad placement information. 7 |Back End Design Steps (2/4) + Placement: The gates in the net list are assigned to non-overlapping locations on the die area. + Logic/placement refinement: Iterative logical and placement transformations to achieve performance and power constraints. + Clock Tree Synthesis: The clock tree is built using inverters and buffers. For balancing the clock skew and minimising insertion delay in order to meet timing and power. + Routing: The wires that connect the gates in the net list are added. + Sign-off: Performance (timing closure), noise (signal integrity), and yield (Design for manufacturability) violations are removed.Back End Design Steps (3/4) + Design for manufacturability: The design is modified, where possible, to make it as easy and efficient as possible to produce. + This is achieved by adding extra vias or adding dummy (metal/diffusion/poly) layers wherever possible, while complying to the design rules, set by the foundry. + Packaging & Testing: Since errors are expensive, time-consuming and hard to spot, extensive testing is done, making sure the mapping to logic was done correctly, and packaging the chip following manufacturing rules. + Post Silicon Validation: involves operating one or more manufactured chips in actual application environments to validate correct behaviors over specified operating conditions + Chip Tape-out: the design data is turned into photomasks in mask data preparation.ASIC Vs FPGA exw» a | > — 4 weeks for fab) of MHz) High unit cost (S1,000's) ‘Comments *Oftenused for | « Especially useful FPGA shrink in markets that change fast or have low volumesFPGA -A Conceptual View = An FPGA is like an electronic breadboard that is wired together by an automated synthesis tool = Built-in components are called macros‘FPGA —AN inside Took aFPGA Based Design — Xilinx Flow Design [Design Verteaton ay -}———5 Berard —— Simdaton Design } Syntesis Furctonal [TP Lsindaton Design (tae Ting Implementation | Anaya LT ba Toning ‘Ancataton [| Simulation | Programming | Nericatonesource (1/2): IEEE Standards IEEE Standard for Verilog Hardware Description Language," in /EEE Std 1364-2005 (Revision of IEEE Std 1364-2001) , vol., no., pp.1-590, 7 April 2006, doi: 10.1109/IEEESTD.2006.99495. IEEE Standard for System Verilog--Unified Hardware Design, Specification, and Verification Language," in IEEE Std 1800-2017 (Revision of IEEE Std 1800-2012) , vol., no., pp.1-1315, 22 Feb. 2018, doi: 10.1109/ IEEESTD.2018.8299595.