VLSI and Chip Design Department of ECE 2023-24

UNIT – I
INTRODUCTION - BASIC MOS TRANSISTOR

The invention of the transistor by William B. Shockley, Walter H. Brattain and John Bardeen
of Bell Telephone laboratories was followed by the development of the Integrated circuit (IC)
The very first IC emerged at the beginning of 1960 and since that time there have already
been 4 generations of ICs
1) SSI ( Small Scale Integration)
2) MSI ( Medium Scale Integration)
3) LSI ( Large Scale Integration)
4) VLSI ( Very Large Scale Integration)
Now we see the emergence of the 5th generation, ULSI ( Ultra Large Scale Integration) which
is characterized by complexities in excess of 3 million devices on a single IC [Link] the bounds of
MOS technology, the possible circuit realizations may be based on pMOS, nMOS, CMOS and now
BiCMOS devices. Although CMOS is the dominant technology, some of the examples used to illustrate
the design processes will be presented in nMOS form. The reasons are :
1) For NMOS technology, the design methodology and the design rules are easily learned, thus
providing a simple but excellent introduction to structured design for VLSI.
2) nMOS technology and design processes provide an excellent background for other
technologies. In particular some familiarity with nMOS allows a relatively easy transition to CMOS
technology and design.
3) For GaAs technology some arrangements in relation to logic design are similar to those
employed in nMOS technology. Therefore, understanding the basics of nMOS design will assist in the
layout of GaAs circuits.

BASIC MOS TRANSISTORS

nMOS devices are formed in a p-type substrate of moderate doping level. The source and drain regions
are formed by diffusing n-type impurities through suitable masks into 3 areas to give the desired n-
impurity concentration and give rise to depletion regions which extend mainly in the more lightly doped
p-region.
• Thus, source and drain are isolated from one another by 2 diodes.
• Connections to the source and drain are made by a deposited metal layer. . ( Fig a)
• A polysilicon gate is deposited on a layer of insulation over the region between source and drain

• If the gate is connected to a suitable positive voltage with respect to the source, then the electric
field established between the gate and the substrate gives rise to a charge inversion region in the
substrate under the gate insulation and a conducting path or channel is formed between source and drain.
• Channel may also be established so that it is present under the condition Vgs = 0 by implanting
suitable impurities in the region between the insulation and the gate. (fig b)

• Substrate is of n-type material and the source and drain diffusions are consequently p-type.(fig c)

[Link]’s College of Engineering/[Link]’s Institute of Technology 1

VLSI and Chip Design Department of ECE 2023-24
ENHANCEMENT MODE TRANSISTOR ACTION:
• In order to establish the channel in the first place a min. voltage level of threshold voltage Vt
must be established between gate and source.
• Fig (a) indicates the conditions
prevailing with the channel establishedbut
no current flowing between source and
drain (Vds = 0)
• Condition: When current flows in the
channel by applying a voltage Vds between
drain and source.
• Corresponding IR drop = Vds along the
channel.
• This results in the voltage between gate
and channel varying with distance along
the channel with the voltage being a max.
ofVgs at the source end.
• Effective voltage Vg = Vgs-Vt, there will
be voltage available to invert the channel
at the drain end so long as Vgs – Vt>= Vds.
• Limiting condition comes when Vds =
Vgs – Vt.
• For all voltages Vds<Vgs – Vt, the device
is in the non-saturated region of operation.
• IR drop = Vgs –Vt takes place over less
than the whole length of the channel so
that over part of the channel, near the
drain, there is insufficient electric field
available to give rise to inversion layer to
create the channel.
• Diffusion current completes the path
from source to drain causing the channel
to exhibit a high resistance known as
saturation region.

DEPLETION MODE TRANSISTOR ACTION

• The channel is established, due to the implant, even when Vgs = 0 and to cause the channel to cease
to exist a –ve voltage Vtd must be applied between gate and source.
Vtd is typically < -0.8Vdd, depending on
the implant and substrate bias, but
threshold voltage differences apart.

Drain to source current Ids versus voltage Vds relationships

• The whole concept of the MOS transistor evolves from the use of a voltage on the gate to induce a
charge in the channel between source and drain, which may then be caused to move from source to
drain under the influence of an electric field created by voltage Vds applied between source and drain.
• Since the charge induced is dependent on the gate to source voltage Vgs then Igs is independent on both
Vgs and Vds.
• Consider a structure in which electrons will flow from source to drain.

= , First, transit time ζ sd

But velocity , Where μ = electron or hole mobility (surface) Eds = electric field (drain to
source) ;
Now , So that , Thus,
Typical values of μ at room temp. areμn = 650 cm /Vsec ( surface) μp = 240 cm2/Vsec (surface)
2

Non Saturated region:

[Link]’s College of Engineering/[Link]’s Institute of Technology 2

 VLSI and Chip Design Department of ECE 2023-24
• Charge induced in channel due to gate voltage is due to to the voltage difference between the gate
and the channel Vgs
• Voltage along the channel varies linearly with distance X from source due to the IR drop in the
channel.
• Assuming the device is not saturated then the average value is Vds/2
• Effective gate voltage Vg = Vgs-Vt, Where Vt is the threshold voltage needed to invert the charge
under the gate and establish the channel.
, Thus induced charge , Where
Eg= avg. electric field gate to channel
εins = relative permittivity of insulation between gate and channel
ε0 = permittivity of free space = 8.85x10-14 Fcm-1
Where D = oxide thickness
Thus 3
Combine eqn 2 & 3 in 1 , we have
or in the non saturated or resistive region where Vds<Vgs - Vtand
/D
The factor W/L is of course contributed by the geometry and it is a common practice to write
 = K. W/L
 
so that Ids =  (Vgs −Vt)Vds −V 2 ds / 2  4a ( Alternate form of Eqn4)
Gate/Channel Capacitance (parallel plate) Also , so

Sometimes it is convenient to use gate capacitance per unit area Co rather than Cg. Noting that Cg = Co
WL

We may also write , Ids = Co W/L (Vgs − Vt)Vds − V 2 ds / 2 4c 
Saturated region:
Saturation begins when Vds = Vgs - Vt. Since at this point the IR drop in the channel equals the effective
gate to channel voltage at the drain and we may assume that the current remains fairly constant as Vds
increases further.
Ideal I-V Characteristics
Drain current of MOS device in different operating regions.
MOS transistors have three regions of operation:
• Cutoff or sub-threshold region •Linear region • Saturation region

The long-channel model assumes that the current through an OFF transistor is [Link] a transistor turns
ON (Vgs>Vt),the gate attracts carriers(electrons) to form a channel. The electrons drift from source to
drain at a rate proportional to the electric field between these regions. Thus, we can compute currents
if we know the amount of charge in the channel and the rate at which it moves. We know that the
charge on each plate of a capacitor is Q=CV. Thus, the charge in the channel Qchannel is
where Cg is the capacitance of the gate to the channel and Vgc-Vt is the
amount of voltage attracting charge to the channel beyond the minimum required to invert from pton.
The gate voltage is referenced to the channel, which is not grounded. If the source is at Vs and

[Link]’s College of Engineering/[Link]’s Institute of Technology 3

 VLSI and Chip Design Department of ECE 2023-24
the drain is at Vd, the average is Vc=(Vs+Vd)/2= Vs+Vds/2. Therefore, the mean difference between
the gate and channel potentials Vgc is Vg–Vc=Vgs–Vds /2,as shown in Figure 2.5. We can model the
gate as a parallel plate capacitor with capacitance proportional to area over thickness. If the gate has
length L and width W and the oxide thickness is tox, as shown in Figure2.6, the capacitance is

Where ε0 is the permittivity of frees pace,8.85×10–14F/cm,andthepermittivityofSiO2is

kox=3.9times as great. Often, the εox/tox term is called Cox, the capacitance per unit area of the
gate oxide.

Some nanometer processes use a different gate dielectric with a higher dielectric constant. In these
processes, tox the equivalent oxide thickness (EOT), the thickness of a layer of SiO2 that has the same
Cox. In this case, tox is thinner than the actual dielectric. Each carrier in the channel is accelerated to
an average velocity, v, proportional to the lateral electric field, i.e., the field between source and drain.
The constant of proportionality μ is called the mobility. The electric field E is the voltage
difference between drain and source Vds divided by the channel length . The time required
for carriers to cross the channel is the channel length divided by the carrier velocity: L/v. Therefore,
the current between source and drain is the total amount of charge in the channel divided by the time
required to cross

The term Vgs–Vt arises so often that it is convenient to abbreviate it as VGT. Equation describes the
linear region of operation, for Vgs>Vt, but Vds relatively small. It is called linear or resistive because
when Vds<<VGT, Ids increases almost linearly with Vds, just like an ideal resistor. The geometry and
technology- dependent parameters are sometimes merged into a single factor ᵝ.

If Vds>Vdsat-VGT, the channel is no longer inverted in the vicinity of the drain; we say it is pinched
off. Beyond this point, called the drain saturation voltage, increasing the drain voltage has no further
effect on current. Substituting Vds=Vdsat at this point of maximum current into Eq(2.5),we find an
expression for the saturation current that is independent of Vds. …
This expression is valid for Vgs>Vt and Vds>Vdsat. Thus, long-channel MOS transistors are said to
exhibit square-law behavior in saturation.
Two key figures of merit for a transistor are Ion and Ioff. Ion (also called Idsat) is the ON current,
Ids, when Vgs=Vds=VDD. Ioff is the OFF current when Vgs=0 and Vds=VDD. According to the
long-channel model, Ioff=0and .

Figure 2.7(a) showsthe I-Vcharacteristicsforthe [Link]-ordermodel,the current

[Link]’s College of Engineering/[Link]’s Institute of Technology 4

VLSI and Chip Design Department of ECE 2023-24
is zero for gate voltages below Vt. For higher gate voltages, current increases linearly with Vds for
small Vds. As Vds reaches the saturation point Vdsat=VGT, current rolls off and eventually becomes
independent of Vds when the transistor is saturated. pMOS transistors behave in the same way, but
with the signs of all voltages and currents reversed. The I-V characteristics are in the third quadrant, as
shown in Figure2.7 (b).

Non -Ideal I-V Effects

The saturation current increases less than quadratically with increasing Vgs . This is caused
by two effects: velocity saturation and mobility degradation.
• At high lateral field strengths (Vds /L), carrier velocity ceases to increase linearly with field
strength. This is called velocity saturation and results in lower Ids than expected at high Vds .
• At high vertical field strengths (Vgs /tox ), the carriers scatter off the oxide interface more often,
slowing their progess. This mobility degradation effect also leads to less current than expected
at high Vgs .
• The saturation current of the nonideal transistor increases somewhat with Vds . This is caused
by channel length modulation, in which higher Vds increases the size of the depletion region
around the drain and thus effectively shortens the channel.
• Increasing the potential between the source and body raises the threshold through the body
effect. Increasing the drain voltage lowers the threshold through drain-induced barrier
lowering. Increasing the channel length raises the threshold through the short channel effect.
• When Vgs<Vt , the current drops off exponentially rather than abruptly becoming zero. This is
called subthreshold conduction. The current into the gate Ig is ideally 0. However, as the thickness
of gate oxides reduces to only a small number of atomic layers, electrons tunnel through the gate,
causing some gate leakage current. The source and drain diffusions are typically reverse- biased
diodes and also experience junction leakage into the substrate or well.
Both mobility and threshold voltage decrease with rising temperature. The mobility effect tends
to dominate for strongly ON transistors, resulting in lower Ids at high temperature. The threshold effect
is most important for OFF transistors, resulting in higher leakage current at high temperature. In
summary, MOS characteristics degrade with temperature.

[Link]’s College of Engineering/[Link]’s Institute of Technology 5

 VLSI and Chip Design Department of ECE 2023-24
Mobility Degradtion and Velocity Saturation
• Carrier drift velocity, and hence current, is proportional to the lateral electric field E lat = Vds /L
between source and drain. The constant of proportionality is called the carrier mobility, μ. The long-
channel model assumed that carrier mobility is independent of the applied fields.
• A high voltage at the gate of the transistor attracts the carriers to the edge of the channel, causing
collisions with the oxide interface that slow the carriers. This is called mobility degradation.
• Carriers approach a maximum velocity vsat when high fields are applied. This phenomenon is called
velocity saturation.
Channel Length Modulation
Ideally, Ids is independent of Vds for a transistor in saturation, making the transistor a perfect
current source. The p–n junction between the drain and body forms a depletion region with a width Ld
that increases with Vdb. The depletion region effectively shortens the channel length to Leff = L - Ld

Assume the source voltage is close to the body voltage so Vdb = Vds. Hence, increasing Vds decreases
the effective channel length. Shorter channel length results in higher current; thus, Ids increases with
Vds in saturation. This can be crudely modeled by multiplying EQ (2.10) by a factor of (1 + Vds / VA),
where VA is called the Early voltage. In the saturation region

As channel length gets shorter, the effect of the channel length modulation becomes relatively more
important. Hence, VA is proportional to channel length. This channel length modulation model is a
gross oversimplification of nonlinear behavior and is more useful for conceptual understanding than for
accurate device modeling.
Threshold Effects
So far, we have treated the threshold voltage as a constant. However, Vt increases with the source
voltage, decreases with the body voltage, decreases with the drain voltage, and increases with channel
length. This section models each of these effects.
Body Effect
The body is an implicit fourth terminal. When a voltage Vsb is applied between the source and body,
it increases the amount of charge required to invert the channel, hence, it increases the threshold voltage.
The threshold voltage can be modeled as
where Vt0 is the threshold voltage when the source is at the body potential, ϕs is the surface potential
at threshold and γ is the body effect coefficient, typically in the range 0.4 to 1 V1/2.
i. Drain induced barrier Lowering (DIBL)
The drain voltage Vds creates an electric field that affects the threshold voltage. This drain-
induced barrier lowering (DIBL) effect is especially pronounced in short-channel transistors.
• It can be modeled asVt = Vto –ηVds. where η is the DIBL coefficient, typically on the order
of 0.1 (often expressed as 100 mV/V).
Drain-induced barrier lowering causes Ids to increase with Vds in saturation, in much the same way as
channel length modulation does. This effect can be lumped into a smaller Early voltage VA.
Short Channel Effects
The threshold voltage typically increases with channel length. This phenomenon is especially
pronounced for small L where the source and drain depletion regions extend into a significant portion
of the channel, and hence is called the short channel effect or Vtrolloff.
ii. Leakage
• Even when transistors are nominally OFF, they leak small amounts of current. Leakage mechanisms
include subthreshold conduction between source and drain, gate leakage from the gate to body, and
junction leakage from source to body and drain to body.
• Subthreshold conduction is caused by thermal emission of carriers over the potential barrier set by
the threshold. Gate leakage is a quantum-mechanical effect caused by tunneling through the

[Link]’s College of Engineering/[Link]’s Institute of Technology 6

VLSI and Chip Design Department of ECE 2023-24
extremely thin gate dielectric. Junction leakage is caused by current through the p-n junction
between the source/drain diffusions and the body.

Subthreshold Leakage
• The long-channel transistor I-V model assumes current only flows from source to drain when Vgs>
Vt. In real transistors, current does not abruptly cut off below threshold, but rather drops off
exponentially.
• When the gate voltage is high, the transistor is strongly ON. When the gate falls below Vt , the
exponential decline in current appears as a straight line on the logarithmic scale. This regime of
Vgs<Vt is called weak inversion.
• The subthreshold leakage current increases significantly with Vds because of drain-induced barrier
lowering. There is a lower limit on Ids set by drain junction leakage that is exacerbated by the
negative gate voltage.
• Subthreshold leakage current is described by EQ (2.42). Ids0 is the current at threshold and is
dependent on process and device geometry.

Gate Leakage
According to quantum mechanics, the electron cloud surrounding an atom has a probabilistic spatial
distribution. For gate oxides thinner than 15–20 Å, side of the oxide, where it will get whisked away
through the channel. This effect of carriers crossing a thin barrier is called tunneling, and results in
leakage current through the gate.
Two physical mechanisms for gate tunneling are called Fowler-Nordheim (FN) tunnelingand
direct tunneling. FN tunneling is most important at high voltage and moderate oxide thickness and is
used to program EEPROM memories. Direct tunneling is most important at lower voltage with thin
oxides and is the dominant leakage component. The direct gate tunneling current can be estimated as

where A and B are technology constants.

Junction Leakage
The p–n junctions between diffusion and the substrate or well form diodes. The well-to-
substrate junction is another diode. The substrate and well are tied to GND or VDD to ensure these
diodes do not become forward biased in normal operation. However, reverse-biased diodes stillconduct
a small amount of current ID.

where IS depends on doping levels and on the area and perimeter of the diffusion region and VD is the
diode voltage (e.g., –Vsb or –Vdb). When a junction is reverse biased by significantly
more than the thermal voltage, the leakage is just –IS, generally in the 0.1–0.01 fA/μm2 range, which
is negligible compared to other leakage mechanisms.
More significantly, heavily doped drains are subject to band-to-band tunneling (BTBT) and
gate-induced drain leakage (GIDL).
Temperature Dependence
Transistor characteristics are influenced by temperature. Carrier mobility decreases with temperature.
An approximate relation is
where T is the absolute temperature, Tr is room temperature, and kμ is a fitting parameterwith a

[Link]’s College of Engineering/[Link]’s Institute of Technology 7

 VLSI and Chip Design Department of ECE 2023-24
typical value of about 1.5. vsat also decreases with temperature, dropping by about20% from 300 to 400
K. The magnitude of the threshold voltage decreases nearly linearly with temperature and maybe
approximated by where kvt is typically about 1–2
mV/K. Ion at high VDD decreases with temperature. Subthreshold leakage increases exponentiallywith
temperature.
• Subthreshold leakage is exponentially dependent on temperature, so lower threshold voltages can
be used. Velocity saturation occurs at higher fields, providing more current.
• As mobility is also higher, these fields are reached at a lower power supply, saving power.
Depletion regions become wider, resulting in less junction capacitance.
Geometry Dependence
• The layout designer draws transistors with width and length Wdrawn and Ldrawn. The actual gate
dimensions may differ by some factors XW and XL.
• the source and drain tend to diffuse laterally under the gate by LD, producing a shorter effective
channel length that the carriers must traverse between source and drain. Similarly, WD accounts for
other effects that shrink the transistor width. The factors of two come from lateral diffusion on both
sides of the channel.

• Therefore, a transistor drawn twice as long may have an effective length that is more than twice as
great. Similarly, two transistors differing in drawn widths by a factor of two may differ in
saturation current by more than a factor of two.
• Threshold voltages also vary with transistor dimensions because of the short and narrow channel
effects.
Combining threshold changes, effective channel lengths, channel length modulation, and
velocity saturation effects, Idsat does not scale exactly as 1/L. In general, when currents must be
precisely matched (e.g., in sense amplifiers or A/D converters), it is best to use the same width and
length for each device. Current ratios can be produced by tying several identical transistors in parallel.
CMOS TECHNOLOGIES
CMOS provides an inherently low power static circuit technology that has the capability of providing
a lower-delay product than comparable design-rule nMOS or pMOS technologies. The four dominant
CMOS technologies are:
P-well process
n-well process
twin-tub process
Silicon on chip process

nMOS FABRICATION
• Processing is carried out on a thin wafer cut from a single crystal of silicon of high purity into
which the required p-impurities are introduced as the crystal is grown.
• A layer of silicon dioxide ( SiO2), typically 1m thick is grown all over he surface of the wafer
to protect the surface, act as a barrier to dopants during processing and provide a generally insulating
substrate on to which other layers may be deposited and patterned.
• The surface is now covered with a photo resist which is deposited onto the wafer and spun to
achieve an even distribution of the required thickness.
• The photo resist layer is then exposed to ultra violet light through a mask which defines those
regions into which diffusion is to take place together with transistor channels.
• These areas are subsequently readily etched away together with the underlying silicon dioxide so
that the wafer surface is exposed in the window defined by the mask.
• Remaining photo resist is removed and a thin layer of SiO2 is grown over the entire chip surface
and then polysilicon is deposited on top of this to form the gate structure. The Layer consists of
heavily doped polysilicon deposited by chemical vapor deposition (CVD).
• Photo resist coating and masking allows the polysilicon to be patterned and then the thin oxide is
removed to expose areas into which n-type impurities are to be diffused.
• Thin oxide is grown over all again and is then masked with photo resist and etched to expose
selected areas of the polysilicon gate and the drain and source areas where connections are to be
made.
• The whole chip then has metal (Al) deposited over its surface to a thickness typically of 1 m. This
metal layer is then masked and etched to form the required interconnection pattern.

[Link]’s College of Engineering/[Link]’s Institute of Technology 8

VLSI and Chip Design Department of ECE 2023-24

CMOS FABRICATION
• P-well process is widely used in practice and then the n-well process is also popular.
P-well process
• The diffusion must be carried out with special care since the p-well doping concentration and depth
will affect the threshold voltages as well as the breakdown voltages of the n-transistor.
• To achieve low threshold voltages ( 0.6 to 1.0 V) we need wither deep well diffusion or high well
resistivity.
• But deep wells require larger spacing due to lateral diffusion and therefore a larger chip area.

[Link]’s College of Engineering/[Link]’s Institute of Technology 9

VLSI and Chip Design Department of ECE 2023-24
• The p-well act as substrates for the n-devices within the parent n-substrate and provided that voltage
polarity restrictions are observed, the 2 areas are electrically isolated.

Layout Design rules

Layout design rules describe how small features can be and how closely they can be reliably
packed in a particular manufacturing process. Industrial design rules are usually specified in microns.
This makes migrating from one process to a more advanced process or a different foundry’s process
difficult because not all rules scale in the same way.
Mead and Conway popularized scalable design rules based on a single parameter ,λ, that
characterizes the resolution of the process. Λ is generally half of the minimum drawn transistor channel
length. This length is the distance between the source and drain of a transistor and is set by the
minimum width of a polysilicon wire. Designers often describe a process by its feature size. Feature
size refers to minimum transistor length, so λ is half the feature size.
This length is the distance between the source and drain of a transistor and is set by the
minimum width of a polysilicon wire. For example, a 180 nm process has a minimum polysilicon width
(and hence transistor length) of 0.18 μm and uses design rules with λ= 0.09 μm3. Lambda- based rules
are necessarily conservative because they round up dimensions to an integer multiple ofλ
A conservative but easy-to-use set of design rules for layouts with two metal layers in an n-well
process is as follows:
• Metal and diffusion have minimum width and spacing of 4 λ.
• Contacts are 2 λ × 2 λ and must be surrounded by 1 λ on the layers above and below.
• Polysilicon uses a width of 2 λ.
• Polysilicon overlaps diffusion by 2λ where a transistor is desired and has a spacing
of 1 λ away where no transistor is desired.
• Polysilicon and contacts have a spacing of 3λ from other polysilicon or contacts.
• N-well surrounds pMOS transistors by 6λ and avoids nMOS transistors by 6λ.
Transistor dimensions are often specified by their Width/Length (W/L) ratio. For example, the
nMOS transistor in Figure 1.39 formed where polysilicon crosses n-diffusion has a W/L of 4/2. In a
0.6 μm process, this corresponds to an actual width of 1.2 μm and a length of 0.6 μm. Such a

[Link]’s College of Engineering/[Link]’s Institute of Technology 10

VLSI and Chip Design Department of ECE 2023-24
minimum-width contacted transistor is often called a unit transistor.

pMOS transistors are often wider than nMOS transistors because holes move more slowly than
electrons so the transistor has to be wider to deliver the same current. Figure 1.40(a) shows a unit
inverter layout with a unit nMOS transistor and a double-sized pMOS transistor. Figure 1.40(b) shows
a schematic for the inverter annotated with Width/ Length for each transistor. In digital systems,
transistors are typically chosen to have the minimum possible length because short-channel transistors
are faster, smaller, and consume less power. Figure 1.40(c) shows a shorthand we will often use,
specifying multiples of unit width and assuming minimum length.
Gate layouts
Line of Diffusion based style consists of four horizontal strips:
Metal ground at the bottom of the cell, n-diffusion, p-diffusion, and metal power at the top.
The power and ground lines are often called supply rails. Polysilicon lines run vertically to form
transistor gates. Metal wires within the cell connect the transistors appropriately.

Figure 1.41(a) shows such a layout for an inverter. The input A can be connected from the top,
bottom, or left in polysilicon. The output Y is available at the right side of the cell in metal. Recall that
the p-substrate and n-well must be tied to ground and power, respectively.
Figure 1.41(b) shows the same inverter with well and substrate taps placed under the power and
ground rails, respectively. Figure 1.42 shows a 3-input NAND gate. Notice how the nMOS transistors
are connected in series while the pMOS transistors are connected in parallel. Power and ground extend
2 λ on each side so if two gates were abutted the contents would be separated by 4 λ, satisfying design
rules. The height of the cell is 36 λ, or 40 λ if the 4 λ space between the cell and another wire above it
is counted. All these examples use transistors of width 4 λ.

[Link]’s College of Engineering/[Link]’s Institute of Technology 11

VLSI and Chip Design Department of ECE 2023-24

[Link]’s College of Engineering/[Link]’s Institute of Technology 12