Design for testability (DFT)
Unit-5
DFT
• The chip manufacturing process is prone to defects and the defects are
commonly referred as faults.
• A fault is testable if there exists a well-specified procedure to expose it in the
actual silicon.
• To make the task of detecting as many faults as possible in a design, we need to
add additional logic; Design for testability (DFT) refers to those design techniques
that make the task of testing feasible.
• The most common DFT techniques for logic test are called Scan, ATPG and BIST.
Testing a CMOS ICs
To checking the correctness of the ICs, before and after the fabrication.
Testing is done at several levels
1. Wafer Level : i.e Die is tested.
2. Packaged Level: to test physical nature.
3. Board Level: Placed in board after manufacture for testing.
4. System Level: Specific testing if malfunction occurred to recheck the
design fault.
5. Field Test: End user test, test while using the ICs
Fault Models
• Fault models simplify how manufacturing defects behave, so that test
patterns (Vectors) can be created to find and detect those defects.
The common fault models are:
• Functional Defects: Stuck-at Fault Model
• Current defects: Pseudo Stuck-at Fault Model (IDDQ)
• Speed defects: At-speed Fault Model, Path Delay Fault
The two most common fault models are stuck-at and at speed fault
models.
Fault Models
• Fault models simplify how manufacturing defects behave, so that test
patterns (Vectors) can be created to find and detect those defects.
The common fault models are:
• Functional Defects: Stuck-at Fault Model
• Current defects: Pseudo Stuck-at Fault Model (IDDQ)
• Speed defects: At-speed Fault Model, Path Delay Fault
The two most common fault models are stuck-at and at speed fault
models.
1. Stuck-at Faults
• This is the most common fault model used in industry. It models
manufacturing defects which occurs when a circuit node is shorted to VDD
(stuck-at-1 fault) or GND (stuck-at-0 fault) permanently.
• The fault can be at the input or output of a gate.
• Thus a simple 2-input AND gate has six possible stuck-at faults
1. Stuck-at Faults
• There are three input ports in the circuit, thus we can have a combination of eight
different inputs or patterns {000, 001, 010, 011, 100, 101, 110, 111}.
• Out of the eight patterns, only two patterns {011, 111} will be able to detect this
fault because with rest of the patterns the expected output will be same as the
actual circuit output in the presence of this s-a-0 fault.
• For bigger circuits the CAD tools (ATPG tools) will do the pattern generation.
• The ATPG tools will try to generate the stuck-at fault patterns required to test all
the possible fault locations using complex algorithms.
Stuck at fault for AND Gate
At-speed Faults
• It models the manufacturing defects that behave as gross delays on gate input-output
ports. At-speed fault models most widely used today include the path delay model and the
transition delay model.
• Each port is tested for logic 0-to-1 transition delay (low-to-rise fault) or logic 1-to-0
transition delay (rise-to-fall fault).
• Testing logic at-speed requires a test pattern with two parts. The first part launches a logic
transition value along a path, and the second part captures the response at a specified time
determined by the system clock speed.
• If the logic involved did not transition as expected during the cycle time, the path fails the
test and is considered to contain a defect.
Assume Initial Value stored in Flip Flop 1 = 1
Assume Initial Value stored in Flip Flop 2 = 1
After 1st Clock pulse (Launch Edge)
Captured Value in Flip Flop 1 = 0
(1 to 0 transition occurs at the output of the AND gate)
Captured Value in Flip Flop 2 = 1
After 2nd Clock pulse (Capture Edge)
Expected Captured Value in Flip Flop 2 = 0
Actual Captured Value in Flip Flop 2 = 1
SCAN and ATPG
• Scan is the internal modification of the design’s circuitry to increase its test-ability.
• ATPG stands for Automatic Test Pattern Generation; as the name suggests, this is
basically the generation of test patterns. we can say that Scan makes the process of
pattern generation easier for detection of the faults.
It is difficult to control the flop’s value through primary inputs and observe the captured
response in primary outputs.
• To test a fault we need to initialize the flops to the required values.
• To solve this issue we do ‘Scan Insertion’ during synthesis. ‘Scan Insertion’ is to make a difficult-to-
test sequential circuit behave (during testing process) like an easier-to-test combinational circuit.
Scan Test involves two steps:
1. Converting Regular Flop to Scan Flop
All the flops in the design are converted into scan flops, except –
• The ones that are excluded by user. These are called non-scan flops.
• The ones that have DFT DRC violation(s).
2. Stitching the Scan Flops to form Scan Chains
• The scan flops are stitched to form scan chain(s) as shown below.
The number of scan chains depends upon various user inputs like –
• Length of scan chain, Clock domain mixing, Power domain mixing
Voltage domain mixing
• To initialize any flop to a value as shown in the above image, we simply
make the SE = 1, such that SI to Q path is activated and we shift in the
required values serially through a top level primary input called Scan-
Input.
• Once the required values are loaded to the flops, we capture the values
from combinational circuit by making SE = 0.
• To observe the captured response we make the SE = 1 and serially shift
out the captured data through a primary output called Scan-Output.
• Thus in a way, we can say the scan flop’s output (Q) act as pseudo
primary output of the design and the scan flop’s input (D) act as pseudo
primary inputs to the design, thereby making it a pseudo combination
circuit.
ATE
• Once the patterns are generated, the expected response of the circuit for each pattern is obtained
in pre-silicon.
• The expected responses along with the patterns are then stored in the memory of Automatic Test
Equipment (ATE).
• In post-silicon, the manufactured chip is tested using the ATE, which loads the pattern and
compares it with the expected response for pass or fail status.
Advantage and Disadvantages of ATE
Advantages of Scan-based DFT:
• Enhanced Testability: Scan insertion allows for the control and observation of
internal flip-flops (FFs), making it easier to test sequential circuits.
• Automated Test Pattern Generation (ATPG): can automatically generate test
patterns based on the scan structure.
• High Fault Coverage: Can achieve high fault coverage, ensuring the detection of
most design faults.
Disadvantages of Scan-based DFT:
• Design Complexity:Scan insertion and the management of scan chains can add
complexity to the design.
• Testing Time: test patterns into and out of scan chains can increase testing time.
• Increased Power Consumption and cost Overhead: The additional circuitry and
the need of scan cells during testing can increase power consumption and area.
Limitations of Scan-based DFT
• Scan Insertion: Requires modification of the original circuit design to add
scan cells.
• Scan Chain Complexity: Managing multiple scan chains can be complex,
especially in large designs.
• Performance Overhead: Scan insertion can introduce timing constraints and
potentially reduce the maximum operating frequency.
• Power Consumption Overhead: Scan-based testing can lead to increased
power consumption, especially when testing at high frequencies.
Built in Self Test (BIST)
BIST (Built-In Self-Test) is a DFT technique that allows a chip to test itself without
external equipment.
BIST reduces testing costs by minimizing reliance on external Automated Test
Equipment (ATE).
Provides the option of infield testing and faster diagnostic property.
Types of BIST:
1. Memory BIST (MBIST): Focuses on testing embedded memory blocks within a
chip. MBIST uses specific algorithms to detect faults in memory cells, rows, and
columns.
2. Logic BIST (LBIST): Tests combinational and sequential logic circuits. It often uses
LFSRs to generate pseudorandom test patterns and a signature analyzer to
compare the CUT's responses.
3. Analog and Mixed-Signal BIST: Designed for testing analog components like ADCs
and DACs.
Built in Self Test (BIST) Architecture
The Architecture has three major components:
1. BIST controller: Manages the BIST process, sequencing test patterns, and controlling the flow of data between
the TPG and ORA.
2. TPG (Test Pattern Generator): Generates a sequence of test patterns designed to stimulate the CUT and reveal
potential faults.
3. RA (Response Analyzer): Compares the actual output responses of the CUT with the expected outputs or
compacts the responses into a signature for efficient pass/fail determination.
• The basic mechanism of LBIST is it uses a Linear Feedback Shift Register (LFSR) to generate the
inputs to the device’s internal scan chain, initiate a functional cycle to capture the response of the
device,
• Then response compactor compress the captured response using a multiple input signature register
(MISR). The compressed response that comes out of the MISR is called the signature.
• Any corruption in the output signature indicates a defect in the device.
Advantages of BIST in DFT:
• Reduced Testing Costs: BIST eliminates the need for expensive external test
equipment, leading to lower testing costs.
• Reduced Test Generation Effort: BIST minimizes the need for external test pattern
generation, saving time and resources.
• Faster Time: BIST accelerates the testing process, enabling faster product
development.
• Improved Reliability: BIST can be used to test the IC at various stages of the
manufacturing process and during the operational life of the product, enhancing
reliability.
• Early Fault Detection: BIST helps identify defects early in the manufacturing process,
preventing cascading effects and improving yield.
Disadvantages of BIST in DFT:
• Increased Design Complexity: Implementing BIST circuitry adds to the complexity of
the design, requiring specialized knowledge and resources.
• Overhead in Chip Area and Power: BIST circuitry consumes chip area and power,
which needs to be considered in the design and may not be suitable for all
applications.
Assignment:
1. Find the minimum test signal for the given circuits for stuck at fault
for 0 and 1 both.
2. Interchange the gate positions of the gates and then find the
recalculate the test signals
