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VLSI Training Module

The document outlines an in-house training schedule for VLSI at the Guru Tegh Bahadur Institute of Technology, compiled by Dr. Prachi Dewan. It includes a comprehensive list of topics, tools, experiments, and the estimated duration of the module, which totals 40 hours over 4 to 5 weeks. The training aims to prepare participants for job roles such as IC Design Engineer and Verification Engineer, with potential placements at companies like Synopsys and AMD.

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23 views5 pages

VLSI Training Module

The document outlines an in-house training schedule for VLSI at the Guru Tegh Bahadur Institute of Technology, compiled by Dr. Prachi Dewan. It includes a comprehensive list of topics, tools, experiments, and the estimated duration of the module, which totals 40 hours over 4 to 5 weeks. The training aims to prepare participants for job roles such as IC Design Engineer and Verification Engineer, with potential placements at companies like Synopsys and AMD.

Uploaded by

keshavkumar88630
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

Guru Tegh Bahadur Institute of Technology

Inhouse Training Schedule for VLSI

Compiled by:
[Link] Dewan
Vidisha
Khetarpal

Module Details: VLSI


1. Complete List of Topics to be Covered

- Introduction to VLSi (Hardware Description Languages)

- VLSI Design Methodology

-----System specification and architecture design

------Functional design

-----Logical design

-----Fabrication

-----Packaging

- Top Design Methodology

------System Level

------Algorithmic

------RTL

------Gate Level

-------Transistor Level

- Design Trends in VLSI

- Challenges in VLSI Technology


- CMOS Fabrication Process

- Digital Fundamentals

- CMOS Circuit Characterization

- CMOS Logic Gate Design

- Dynamic CMOS Logic

- Static Versus Dynamic Logic

- Sequential Logic

- Memories

- Software Introduction

- MOS Schematic Simulation

2. Tools to be Used & Proposed Experiments/Practicals


-EDA TOOLS: CADENCE, MENTOR GRAPHICS
-TANNER EDA TOOLS
3. Experiments/Practicals:
- Implementation of DC characteristics of NMOS, PMOS, Inverter

- Implementation of basic and universal gates (AND, OR, NAND, NOR, XOR, XNOR)

- Implementation of combinational circuits ( half adder, full adder)

- Introduction to CMOS TG

- Implementation of MUX, Demux using CMOS TG

- Introduction to IC Layout Design

- Implementation of common source amplifier, common gate amplifiers

- Delay Time analysis and calculation

- Minor project

4. Estimated Duration of Module

Total Duration: 40 Hours

- Theory: 20 Hours

- Practical/Hands-on: 20 Hours

Suggested Duration: 4 to 5 Weeks

[Link] Job Roles & Potential Companies for Placement


- IC Design Engineer

- Physical Design Engineer

- Verification Engineer

- Analog/Mixed-Signal Design Engineer

[Link] Companies:
- Synopsys

- AMD

- Cadence

- NXP

- STMicroelctronics

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