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VHDL Syllabus

The document outlines the T.Y.B.Sc. Electronic Science course for 2021 at Savitribai Phule Pune University, focusing on Digital Design using Verilog. It includes course outcomes, detailed unit topics covering Verilog structure, modeling styles, logic synthesis, and programmable logic devices. Recommended textbooks for further study are also provided.

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58 views1 page

VHDL Syllabus

The document outlines the T.Y.B.Sc. Electronic Science course for 2021 at Savitribai Phule Pune University, focusing on Digital Design using Verilog. It includes course outcomes, detailed unit topics covering Verilog structure, modeling styles, logic synthesis, and programmable logic devices. Recommended textbooks for further study are also provided.

Uploaded by

sachin bahade
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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T.Y.B.Sc.

Electronic Science 2021(CBCS Pattern)

SAVITRIBAI PHULE PUNE UNIVERSITY, PUNE


T.Y. B.Sc. ELECTRONIC SCIENCE
2021 PATTERN CBCS
Discipline Specific Elective Course

EL 351: Paper I: Digital Design using VERILOG

SEMESTER V CREDITS: 2 LECTURES: 36


Course Outcomes: After completing the course, the students will be able to
CO1: Know and understand structure of HDL and Verilog.
CO2: Understand different modeling styles in Verilog.
CO3: Use Verilog effectively for simulation, verification and synthesis of digital system.
CO4: Understand basics of programmable logic devices.

UNIT 1: Introduction to Verilog (10 LECTURES)


A Brief History of HDL, Structure of HDL Module, Comparison of VHDL and Verilog,
Introduction to Simulation and Synthesis Tools, Test Benches, Verilog Modules, Delays, data
flow style, behavioral style, structural style, mixed design style, simulating design
Introduction to Language Elements: Keywords, Identifiers, White Space Characters,
Comments, Format, Integers, Reals and Strings, Logic Values, Data Types-net types,
undeclared nets, scalars and vector nets, Register type, Parameters, Expressions, Operands,
Operators, types of Expressions

UNIT 2: Modeling Styles (12 LECTURES)


Data flow Modeling: Continuous assignment, net declaration assignments, delays, net delays.
Behavioral Modeling: Procedural constructs, timing controls, block statement, procedural
assignments, conditional statement, loop statement, procedural continuous assignment
Gate level modeling: Introduction, built in Primitive Gates, multiple input gates, Tri-state gates,
MOS switches, bidirectional switches, gate delay, array instances, implicit nets, Examples
(both combinational and sequential logic circuits)

UNIT 3: Logic synthesis with Verilog (8 LECTURES)


Concept of logic synthesis, Synthesis design flow, Synthesis of combinational logic for two
bit magnitude comparator, Synthesis of Sequential Logic with Flip-Flops

UNIT 4: Introduction to Programmable Logic Devices (6 LECTURES)


Introduction of Programmable Logic Array (PLA), Programmable Array Logic (PAL),
Programmability of PLDs, Complex PLDs (CPLDs), Field-Programmable Gate Arrays

RECOMMENDED BOOKS:
1. Verilog HDL: A Guide to Digital Design & Synthesis, Samir Palnitkar, SunSoft Press,
ISBN: 978-81-775-8918-4.
2. Digital Fundamentals, Floyd and Jain, Pearson Education, ISBN: 8177587633
3. Fundamental digital logic with Verilog design by Stephen Brown and Zvonka Vrenesic,
Mc Graw Hill Publication, ISBN 0-07-282315-1 ISBN 0-07-121322-8 (ISE)

Year 2020-21 5

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