APB PROTOCOL
A Beginner’s Guide
Understanding AMBA
The AMBA (Advanced Microcontroller Bus Architecture) is a widely adopted open-standard
protocol developed by ARM for on-chip communication among components in a System-on-
Chip (SoC). It defines multiple bus protocols—like AHB, AXI, and APB—to efficiently
connect high-performance modules such as processors, memory, and peripherals. AMBA
enables modular design, scalability, and reuse of IP blocks, which accelerates SoC
development while maintaining interoperability.
Understanding Advanced Peripheral Bus (APB)
The Advanced Peripheral Bus (APB) is a part of the AMBA family, designed for connecting low-
bandwidth peripherals like UARTs, GPIOs, and timers. Unlike AXI or AHB, which support high-speed
pipelining, APB offers a simple, low-power interface with a straightforward address and data transfer
mechanism. It is ideal for scenarios where power efficiency and simplicity are more critical than
throughput, making it a popular choice for peripheral subsystems in SoCs.
Applications of APB in Real-Time Systems
The Advanced Peripheral Bus (APB) is widely used in real-time embedded systems where
low-power and simplicity are crucial. It connects slow peripherals that do not require high-
speed data transfer. Some real-time applications of APB include:
• UART (Universal Asynchronous Receiver Transmitter): For serial communication
with external devices.
• GPIO (General-Purpose Input/Output): For controlling LEDs, switches, and external
components.
• Timers and Counters: For delay generation, time measurement, or triggering tasks at
precise intervals.
• Watchdog Timers: For system reliability and automatic reset on faults.
• I²C and SPI Controllers: For communication with sensors, EEPROMs, and display
modules.
• PWM Controllers: Used in motor control, LED dimming, and signal generation.
• RTC (Real-Time Clock): To keep track of time in embedded systems.
• Interrupt Controllers: For managing peripheral interrupts in real-time applications.
APB Signal Descriptions
Signal Source Brief Description
Clock signal for APB; all transfers are timed on the rising edge
PCLK Clock source
of PCLK.
PRESETn System reset Active-low reset signal; usually tied to system bus reset.
PADDR APB bridge Address bus (up to 32 bits) for selecting registers in the slave.
Indicates privilege, security level, and access type
PPROT APB bridge
(data/instruction).
Select signal for individual slave; HIGH means the slave is
PSELx APB bridge
selected.
PENABLE APB bridge Indicates the enable phase (2nd cycle) of a transfer.
PWRITE APB bridge HIGH = write operation; LOW = read operation.
PWDATA APB bridge Write data bus (up to 32 bits), valid when PWRITE is HIGH.
Byte lane write strobes; indicates which bytes of PWDATA are
PSTRB APB bridge
valid.
Slave
PREADY Indicates slave is ready; used to extend transfer if LOW.
interface
Slave Read data bus (up to 32 bits), driven by slave when PWRITE is
PRDATA
interface LOW.
Slave
PSLVERR Transfer error indicator; optional signal, LOW if not supported.
interface
APB State Diagram
The APB (Advanced Peripheral Bus) protocol operates through a simple three-state control flow:
1. IDLE State
• PSELx = 0, PENABLE = 0
• Default state where no transfer is occurring.
• Bus remains in this state until a new transfer is initiated.
2. SETUP State
• PSELx = 1, PENABLE = 0
• Triggered when a transfer is requested.
• Address, control, and write data (if applicable) are provided.
• The bus stays in SETUP for only one clock cycle and always transitions to ACCESS in the next
cycle.
3. ACCESS State
• PSELx = 1, PENABLE = 1
• Actual read or write operation takes place here.
• Bus remains in ACCESS until the slave asserts PREADY = 1:
o If PREADY = 0: bus stays in ACCESS (wait state).
o If PREADY = 1: bus goes to IDLE (if no further transfers) or SETUP (if another
transfer is pending).
This three-phase operation ensures that APB provides a lightweight, non-pipelined interface ideal
for slow peripherals with predictable behavior.
APB Write Transfers
The APB protocol supports write operations in two ways: with no wait states and with wait states.
These operations are handled in two distinct phases — Setup and Access.
Write Transfer with No Wait States
T1 (Setup Phase):
Signals like PADDR, PWDATA, PWRITE, and PSEL are set and latched on the rising edge
of PCLK.
PENABLE is LOW at this stage.
T2 (Access Phase Begins):
PENABLE is asserted HIGH, indicating the Access phase.
If the slave asserts PREADY = 1, the write transfer will complete in the next clock cycle.
T3 (Transfer Completion):
At the next clock edge, the slave accepts the data.
Both PENABLE and PSEL are deasserted.
The bus can go back to IDLE or start a new transfer.
Write Transfer with Wait States
If the slave is not ready, it drives PREADY = 0 during the Access phase.
As a result, the master holds all control and data signals constant:
PADDR, PWDATA, PWRITE, PSEL, PENABLE, PSTRB, and PPROT remain stable.
The bus stays in the ACCESS state, and wait states are inserted.
Once the slave asserts PREADY = 1, the transfer completes on the next clock edge.
APB Read Transfers
Like write operations, APB supports read operations through Setup and Access phases, with or
without wait states.
Read Transfer with No Wait States
T1 (Setup Phase):
Master sets the address (PADDR), PWRITE = 0, and asserts the select signal (PSEL).
These signals are latched on the rising edge of PCLK.
PENABLE remains LOW in this phase.
T2 (Access Phase Begins):
Master asserts PENABLE = 1.
Slave asserts PREADY = 1 and drives valid data on PRDATA.
Data is read by the master at the rising edge of PCLK.
T3 (Transfer Completion):
Transfer ends; PENABLE and PSEL are deasserted.
Bus returns to IDLE or proceeds to another transfer.
Read Transfer with Wait States
• During the Access phase, if the slave is not ready, it drives PREADY = 0.
• The master holds all control signals constant:
o PADDR, PWRITE, PSEL, PENABLE, and PPROT remain stable.
• The slave keeps PRDATA undefined until it is ready.
• Once the slave asserts PREADY = 1, valid data appears on PRDATA, and the master reads it
on the next rising edge.
