VLSI Design

B.E., VII Semester, Electronics & Communication Engineering

[As per Choice Based Credit System (CBCS) scheme]

Subject Code: 18EC72 CIE Marks 40

Number of Lecture Hours/Week :04 SEE Marks 60
Total Number of Lecture Hours 40 (08Hours / Module) Exam Hours 03

Prepared by
PRADEEPA S C
[Link]
EC Dept.
JNNCE,Shimoga.
 VLSI Design

Course Objectives:
• Impart knowledge of MOS transistor theory and CMOS
technologies.
• Impart knowledge on architectural choices and
performance tradeoffs involved in designing and realizing
the circuits in CMOS technology.
• Cultivate the concepts of subsystem design processes.
• Demonstrate the concepts of CMOS testing.
Course outcomes:
• Demonstrate understanding of MOS transistor theory, CMOS
fabrication flow and technology scaling.
• Draw the basic gates using the stick and layout diagrams with the
knowledge of physical design aspects.
• Interpret Memory elements along with timing considerations.
• Demonstrate knowledge of FPGA based system design.
• Interpret testing and testability issues in VLSI Design.
• Analyze CMOS subsystems and architectural issues with the
design constraints.
 Module-1

Introduction

 A Brief History
 MOS Transistors
(1.1 to 1.4 of TEXT2)

MOS Transistor Theory

Introduction,
Long-channel I-V Characteristics,
Non-ideal I-V Effects,
DC Transfer Characteristics
(2.1, 2.2, 2.4 and 2.5 of TEXT2).
 Lecture Overview
• What is a Transistor?
• History
• Types
• Characteristics
• Applications
 What is a Transistor?
• Semiconductors: ability to change from conductor to
insulator
• Can either allow current or prohibit current to flow
• Useful as a switch, but also as an amplifier
• Essential part of many technological advances
 A Brief History
Vacuum tubes
• Purpose
– Used as signal amplifiers and switches
– Advantages
• High power and frequency operation
• Operation at higher voltages
• Less vulnerable to electromagnetic pulses
– Disadvantages
• Very large
• Energy inefficient
• Expensive
 Invention
• Evolution of electronics
– In need of a device that was small, robust, reliable,
energy efficient and cheap to manufacture
• 1947
– John Bardeen, Walter Brattain and William Schockly
invented transistor
• Transistor Effect
– “when electrical contacts
were applied to a crystal
of germanium, the output
power was larger than
the input.”
 The Transistor is Born
• Bell Labs (1947): Bardeen,
Brattain, and Shockley
• Originally made of
germanium
• Current transistors made
of doped silicon
General Applications
Types of transistors
 MOS Transistors
• Silicon (Si), a semiconductor, forms the basic starting material for most
integrated circuits.
• Pure silicon consists of a three-dimensional lattice of atoms.
• Silicon is a Group IV element, so it forms covalent bonds with four adjacent atoms,
as shown in Figure 1.7(a).
• Pure silicon is a poor conductor.
• The conductivity can be raised by introducing small amounts of impurities,
called dopants, into the silicon lattice.
• A dopant from Group V of the periodic table such as , arsenic has five valence
electrons.
• It replaces a silicon atom in the lattice and still bonds to four neighbours, so the
fifth valence electron is loosely bound to the arsenic atom, as shown in
Figure 1.7(b).
 MOS Transistors
• Thermal vibration of the lattice at room temperature is enough to set the electron
free to move, leaving a positively charged As+ ion and a free electron.
• The free electron can carry current so the conductivity is higher.
• We call this an n-type semiconductor because the free carriers are negatively
charged electrons.
• Similarly, a Group III dopant, such as boron, has three valence electrons, as
shown in Figure 1.7(c).
• The dopant atom can borrow an electron from a neighboring silicon atom, which
in turn becomes short by one electron.
• That atom in turn can borrow an electron, and so forth, so the missing electron,
or hole, can propagate about the lattice.
The hole acts as a positive carrier so we call this a p-type semiconductor.
 MOS Transistors

Transistor operation is controlled by electric fields so the devices are also

called Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) or
simply FETs.

 A Metal-Oxide-Semiconductor (MOS) structure is created by superimposing several

layers of conducting and insulating materials to form a sandwich-like structure.
 These structures are manufactured using a series of chemical processing steps
involving oxidation of the silicon, selective introduction of dopants, and deposition
and etching of metal wires and contacts.
 Transistors are built on nearly flawless single crystals of silicon, which are available
as thin flat circular wafers of 15–30 cm in diameter.
 CMOS technology provides two types of transistors (also called devices): an n-type
transistor (nMOS) and a p-type transistor (pMOS).
 MOS Transistors
Cross-sections and symbols of these transistors are shown in Figure 1.9. The n+ and p+
regions indicate heavily doped n- or p-type silicon.
MOS Transistors
The FET differs from BJT in the following important
characteristics:

1. It is a unipolar device.
2. It is simpler to fabricate.
3. Occupies less space in Integrated form, packaging density is
high(>200 million)
4. It has higher input resistance.
5. It can be used as a symmetrical Bilateral switch.
6. It functions as a memory device.
7. It is less noisy than a BJT.
THE ONLY DISADVANTAGE IS IT HAS SMALLER GAIN-BANDWIDTH
PRODUCT THAN BJT
IGFET or MOSFET:
• MOSFETs are three terminal devices with a Gate, Drain and
Source
• Both P-channel (PMOS) and N-channel (NMOS) MOSFETs are
available.
• Voltage controlled field effect transistor.
 IGFET or MOSFET:
MOSFETs are available in two basic forms:

1. Depletion Type - the transistor requires the Gate-Source voltage,

(VGS) to switch the device "OFF". The depletion mode MOSFET is
equivalent to a "Normally Closed" switch.

2. Enhancement Type - the transistor requires a Gate-Source voltage,

(VGS) to switch the device "ON". The enhancement mode MOSFET is
equivalent to a "Normally Open" switch.
 MOSFETs Symbol
N-channel (NMOS) MOSFETs

P-channel (PMOS) MOSFETs

CMOS Logic
The Inverter
The NAND Gate
The NOR Gate
Pass Transistors
Transmission Gates
Tristates
Tristates
Multiplexers
Latches
MOS Transistor Theory
Device Operation:
1. With No Gate Voltage.
2. Creating a Channel for Current Flow.
3. Effect of Applying a Small VDS.
4. Operation as VDS Is Increased.

Vdg

Vds

Vgs
There are three distinct regions of operation:
1. The cutoff region,
2. The Linear or triode region,
3. The saturation region.
2. The Linear or triode region.
3. The saturation region.
MOS Transistor Theory
Ideal I-V Characteristics
Let us derive a model relating the current and voltage (I-V) for an nMOS
transistor in each of these regions.
The model assumes that the channel length is long enough that the lateral
electric field (the field between source and drain) is relatively low.
This model is variously known as the long-channel, ideal, first-order, or
Shockley model.
The long-channel model assumes that the current through an OFF transistor is 0.
When a transistor turns ON (Vgs > Vt), the gate attracts carriers (electrons) to
form a channel.
We know that the charge on each plate of a capacitor is Q = CV.
Thus, the charge in the channel Qchannel is

where Cg is the capacitance of the gate to the channel

Vgc –Vt is the amount of voltage attracting charge to the channel beyond
the minimum required to invert from p to n.
Ideal I-V Characteristics
 Ideal I-V Characteristics
We can model the gate as a parallel plate capacitor with capacitance proportional
to area over thickness.
If the gate has length L and width W and the oxide thickness is tox, as shown in
Figure 2.6, the capacitance is

where ,
ε0 is the permittivity of free space, 8.85 × 10–14
F/cm,
Permittivity of SiO2 is kox = 3.9 times as great.

Often, the εox/tox term is called Cox, the

capacitance per unit area of the gate oxide.
 Ideal I-V Characteristics
Each carrier in the channel is accelerated to an average velocity, v, proportional to the
lateral electric field, i.e., the field between source and drain.
The constant of proportionality μ is called the mobility.

A typical value of μ for electrons in an nMOS transistor with low electric fields is 500–
700 cm2/Vs

The electric field E is the voltage difference between drain and source Vds divided by
the channel length

The time required for carriers to cross the channel is the channel length divided by the
carrier velocity: L/v
Therefore, the current between source and drain is the total amount of charge in the
channel divided by the time required to cross
Ideal I-V Characteristics

linear region of operation

--------------(A)

k prime
Ideal I-V Characteristics
If Vds > Vdsat ≡ VGT, the channel is no longer inverted in the vicinity of the drain; we
say it is pinched off.

Substituting Vds = Vdsat in (A)

we find an expression for the saturation current that is independent of
Vds.

summarizes the current in the three regions:

--------------(B)
 Nonideal I-V Effects
The long-channel I-V model of EQ (A) neglects many effects that are important to
devices with channel lengths below 1 micron.
Figure 2.14 compares the simulated I-V characteristics of a 1-micron wide nMOS
transistor in a 65 nm process.
Nonideal I-V Effects
1. Mobility Degradation and Velocity Saturation
2. Channel Length Modulation
3. Body Effect
4. Subthreshold Leakage
5. Junction Leakage
6. Tunneling
7. Temperature Dependence
8. Geometry Dependence
1. Mobility Degradation and Velocity Saturation

Mobility degradation : A high voltage at the gate of the

transistor attracts the carriers to the edge of the channel,
causing collisions with the oxide interface that slow the
carriers.

Velocity saturation : Carriers approach a maximum

velocity vsat when high fields are applied.
 Velocity Saturation
• At high Elat, carrier velocity rolls off
– Carriers scatter off atoms in silicon lattice
– Velocity reaches vsat
• Electrons: 107 cm/s
• Holes: 8 x 106 cm/s
– Elat lateral electric field.
 Velocity Saturation I-V Effects
• Ideal transistor ON current increases with VDD2
W Vgs  Vt 
2

 Vgs  Vt 
2
I ds  Cox
L 2 2

• Velocity-saturated ON current increases with VDD

I ds  CoxW Vgs  Vt  vmax

• Real transistors are partially velocity saturated

– Approximate with α-power law model
– Ids  VDDα
– 1 < α < 2 determined empirically (≈ 1.3 for 65 nm)
 a-Power Model
The α-power law model provides a simple approximation to capture
this behaviour

α is called the velocity saturation index

 0 Vgs  Vt cutoff

 V
I ds   I dsat ds Vds  Vdsat linear
 Vdsat
 I dsat Vds  Vdsat saturation


  Vt 
a
I dsat  Pc V gs
2
Vdsat  Pv Vgs  Vt 
a /2
 2. Channel Length Modulation
• Reverse-biased p-n junctions form a
depletion region
– Region between n and p with no carriers
– Width of depletion Ld region grows with reverse
bias
Leff = L – Ld
• Shorter Leff gives more current GND
Source
VDD
Gate
VDD
Drain

– Ids increases with Vds Depletion Region

Width: Ld

– Even in saturation n n
L
+ Leff +
p GND bulk Si
GND VDD VDD
Source Gate Drain
Depletion Region
Width: Ld

n L n
+ Leff +
p GND bulk Si
 2. Channel Length Modulation
This can be crudely modeled by multiplying EQ (B) by a
factor of (1 + λVds ), in the saturation region, we find


I ds  Vgs  Vt  1  Vds 
2

2
• λ = channel length modulation factor.
– not feature size
– Empirically fit to I-V characteristics
• Channel length modulation is very important to analog
designers because it reduces the gain of amplifiers.
 [Link] Effect
• Body is a fourth transistor terminal.
• Vsb affects the charge required to invert the channel
– Increasing Vs or decreasing Vb increases Vt
Vt  Vt 0    s  Vsb  s 
ᶲs = surface potential
N
at threshold
s  2vT ln A
ni
– Depends on doping level NA
– And intrinsic carrier concentration ni

tox 2q si N A
  2q si N A 
 ox Cox
 4. Subthreshold Leakage
 Ideally at VGS < VT, ID = 0.
 The MOS device is partially conducting for gate voltages below
the threshold voltage.
 This is termed sub-threshold or weak inversion conduction.

• Subthreshold leakage exponential with Vgs

Vgs Vt 0 Vds  k V sb
 Vds

I ds  I ds 0e nvT
1  e vT 
 
 
 [Link] Leakage
 Conduction even when transistor is in cut-off
 Substrate to diffusion junctions are reverse biased
 However reverse biased diodes do conduct leakage current

• Reverse-biased p-n junctions have some leakage

– Ordinary diode leakage
– Band-to-band tunneling (BTBT)
– Gate-induced drain leakage (GIDL)

p+ n+ n+ p+ p+ n+

n well
p substrate
6. Tunneling
 There is a finite probability that
carriers will tunnel though the
gate oxide. This result in gate
leakage current flowing into
the gate
 The probability drops off
exponentially with tox
 For oxides thinner than
15-20 Å, tunneling becomes a
factor

Use high-K materials in the

gate oxide layer
7. Temperature Dependence

 Transistor characteristics are

influenced by temperature
  decreases with T
 Vt decreases linearly with T
 Ileakage increases with T
 ON current decreases with T
OFF current increases with T
 Thus, circuit performances are
worst at high temperature
 Temperature Issues
• Circuit performance is therefore generally worse at
high temperatures.
• Conversely cooling can enable better performance.
• Cooling techniques
– Convection
• Natural
• Fans
• Heat sinks
– Active cooling
• Water cooling
• Liquid nitrogen
8. Geometry Dependence
 Layout designers draw transistors with Wdrawn, Ldrawn
 Actual dimensions may differ from some factor XW and XL
 The source and drain tend to diffuse laterally under the gate by L D,
producing a shorter effective channel
 Similarly, diffusion of the bulk by WD decreases the effective channel
width
 In process below 0.25 m the effective length of the transistor also
depends significantly on the orientation of the transistor

Where ,
LD and WD other effects that shrink the transistor Length and width
 Module-1

Introduction

 A Brief History
 MOS Transistors
 MOS Transistor Theory
 Ideal I-V Characteristics
 Non-ideal I-V Effects
 DC Transfer Characteristics
(1.1, 1.3, 2.1, 2.2, 2.4, 2.5 of TEXT 2).
Fabrication

 nMOS Fabrication
 CMOS Fabrication[P-well process, N-well process, Twin tub process],
 BiCMOS Technology
(1.7, 1.8,1.10 of TEXT 1).
DC Transfer Characteristics

CMOS Inverter Static Behavior: DC Analysis

CMOS Inverter: DC Analysis

 DC Response: Vout vs. Vin for a gate

 Inverter
 When Vin = 0  Vout = VDD
 When Vin = VDD  Vout = 0
 In between, Vout depends on transistor current
 Idsn = |Idsp|
 Graphical solution gives very good insight
 Transistors operation regions

 Current depends on transistor’s operation

region
 For what Vin and Vout are nMOS and pMOS in
 Cutoff ?
 Linear ?
 Saturation ?
 nMOS and pMOS operation

VDD
VDD
Idsp
Idsp Vin Vout
Vin Vout Idsn
Idsn

Vgsn = Vin Vgsp = Vin - VDD

Vdsn = Vout Vdsp = Vout - VDD
Graphical derivation of the inverter DC
response: I-V Characteristics

 Make pMOS wider than nMOS such that n = p

 For simplicity let’s assume Vtn=Vtp
Graphical derivation of the inverter DC response: current vs.
Vout, Vin
 Load Line Analysis:
For a given Vin:
 Plot Idsn, Idsp vs. Vout
 Vout must be where |currents| are equal
 Graphical derivation of the inverter DC response:
Load Line Analysis

 Vin = 0

Vin0

Idsn, |Idsp|

Vin0
VDD
Vout
Graphical derivation of the inverter DC response:
Load Line Analysis
 Vin = 0.2 VDD

Vin1
Idsn, |Idsp|

Vin1
VDD
Vout
 Graphical derivation of the inverter DC response:
Load Line Analysis

 Vin = 0.4 VDD

Idsn, |Idsp|

Vin2
Vin2

VDD
Vout
Graphical derivation of the inverter DC response:
Load Line Analysis

 Vin = 0.6 VDD

Idsn, |Idsp|

Vin3
Vin3

VDD
Vout
Graphical derivation of the inverter DC response:
Load Line Analysis

 Vin = 0.8 VDD

Vin4
Idsn, |Idsp|

Vin4
VDD
Vout
Graphical derivation of the inverter DC response:
Load Line Analysis

 Vin = VDD

Vin0 Vin5

Vin1
Idsn, |Idsp|

Vin2
Vin3
Vin4
VDD
Vout
DC transfer curve: operating regions
 Beta Ratio
 If p / n  1, switching point will move from VDD/2
 Called skewed gate
 Noise Margins
 How much noise can a gate input see before it does not
recognize the input ?
 Noise Margins
 To maximize noise margins, select logic levels at unity gain
point of DC transfer characteristic
 DC parameters
 Input switching threshold: VTH
 Minimum high output voltage: VOH
 Maximum low output voltage: VOL
 Minimum HIGH input voltage: VIH
 Maximum LOW input voltage: VIL

NML =VIL -VOL

NMH =VOH -VIH

Pass Transistor DC Characteristics