Amrita School of Engineering

Bengaluru Campus
Department of Electronics &
Communication Engineering

23ECE383
VLSI Design Laboratory
V Semester ECE & EAC
Lab Manual

1
 Vision and Mission of the Institute
Vision To be a global leader in the delivery of engineering education,
transforming individuals to become creative, innovative, and socially
responsible contributors in their professions.
M1 To provide best-in-class infrastructure and resources to achieve
excellence in technical education
M2 To promote knowledge development in thematic research areas that
have a positive impact on society, both nationally and globally
M3 To design and maintain the highest quality education through active
Mission engagement with all stakeholders – students, faculty, industry, alumni
and reputed academic institutions
M4 To contribute to the quality enhancement of the local and global
education ecosystem
M5 To promote a culture of collaboration that allows creativity, innovation,
and entrepreneurship to flourish
M6 To practice and promote high standards of professional ethics,
transparency, and accountability

Vision and Mission of the Department

To provide a value-based learning environment for producing
Vision engineers with a blend of technical skills, moral values and leadership
qualities in the field of Electronics, Communication and Computing
channelized towards technological advancement to cater to the needs
of the industry and the society.
M1 Achieving excellence in teaching and learning with an emphasis
on fundamental knowledge and hands-on exposure to match the
state-of-the-art in technology.
Mission M2 Providing an environment for core competency development
and enhancing quality research in emerging areas.
M3 Facilitating professional growth to the students for higher
education and career in industry and academia
M4 Imbibing the essence of human values, ethics and
professional skills to sustain socio -economic development

2
General Do’s and Don’ts

Do’s Don’ts
1. Be regular to the lab. 1. Do not write anything on the table.
2. Maintain silence. 2. Do not connect measuring instrument
without earthing /grounding.
3. Read and try to know the theory behind the
experiment before coming to the lab. 3. Do not set instrument specifications
more than specified for the experiment.
4. Handle the equipment carefully and gently.
4. Do not connect instrument/supply if you
5. For making connection, use ground first.
are not sure. Contact lab assistant and
6. Verify the connections before switching ON faculty.
power supply.
5. Don’t leave the lab even you have
7. For simulation based- experiment, create your completed.
own folder for your programs.
8. Understand each experiment well, analyze and
interpret the results.
9. After the completion of the experiments switch
off the power supply and return the
apparatus/components
10. Shut down the systems properly before leaving
the work bench.
11. Arrange the chairs/stools and equipment
properly before leaving the lab.

3
 23ECE383/ VLSI Design Laboratory
Course Objectives
• To enable the use of simulation tools for analyzing CMOS circuits
• To provide hands-on experience in HDL modeling and simulation of digital subsystems
• To provide a background in the synthesis and implementation of HDL models

Course Outcomes: At the end of the course, the student should be able to
CO1: model and simulate combinational subsystems using HDLs
CO2: model and simulate sequential subsystems using HDLs
CO3: implement HDL models on FPGA
CO4: model and simulate CMOS logic circuits

Syllabus
Define a system which might cover most of the experiments. It is possible to define at most 2 systems
for whole experiments of this course. In the beginning of the lab class, system level explanation must
be given to the students.

Examination/evaluation for system level should have higher weightage of marks. They need to
develop system (at least prototype) at the end, not on breadboard.

1. Write Verilog code to design following combinational circuits using Gate level (Structural)
modeling- (i) Half adder (ii) 2:1 Multiplexer
2. Write Verilog code to design following combinational circuits using Data flow modeling- (i) Half
adder (ii) 2:1 Multiplexer
3. Write Verilog code to design following combinational circuits using Gate level (Structural)
modeling- (i) Full adder using half adders and any other required logic gate (ii) 4:1 Multiplexer using
2:1 Multiplexers only (iii) 8:1 Multiplexer using 2:1 Multiplexers only
4. Write Verilog code to design following sequential circuits using behavioral modeling- (i) D Latch
(ii) D Flip-flop (iii) T Flip-flop (iv) JK Flip-flop
5. Write a Verilog code to design 4-bit Up/Down counter using behavioral modeling.
6. Implementation of sequence detector using Mealy and/or Moore FSM.
7. Implementation of FIFO and LIFO.
8. Design and analyze the transient characteristics for CMOS logic schematics.
9. Design and analyze the transient Characteristics for Full Adder and Ripple Carry Adder using
CMOS logic in schematic.
10. Design and analyze the transient characteristics for D-Flip Flop, JK Flipflop, and T-Flip Flop
using CMOS logic in schematic.

4
Text Book(s)

1. Samir Palnitkar, ―Verilog HDL: A Guide to Digital Design and Synthesis‖, Second Edition,
Pearson, 2003. Michael D Ciletti, ―Advanced Digital Design with the Verilog HDL‖, Second
Edition, Pearson, 2017.
2. J. P. Uyemura, ―Introduction to VLSI Circuits and Systems‖, John Wiley and Sons, 2006.

Reference(s)

1. T. R. Padmanabhan and B. Bala Tripura Sundari, ―Design through the Verilog HDL‖, First
Edition, Wiley Interscience, 2004.
2. Stephen Brown, Zvonko Vranesic, ―Fundamentals of Digital logic with Verilog Design‖, Tata
McGraw Hill Publishing Company Limited, Special Indian Edition, 2007.

5
List of Experiments

Sl. No. Experiment Course

Outcome
1 Write Verilog code to design following combinational circuits usingCO1
Gate level (Structural) modelling- (i) Half adder (ii) 2:1 Multiplexer
2 Write Verilog code to design following combinational circuits using CO1+CO3
Data flow modelling and also implement using FPGA.
(i) Half adder
(ii) 2:1 Multiplexer
3 Write Verilog code to design following combinational circuits using CO1+CO3
Gate level (Structural) modelling and also implement using FPGA.
(i) Full adder using half adders and any other required logic
gate
(ii) 4:1 Multiplexer using 2:1 Multiplexers only
(iii) 8:1 Multiplexer using 2:1 Multiplexers only
4 Write Verilog code to design following sequential circuits using CO2+CO3
behavioural modelling.
(i) D Latch
(ii) D Flip-flop
(iii) T Flip-flop
(iv) JK Flip-flop
5 Design and analyse the transient characteristics for CMOS logic CO4
schematics. e.g. Inverter, NAND, NOR, XOR and F = (AB+C)’ etc.
6 Design and analyse the transient characteristics for D-Flip Flop, JK CO4
Flipflop, and T-Flip Flop using CMOS logic in schematic.
7 Design and analyse the transient Characteristics for advanced CMOS CO4
circuits like Pseudo nMOS circuit, Mirror circuit and Dynamic logic
circuit etc.
System Design CO4

Course Project: System Design as an End Semester Exam of Lab 23ECE383 and Assignment
of Theory 23ECE302
Group Size: 4 students
Number of Groups per class: approximately 17 for ECE and 20 for EAC
Circuits will be given by the faculty.
Each group will get one circuit.

6
 INDEX
Sl. Experiment Date of
No. Experiment
Conduction
1 Write Verilog code to design following combinational circuits using Gate
level (Structural) modelling- (i) Half adder (ii) 2:1 Multiplexer
2 Write Verilog code to design following combinational circuits using Data
flow modelling and also implement using FPGA.
(i) Half adder
(ii) 2:1 Multiplexer
3 Write Verilog code to design following combinational circuits using Gate
level (Structural) modelling and also implement using FPGA.
(i) Full adder using half adders and any other required logic gate
(ii) 4:1 Multiplexer using 2:1 Multiplexers only
(iii) 8:1 Multiplexer using 2:1 Multiplexers only
4 Write Verilog code to design following sequential circuits using
behavioural modelling.
(i) D Latch
(ii) D Flip-flop
(iii) T Flip-flop
(iv) JK Flip-flop
5 Design and analyse the transient characteristics for CMOS logic
schematics. e.g. Inverter, NAND, NOR, XOR and F = (AB+C)’ etc.
6 Design and analyse the transient characteristics for D-Flip Flop, JK
Flipflop, and T-Flip Flop using CMOS logic in schematic.
7 Design and analyse the transient Characteristics for advanced CMOS
circuits like Pseudo nMOS circuit, Mirror circuit and Dynamic logic
circuit etc.
System Design

FACULTY SIGNATURE WITH DATE

7
 Introduction to VERILOG
• Circuit Modeling
• Gate-level Modeling
• Data-level Modeling
• Behavioral Modeling

• What is Verilog HDL?

Verilog HDL is a Hardware Description Language that can be used to model a digital system
at many levels of abstraction:
– Algorithmic-level
– Gate-level
– Switch-level
Verilog is designed for circuit verification and simulation, for timing analysis, for test analysis
(testability analysis and fault grading) and for logic synthesis.
For example, before you get to the structural level of your design, you want to make sure the logical
paths of your design is faultless and meets the specifications

Basic Syntax

Module module_name (port_list);

Declarations:
input, output, wire, parameter…..

System Modeling:
describe the system in gate-level, data-flow, or behavioral style…
endmodule

Gate-Level Modeling

Systems structure can be described using Build-in gates or pre-built modules.

Basic syntax is :
gate-type #delay instance1_name(outputs.., inputs.. ),
:
:
instance6_name(outputs.., inputs.. );
pre-built module module_instance1(output…,inputs..);.

The Built-in Primitive Gates

• Multiple-input gates:
– and, nand, or, nor, xor, xnor
xor xor1(out, inA, inB, inC);

Basic Module Construction

// Compute the logical AND and OR of inputs A and B.

module AND_OR(andOut, orOut, A, B);

output andOut, orOut;
8
 input A, B;
and TheAndGate (andOut, A, B);
or TheOrGate (orOut, A, B);
endmodule

Gate Delays
Syntax: #(Tplh, Tphl)
Examples:
nor #10 Tplh =Tphl=10 time units
nor #(3,5) Tplh=3, Tphl=5
nor #([Link], 5) Tplh=(min2,typ3,max4)

Data-flow Modeling
The basic mechanism used to model a design in the dataflow style is the continuous assignment.
In a continuous assignment, a value is assigned to a net.
Syntax:
assign #delay LHS_net = RHS_expression;

Behavioral Modeling

• The behavior of a design is described using procedural constructs. These are:

– Initial statement: This statement executes only once.
– Always statement: this statement always executes in a loop forever.
• Only register data type can be assigned a value in either of these statements.

Always Statement
Syntax: always
#timing_control procedural_statement
Procedural statement is one of :
– Blocking Procedural_assignment
always
@ (A or B or Cin)
begin
T1=A & B;
T2=B & Cin;
T3=A & Cin;
Cout=T1 | T2 | T3;
end
T1 assignment is occurs first, then T2, then T3….
Procedural statements
Conditional_statement
always
@(posedge clk or posedge reset)
if ( Sum <60)
begin
Grade = C;
Total_C=Total_C +1;
end
9
 else if (Sum<75)
Grade = B;
else
Grade = A;

Case_statement
always
@(Time ==7)
case(Day)
Tue: Pocket-Money = 6;
Mon,
Wed: Pocket_Money = 2;
Fri,
Sat,
Sun: Pocket_Money = 7;
default: Pocket_Money= 0;
endcase

Xilinx Vivado
The Xilinx Vivado Design Suite is the integrated development environment (IDE) used to design
and program the Digilent Basys 3 FPGA board, which features a Xilinx Artix-7 FPGA. The Basys
3 is an entry-level FPGA board designed to be used with Vivado, offering a user-friendly platform
for learning digital design and hardware programming.
Here's a more detailed explanation:
• Basys 3:
This is a physical FPGA board containing a Xilinx Artix-7 FPGA. It's designed for educational and
introductory purposes, providing various input/output devices like switches, buttons, LEDs, and a
seven-segment display.
• Vivado:
Vivado is the software from Xilinx (now AMD) that provides a complete environment for designing,
simulating, and implementing digital circuits on FPGAs. It includes tools for schematic capture,
hardware description language (HDL) coding (Verilog, VHDL), synthesis, place and route, and
bitstream generation.
• Integration:
The Basys 3 is specifically designed to work seamlessly with the Vivado Design Suite. This means
you can easily import your design files (e.g., Verilog code) into Vivado, configure the FPGA, and
then program the Basys 3 board.
• Getting Started:

10
To begin using the Basys 3 with Vivado, you would typically download and install the free
WebPACK edition of Vivado, then create a new project in Vivado, select the correct FPGA device
(Artix-7, XC7A), and import your Verilog or VHDL code.
• Example Projects:
Numerous tutorials and examples demonstrate how to use the Basys 3 with Vivado. These tutorials
often involve creating simple digital logic circuits, controlling LEDs, reading input from switches,
and displaying data on the seven-segment display.
• Key Features of Basys 3:
• Xilinx Artix-7 FPGA
• Onboard clock oscillator (100MHz)
• USB connection for programming and communication
• Various input/output devices (switches, buttons, LEDs, seven-segment display)
• Compatible with Digilent's Adept software for programming
• Key Features of Vivado:
• Complete design flow for FPGA development
• Graphical user interface (GUI) for design entry and simulation
• Powerful synthesis and implementation tools
• Support for various hardware description languages (Verilog, VHDL)
• XDC (Xilinx Design Constraints) files for pin mapping
The Xilinx Vivado Design Suite is used to program the Digilent Basys 3 FPGA board. The Basys 3
is an entry-level FPGA board featuring the Xilinx Artix-7 FPGA, specifically designed to work with
Vivado. It's a popular choice for digital design and student projects due to its features and
compatibility with the free WebPACK edition of Vivado according to Digilent.
Here's a more detailed breakdown:
• Basys 3 Board:
This is a physical development board that houses the Artix-7 FPGA. It's equipped with various on-
board components like LEDs, switches, buttons, a 7-segment display, and expansion ports (Pmod)
to facilitate digital circuit design.
• Xilinx Vivado Design Suite:
This is the software environment used to design, simulate, and program the FPGA. It's a
comprehensive toolset from Xilinx (now part of AMD) that includes tools for high-level synthesis,
logic analysis, and more.
• Compatibility:

11
The Basys 3 board is specifically designed to be compatible with the Vivado Design Suite. The free
WebPACK edition of Vivado is sufficient for working with the Basys 3.
• Features of the Basys 3:
• Artix-7 FPGA: The core of the board is the XC7A35T-1CPG236C Artix-7 FPGA.
• On-board I/O: It includes 16 user LEDs, 16 user switches, 5 user pushbuttons, a 4-
digit 7-segment display, and a 12-bit VGA output.
• Connectivity: It features a USB-JTAG port for programming and communication, a
USB-UART bridge, and multiple Pmod ports for expansion.

[Link]

12
 Introduction of CMOS Schematic
The term CMOS stands for “Complementary Metal Oxide Semiconductor”. This is one of the most
popular technologies in the computer chip design industry and it is broadly used today to
form integrated circuits in numerous and varied applications. Today’s computer memories, CPUs,
and cell phones make use of this technology due to several key advantages. This technology makes
use of both P channel MOSFET (PMOS) and N channel MOSFET (NMOS) semiconductor devices.
This is the dominant semiconductor technology for microprocessors, microcontroller chips,
memories like RAM, ROM, and application-specific integrated circuits (ASICs).

Switch Model of NMOS Transistor

Switch Model of PMOS Transistor

13
 Symbols

General structure of CMOS schematic:

How to Draw CMOS Schematic

1. Write function f.
2. Find the complement of the function f.
3. Number of literals in f’ will give the number of transistors in the CMOS schematic.
4. In conventional CMOS schematic no. of NMOS = no. of PMOS
5. Draw the NMOS network.
➢ AND operation – Transistors in series
➢ OR operation – Transistors in parallel
6. PMOS network is a logical dual of the NMOS network.

14
 Amrita Vishwa Vidyapeetham
Amrita School of Engineering, Bengaluru
Department of ECE
B. Tech. V Semester ECE & EAC
AY2025-2026
23ECE383 VLSI Design Laboratory
Register Number of the Student
Name of the Student
Section
Batch Name
Signature of the Student
Date of the Experiment Conduction

Lab Experiment - 1
Aim: Write Verilog code to design following combinational circuits using Gate level (Structural)
modelling- (i) Half adder (ii) 2:1 Multiplexer
Tool Used: Xilinx Vivado Design Suite

Half Adder

2:1 Multiplexer

15
16
Result:

For Faculty Use Only

Continuous Assessment
(5 Marks)
Faculty Signature with Date

Any Remarks

17
 Amrita Vishwa Vidyapeetham
Amrita School of Engineering, Bengaluru
Department of ECE
B. Tech. V Semester ECE & EAC
AY2025-2026
23ECE383 VLSI Design Laboratory
Register Number of the Student
Name of the Student
Section
Batch Name
Signature of the Student
Date of the Experiment Conduction

Lab Experiment – 2
Aim: Write Verilog code to design following combinational circuits using Data flow modelling and
also implement using FPGA.
(i) Half adder (ii) 2:1 Multiplexer

Tool Used: Xilinx Vivado Design Suite

Theory

Half Adder

2:1 Multiplexer

18
19
Implementation on FPGA:
1. Synthesis:
The Verilog code is first synthesized into a netlist (a representation of the circuit's connections) using
a synthesis tool (like Xilinx Vivado, Intel Quartus, or similar). This tool takes the high-level Verilog
description and translates it into a gate-level representation that can be implemented on the FPGA.
2. Implementation:
The netlist is then mapped to the specific resources available on the target FPGA (logic gates, flip-
flops, etc.). The synthesis tool performs place and route, which involves assigning the logic gates to
specific locations on the FPGA fabric and connecting them with wires.
3. Bitstream Generation:
Finally, a bitstream file is generated. This file contains the configuration data that tells the FPGA
how to configure its programmable logic fabric to implement the designed circuit.
4. FPGA Configuration:
The bitstream is then loaded onto the FPGA, configuring it to function as the half adder or
multiplexer.
Example for FPGA Implementation (Conceptual):
• Synthesis Tool: Use Xilinx Vivado or Intel Quartus for synthesis and implementation.
• Target Device: Select the appropriate FPGA device (e.g., Artix-7, Cyclone V) based on your
needs and board.
• Create a Project: Create a new project in your chosen tool and add the Verilog files for the
half adder and multiplexer.
• Constraints: You may need to create constraints files (e.g., Xilinx UCF or SDC files, or
Intel QSF files) that specify pin assignments, clock frequencies, and other parameters related
to your FPGA board.
• Synthesize: Run the synthesis process. The tool will generate a netlist.
• Implement: Run the implementation process, which includes place and route.
• Generate Bitstream: Generate the bitstream file.
• Program FPGA: Use the tool's programmer to load the bitstream onto your FPGA
development board.

20
Result:

For Faculty Use Only

Continuous Assessment
(5 Marks)
Faculty Signature with Date

Any Remarks

21
 Amrita Vishwa Vidyapeetham
Amrita School of Engineering, Bengaluru
Department of ECE
B. Tech. V Semester ECE & EAC
AY2025-2026
23ECE383 VLSI Design Laboratory
Register Number of the Student
Name of the Student
Section
Batch Name
Signature of the Student
Date of the Experiment Conduction
Lab Experiment - 3
Aim: Write Verilog code to design following combinational circuits using Gate level (Structural)
modelling and also implement using FPGA.
(i) Full adder using half adders and any other required logic gate
(ii) 4:1 Multiplexer using 2:1 Multiplexers only
(iii) 8:1 Multiplexer using 2:1 Multiplexers only
Tool Used: Xilinx Vivado Design Suite

22
23
 Explanation and Implementation Details:
1. Half Adder:
The half_adder module implements a half adder using XOR and AND gates to calculate the
sum and carry, respectively.
2. Full Adder (using half adders):
The full_adder module builds a full adder by connecting two half adders and an OR gate. The
sum is the XOR of the three inputs (a, b, and cin). The carry is the OR of the carry outputs
from the two half adders.
3. 2:1 Multiplexer:
The mux2x1 module implements a 2-to-1 multiplexer using NOT, AND, and OR gates. It
selects between input a or b based on the select line sel.
4. 4:1 Multiplexer:
The mux4x1 module builds a 4-to-1 multiplexer using three 2-to-1 multiplexers. The select
lines sel[1:0] determine which input (a, b, c, or d) is passed to the output.
5. 8:1 Multiplexer:
The mux8x1 module uses seven 2-to-1 multiplexers to implement an 8-to-1 multiplexer. The
select lines sel[2:0] control the selection of the input to be passed to the output.

24
Result:

For Faculty Use Only

Continuous Assessment
(5 Marks)
Faculty Signature with Date

Any Remarks

25
 ita Vishwa Vidyapeetham
Amrita School of Engineering, Bengaluru
Department of ECE
B. Tech. V Semester ECE & EAC
AY2025-2026
23ECE383 VLSI Design Laboratory
Register Number of the Student
Name of the Student
Section
Batch Name
Signature of the Student
Date of the Experiment Conduction

Lab Experiment - 4
Aim: Write Verilog code to design following sequential circuits using behavioural modelling.
(i) D Latch
(ii) D Flip-flop
(iii) T Flip-flop
(iv) JK Flip-flop
Tool Used: Xilinx Vivado Design Suite
Theory:

26
27
 (i) D Latch

28
 (ii) D Flip-Flop (Positive Edge Triggered)

(iii) T Flip-Flop (Toggle Flip-Flop)

(iv) JK Flip-Flop

29
Result:

For Faculty Use Only

Continuous Assessment
(5 Marks)
Faculty Signature with Date

Any Remarks

30
 Amrita Vishwa Vidyapeetham
Amrita School of Engineering, Bengaluru
Department of ECE
B. Tech. V Semester ECE & EAC
AY2025-2026
23ECE383 VLSI Design Laboratory
Register Number of the Student
Name of the Student
Section
Batch Name
Signature of the Student
Date of the Experiment Conduction

Lab Experiment – 5
Aim: Design and analyse the transient characteristics for CMOS logic schematics. e.g. Inverter,
NAND, NOR, XOR and F = (AB+C)’ etc.
Tool Used: DSCH2 (Digital Schematic Editor) or Cadence Virtuoso at 45 nm technology.
Theory
A CMOS inverter contains a PMOS and a NMOS transistor connected at the drain and gate
terminals. A supply voltage Vdd is connected at the PMOS source terminal, and ground is connected
at the NMOS source terminal. The input Vin is connected to the gate terminals and Voutt is
connected to the drain terminals as shown in Figure 1.1.

Figure 1.1 CMOS Schematic for Inverter

When a high voltage (~ Vdd) is given at input terminal (Vin) of the inverter, the PMOS becomes an
open circuit, and NMOS switched OFF so the output will be pulled down to Vss or Gnd. When a
low-level voltage (<Vdd, ~0v) applied to the inverter, the NMOS switched OFF and PMOS switched
ON. So, the output becomes Vdd or the circuit is pulled up to Vdd.

31
 Truth Table
Vin Vout PMOS NMOS
0 1 ON OFF
1 0 OFF ON
Expected Output

Transient Characteristics of CMOS Inverter

CMOS NAND Gate
NAND gate is actually a combination of two logic gates, AND gate followed by NOT gate.

Symbol for 2-input NAND gate

The CMOS schematic for 2-input NAND gate is shown in Figure. It consists of two series NMOS
transistors between output Vout and Ground and two parallel PMOS transistors between Vout and
VDD. If either input A or B is logic 0, at least one of the NMOS transistors will be OFF, breaking
the path from Vout to Ground. But at least one of the PMOS transistors will be ON, creating a path
from Vout to VDD. Hence, the output Y will be high. If both inputs are high, both of the NMOS
transistors will be ON and both of the PMOS transistors will be OFF. Hence, the output will be logic
low.

CMOS Schematic for 2-input NAND gate

32
 Truth Table
A B Vout
0 0 1
0 1 1
1 0 1
1 1 0
Expected Output

Transient Characteristics of 2-input CMOS NAND gate

CMOS NOR Gate
NOR gate is actually a combination of two logic gates, OR gate followed by NOT gate.

Symbol for 2-input NOR gate

The CMOS schematic for 2-input NOR gate is shown in Figure 1.3. The NMOS transistors are in
parallel to pull the output low when either input is high. The PMOS transistors are in series to pull
the output high when both inputs are low, as given in the Truth table. The output is never left floating.

CMOS Schematic for 2-input NOR gate

33
 Truth Table
A B Vout
0 0 1
0 1 1
1 0 1
1 1 0
Expected Output

Transient Characteristics of 2-input CMOS NOR gate

Ex-OR and Ex-NOR gates are special type of gate used in different types of computational circuits.
Apart from the AND, OR, NOT, NAND, and NOR gate, there are two special gates, i.e., Ex-OR and
Ex-NOR. These gates are not basic gates in their own and are constructed by combining with other
logic gates. Their Boolean output function is significant enough to be considered as a complete logic
gate. The XOR and XNOR gates are the hybrids gates.

CMOS Ex-OR Gate

Symbol for 2-input Ex-OR gate

For a 2-input Ex-OR gate output is high when the inputs are different.
Truth Table
A B F
0 0 0
0 1 1
1 0 1
1 1 0

To draw CMOS schematic for 2-input Ex-OR gate-

34
 𝐹 = 𝐴′ 𝐵 + 𝐴𝐵 ′
𝐹 ′ = 𝐴′ 𝐵 + 𝐴𝐵′
Apply Demorgan’s Theorem
𝐹 ′ = (𝐴 + 𝐵 ′ )(𝐴′ + 𝐵)
𝐹 ′ = (𝐴𝐵 + 𝐴′ 𝐵 ′ )

CMOS Schematic for 2-input Ex-OR gate

Expected Output

Transient Characteristics of 2-input CMOS Ex-OR gate

CMOS Ex-NOR Gate

Symbol for 2-input Ex-NOR gate

35
For a 2-input Ex-NOR gate output is high when both the inputs are same.
Truth Table
A B F
0 0 1
0 1 0
1 0 0
1 1 1
To draw CMOS schematic for 2-input Ex-NOR gate-
𝐹 = 𝐴𝐵 + 𝐴′𝐵 ′
𝐹 ′ = 𝐴𝐵 + 𝐴′𝐵′
Apply Demorgan’s Theorem
𝐹 ′ = (𝐴′ + 𝐵 ′ )(𝐴 + 𝐵)
𝐹 ′ = (𝐴′𝐵 + 𝐴𝐵′)

CMOS Schematic for 2-input Ex-NOR gate

Expected Output

Transient Characteristics of 2-input Ex-NOR gate

36
The CMOS schematic for function 𝑓 = ̅̅̅̅̅̅̅̅̅̅
𝑎𝑏 + 𝑐 can be drawn and verified using Truth table of
function f.

CMOS Schematic for the function 𝑓 = ̅̅̅̅̅̅̅̅̅̅

𝑎𝑏 + 𝑐

Expected Output can be verified by using truth table for 𝑓 = ̅̅̅̅̅̅̅̅̅̅

𝑎𝑏 + 𝑐 = 𝑓 (𝑎, 𝑏, 𝑐) = ∑𝑚(0, 1, 2, 4)

37
Result:

For Faculty Use Only

Continuous Assessment
(5 Marks)
Faculty Signature with Date

Any Remarks

38
 Amrita Vishwa Vidyapeetham
Amrita School of Engineering, Bengaluru
Department of ECE
B. Tech. V Semester ECE & EAC
AY2025-2026
23ECE383 VLSI Design Laboratory
Register Number of the Student
Name of the Student
Section
Batch Name
Signature of the Student
Date of the Experiment Conduction

Lab Experiment – 6
Aim: Design and analyse the transient characteristics for D-Flip Flop, JK Flipflop, and T-Flip Flop
using CMOS logic in schematic.
Tool Used: DSCH2 (Digital Schematic Editor) or Cadence Virtuoso at 45 nm technology.
Theory:
Flip-Flop
• Flip-flop is a basic digital memory circuit, which stores one bit of information. Flip flops are
the fundamental blocks of most sequential circuits that are used as memory elements.
• It is also known as a bistable multivibrator or a binary or one-bit memory.
• The state of flip-flop changes at the active state of clock pulses and remains unaffected when
the clock pulse is not active.
• Flip-flops are edge-triggered circuits.
• A D flip-flop can be designed with the help of two D latches.

D Latch
A latch is an electronic device that can be used to store one bit of information. Latches are level-
sensitive circuits. For positive level triggered D latch or Data latch is used to capture, or ‘latch’ the
logic level which is present on the Data line when the clock input is high. When the Clk input falls
to logic 0, the last state of the D input is trapped and held in the latch. A positive level triggered D
latch circuit with its truth table and graphical symbol is shown in Figure.

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 D Latch

D Flip-Flop (Negative edge triggered)

The D flip-flop captures the value of the D-input at a definite portion of the clock cycle (such as the
rising edge of the clock or falling edge of the clock). That captured value becomes the Q output. At
other times, the output Q does not change. The D flip-flop can be viewed as a memory cell, or a
delay line. A negative edge triggered D flip-flop with its truth table and graphical symbol is shown
in Figure.

Negative edge triggered D flip-flop

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 Expected Output

Timing Diagram for D-Latch and D-Flip flop

JK Flip-flop (Negative edge triggered)

The JK flip flop is basically a gated SR flip-flop with the addition of a clock input circuitry that
prevents the illegal or invalid output condition that can occur when both inputs S and R are equal to
logic level “1”. Due to this additional clocked input, a JK flip-flop has four possible input
combinations, “logic 1”, “logic 0”, “no change” and “toggle”. Figure shows logic circuit for a
negative edge triggered JK flip flop designed using D flip-flop, its truth table and graphical symbol.

JK flip-flop using D flip-flop

Expected Output

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 Timing Diagram for negative edge-triggered JK flip-flop

T Flip-Flop (Negative edge triggered)

A clocked flip-flop whose output “toggles”, i.e. changes to the complementary logic state, on every
active transition of the clock signal when t input is high. The device acts as a divide-by-two counter
since two active transitions of the clock signal generate one active transition of the output. It can be
considered as being equivalent to a JK flip-flop whose J and K inputs are shorted. A negative edge-
triggered T flip-flop designed using D flip-flop with its truth table and graphical symbol is shown in
Figure.

T flip-flop using D flip-flop

Expected Output

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 Timing Diagram for negative edge-triggered T flip-flop

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Result:

For Faculty Use Only

Continuous Assessment
(5 Marks)
Faculty Signature with Date

Any Remarks

44
 Amrita Vishwa Vidyapeetham
Amrita School of Engineering, Bengaluru
Department of ECE
B. Tech. V Semester ECE & EAC
AY2025-2026
23ECE383 VLSI Design Laboratory
Register Number of the Student
Name of the Student
Section
Batch Name
Signature of the Student
Date of the Experiment Conduction

Lab Experiment – 7
Aim: Design and analyse the transient Characteristics for advanced CMOS circuits like Pseudo
nMOS circuit, Mirror circuit and Dynamic logic circuit etc.

Tool Used: DSCH2 (Digital Schematic Editor) or Cadence Virtuoso at 45 nm technology.

Theory:
Pseudo nMOS Circuit

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46
Dynamic Circuit

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Result:

For Faculty Use Only

Continuous Assessment
(5 Marks)
Faculty Signature with Date

Any Remarks

48
 SYSTEM DESIGN

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