VLSI D ECS
Chapter 1
VLSI Design flow and Technology Trends
The development of microelectronics spans a time which is even lesser than the average life
expectancy of a human, and yet it has seen as many as four generations. Early 60’s saw the
low-density ssrication processes classified under Small Scale Integration (SSI) in which
transistor count was limited to about 10. This rapidly gave way to Medium Scale Integration
in the late 60’s when around 100 transistors could be placed on a single chip. Transistor-
Transistor logic (TTL) offering higher integration densities outlasted other IC families like
Emitter coupled logic (ECL) and became the basis of the first integrated circuit revolution. It
was the production of this family that gave impetus to semiconductor giants like Texas
Instruments, Fairchild and National Semiconductors. Early seventies marked the growth of
transistor count to about 1000 per chip called the Large-Scale Integration. The transistor
count on a single chip had already exceeded 1000 and hence came the age of Very Large-
Scale Integration or VLSI having 100000 transistors.
Integrated circuit
It is a circuit where all discrete components such as passive as well as active elements are
fabricate done single crystal chips.
• The first semiconductor chip held two transistors each.
• The first integrated circuits held only a few devices, perhaps as many as ten diodes,
transistors, resistors, and capacitors, making it possible to fabricate one or more logic
gates on a single device. As on increasing the number of components (or transistors) per
integrated circuit the technology was developed as:
Small scale integration (SSI)The technology was developed by integrating the number
oftransistors of 1-100 on a single chip. Ex: Gates, flip-flops, op-amps.
Medium scale integration (MSI) The technology was developed by integrating the
number of transistors of 100-1000 on a single chip. Ex: xCounters, MUX, adders, 4-bit
microprocessors.
Large scale integration (LSI)The technology was developed by integrating the number
of transistors of 1000-10000 on a single chip. Ex:8-bit microprocessors,ROM,RAM.
Very large-scale integration (VLSI)The technology was developed by integrating the
number of transistors of 10000-1Million on a single chip. Ex:16-32-bit microprocessors,
peripherals, complimentary high MOS.
NO 1
VLSI D ECS
NO 2
VLSI D ECS
NO 3
VLSI D ECS
Basics of IC Fabrication:
A. STARTING MATERIAL
Silicon is the material most commonly used for the manufacturing of semiconductors.
Silicon is not found in pure chemical form in nature.
Silicon occurs chiefly as a compound of silicon and oxygen called an oxide or as a compound
of silicon and salts called a silicate.
Silicon in the form of an oxide most commonly occurs as silicon dioxide, SiO 2, generally
called silica, or sand.
1. Purification
Silicon for semiconductor applications is taken from quartzite, the rock form
of silicon dioxide. Quartzite has trace levels of other elements that must be removed in the
purification process. It is reacted chemically with coal at a temperature of about 2000 C to
form metallurgical grade silicon (MGS) that is 98% pure, which is not good enough for
semiconductor use, so must be further purified.
This silicon is reacted with very strong hydrochloric acid (similar to strong swimming
pool acid) to form a new liquid called trichlorosilane. The liquid is then purified by fractional
distillation (similar to the distillation process to make whiskey). The resulting, highly purified
trichlorosilane liquid is converted to polycrystalline electronic grade silicon (EGS) by the
Siemens' process. The Siemens' process changes the liquid into a solid polycrystalline silicon
(usually called polysilicon) rod.
NO 4
VLSI D ECS
2. Czochralski Crystal Growing:
The next process step converts the very pure silicon from a polysilicon crystal
form into a single crystal or monocrystalline form. This process is known as Czochralski
crystal growing, often called Cz, the abbreviation for Czochralski.
3. Sawing Crystal Into Wafers
The next sequence of process steps involves sawing the ingot into the
individual wafers and edge
grinding the outer edge of the wafer circumference to a controlled shape.
4. Wafer Preparation
The wafer is double-side (both sides simultaneously) lapped to reduce the
surface roughness and then chemically etched to further smooth both sides of the wafer
surface. A final surface polish is done on the designated side of the wafer. The designated
side is determined by the ground wafer flat(s). The final surface must be very smooth (like a
mirror) and free of surface defects and imperfections. A final chemical cleaning process will
remove the polishing materials, particulants and any other potentially contaminating
materials. These process steps are illustrated in Figure 2-5. Electrical and mechanical
evaluation completes the processing.
NO 5
VLSI D ECS
B. DIELECTRIC FORMATION
A dielectric is a material that is a poor conductor of electricity or does not conduct at all.
Dielectric layers are often called insulators. Dielectric layers play a critical role in the
manufacturing and operation of semiconductors. They are used:
• for insulation between conducting layers (e.g., for devices with more than one level of metal
and to separate the gate from the silicon in an MOS transistor),
• to protect the surface of a completed die,
• to mask off portions of the surface of the wafer during some manufacturing operations, and
• between the plates of capacitors in ICs.
Various forms of dielectrics related to semiconductors include silicon dioxide, silicon
nitride, and silicon oxynitride. The most common is silicon dioxide
Thermally Grown Silicon Dioxide:
NO 6
VLSI D ECS
Silicon has a very unique property when exposed to any source of oxygen. A
chemical reaction that forms silicon dioxide (SiO2) will occur. Silicon dioxide is a very
stable dielectric or insulating material.
In semiconductor manufacturing, thermal oxidation is a well understood process. The
process is done in the temperature range of 750°C to 1150°C to increase the reaction rate.
The rate of oxidation also depends on the source of oxygen and the pressure inside the
process chamber. The process parameters of time, temperature, oxygen source and pressure
are determined by the overall process requirements and circuit design considerations.
Silicon dioxide can be formed by manufacturing techniques other than thermal
oxidation. One isknown as Chemical Vapor Deposition (CVD).
C. PHOTOLITHOGRAPHY:
In the photolithography process sequence, the wafer is covered with a layer of light-
sensitive material (photoresist), which is then selectively exposed to light. The selective
exposure is accomplished by shining the light through a quartz plate (mask or reticle) with a
patterned opaque material on it (Figure 2-14).
The exposed photo resist is washed away and the remaining, unexposed photoresist is
hardened by baking. The portions of the layer below the photoresist not covered by the
hardened photoresist is removed and then the photoresist is removed (Figure 2-15).
NO 7
VLSI D ECS
Photoresist, Negative and Positive
There are two kinds of photoresist commonly used: negative and positive. The
chemical behavior of each resist is illustrated in Figure 2-22. The negative resist responds to
the radiation (UV light) in a manner that prevents the developer solution from removing the
exposed resist. The image formed in the resist is the same as the clear area on the mask. The
unexposed resist is removed by the developing process. Positive photoresist has the opposite
response to the radiation. The areas of the photoresist that are exposed are removed by the
developer solution. Thus, the unexposed resist remains and forms the image on the surface of
the wafer. The chemistries of positive and negative photoresist are very different. Positive
photoresist is developed with a mild alkaline (basic) solution and the negative resist requires
a solvent (xylene) for developing.
NO 8
VLSI D ECS
3. Masks
NO 9
VLSI D ECS
A photomask is a quartz plate with one layer of patterns for all of the ICs on a wafer on it. A
reticle only has the patterns for a few ICs on it . The patterns are formed with opaque
substances such as emulsion or chrome.
E. JUNCTION FORMATION:
Dopant atoms are added to the silicon lattice when the silicon ingot is grown to provide the
electrical characteristics of the wafer (N-type or P-type). During the process of producing ICs
on the wafer, atoms of the same polarity as the wafer or of the opposite polarity must be
introduced into the wafer in selected regions. This alteration of the dopantlevels is done by
solid-state diffusion or ion implantation
NO 10
VLSI D ECS
D. Etch:
The etching process removes the material not protected by the hardened photoresist. The
result of the etching process was illustrated in Figure 2-15 for positive resist .The etching
process is essentially a subtractive process to remove the material not protected by the
photoresist.
NO 11
VLSI D ECS
F. EPITAXIAL DEPOSITION:
The term epitaxial is derived from Greek, meaning to build upon. Epitaxial deposition, in
general, is the deposition of a layer of single-crystal silicon on a single-crystal
(monocrystalline)wafer. The deposited layer is a crystallographic extension of the substrate in
terms of atomic order (i.e., it has the same crystal structure). Thus, the substrate could be
considered the "seed" that is necessary to promote the single-crystal deposition.
G. POLYSILICON DEPOSITION:
Polysilicon deposition is another application of CVD technology for thin films.
Unlike epi, polysilicon is not required to follow the crystal orientation of the substrate (e.g.,
poly on silicon dioxide, which is amorphous). Thin-film polysilicon has many important
applications in the semiconductor industry.
NO 12
VLSI D ECS
Heavily-doped polysilicon has become the most widely used gate-electrode material
for MOS products, both discretes and ICs. In addition, it serves as an interconnect, capacitor
plate(s), doping source, and can be oxidized to form a stable layer of SiO2.
H. METAL DEPOSITION:
Metal (usually aluminum or aluminum with a small amount of other materials) is used
to connect the individual components (diodes, transistors, resistors, and capacitors) in an
integrated circuit. A layer of metal is deposited on the entire top surface of a wafer. Through
photolithography and etch, selected portions of the metal are removed. The remaining
aluminum serves as the conductors (wires) between the various components of each IC.
Fabrication of the nMOS Transistor:
NO 13
VLSI D ECS
NO 14
VLSI D ECS
NO 15
VLSI D ECS
NO 16
VLSI D ECS
CMOS Fabrication Process:
The CMOS can be fabricated using different processes such as:
• N-well process for CMOS fabrication
• P-well process
• Twin tub-CMOS-fabrication process
NO 17
VLSI D ECS
Latchup prevention:
It is possible to design chips that are latchup-resistant, where a layer of insulating oxide
(called a trench) surrounds both the NMOS and the PMOS transistors. This breaks the
parasitic SCR structure between these transistors. Such parts are important in the cases where
the proper sequencing of power and signals cannot be guaranteed (e.g., in hot swap devices).
Devices fabricated in lightly doped epitaxial layers grown on heavily doped substrates are
also less susceptible to latchup. The heavily doped layer acts as a current sink where excess
minority carriers can quickly recombine.
Another possibility for a latchup prevention is the Latchup Protection Technology circuit.
When a latchup is detected, the LPT circuit shuts down the chip and holds it powered-down
for a preset time.
Guidelines for Avoiding Latch-Up:
* Reduce the gains of BJTs by lowering the minority carrier lifetime through gold doping of
the substrate (but without causing excessive leakage currents) or reducing the minority carrier
injection efficiency of BJT emitters by using Schottky source/ drain contacts.
* Usep+ guardband
NO 18
VLSI D ECS
What is Scaling?
• Reduction in size of an MOS chip by reducing the dimensions of MOSFETs and interconnects.
• Reduction is symmetric and preserves geometric ratios which are important to the functioning
of the chip. Ideally, allows design reuse.
• Assume that S is the scaling factor. Then a transistor with original dimensions of L and W
becomes a transistor with dimensions L/S and W/S.
• Typical values of S: 1.2 to 1.5 per biennium:
• Two major forms of scaling
Full scaling (constant-field scaling) – All dimensions are scaled by S and the supply voltage and
other voltages are so scaled.
Constant-voltage scaling – The voltages are not scaled and, in some cases, dimensions
associated with voltage are not scaled.
Full Scaling (Constant-Field Scaling)
This scaling option attempts to preserve the magnitude of internal electric fields in the
MOSFET, while the dimensions are scaled down by a factor of S. To achieve this goal, all
potentials must be scaled down proportionally, by the same scaling factor. Note that this
potential scaling also affects the threshold voltage V.0 Finally, the Poisson equation
describing the relationship between charge densities and electric fields dictates that the
charge densities must be increased by a factor of S in order to maintain the field conditions.
Table 3.2 lists the scaling factors for all significant dimensions, potentials, and doping
densities of the MOS transistor.
NO 19
VLSI D ECS
NO 20
VLSI D ECS
NO 21
VLSI D ECS
NO 22
VLSI D ECS
Short Channel Effect
In normal mosfet it is assumed that the channel is long and wide enough, so that “edge”
effects along the four sides are negligible, longitudinal field is negligible and electric field at
NO 23
VLSI D ECS
every point is perpendicular to the surface. So we could perform one-dimensional analysis
using gradual channel approximation. But in devices where channel is short longitudinal field
will not be negligible compared to perpendicular field. So in that case one-dimensional
analysis gives wrong results and we will have to perform dimensional analysis taking into
account both longitudinal and vertical fields.
(which is out of the scope this course)
When is a channel called a shortchannel?
(i) When junction (source/drain) length is of the order of channel length.
(ii)
(iii) L is not much larger then the sum of the drain and source depletion width.
We have shown below the comparative graphs of I-V characteristics for both long channel
and short channel length MOSFETs. From graph, it can be clearly concluded that when the
channel becomes short, the current in saturation region becomes linearly dependent on
applied drain voltage rather than being square dependent.
Comparison of ID vs VDS characteristics for long and short channel MOSFET
device
MOSFET capacitances:
MOSFET capacitances tend to limit the frequency response of circuits.
Inorder to predict the circuit frequency response, we need to estimate the
circuit capacitance.
MOSFET parasitic capacitances are subdivided into two general
categories:1)oxide related capacitances
NO 24
VLSI D ECS
2)junction related capacitances.
NO 25
VLSI D ECS
In linear-mode operation, the inverted channel extends across the MOSFET, between the
source and the drain. This conducting inversion layer on the surface effectively shields the
substrate from the gate electric field; thus, Cgb = 0. In this case, the distributed gate-to-
channel capacitance may be viewed as being shared equally between the source and the drain,
yielding
When the MOSFET is operating in saturation mode, the inversion layer on the surface does
not extend to the drain, but it is pinched off. The gate-to-drain capacitance component is
therefore equal to zero (Cgd = 0) . Since the source is still linked to the conducting channel,
its shielding effect also forces the gate-to-substrate capacitance to be zero, Cgb = 0. Finally,
the distributed gate-to-channel capacitance as seen between the gate and the source can be
approximated by
NO 26
VLSI D ECS
Junction Capacitances:
Consider the voltage-dependent source-substrate and drain-substrate junction
capacitances, Csband Cdb, respectively. Both of these capacitances are due to the depletion
charge surrounding the respective source or drain diffusion regions embedded in the
substrate.
Note that both of these junctions are reverse-biased under normal operating conditions
of the MOSFET and that the amount of junction capacitance is a function of the applied
terminal voltages. Figure 3.33 shows the simplified, partial geometry of a typical n-channel
enhancement MOSFET, focusing on the n-type diffusion region within the p-type substrate.
NO 27
VLSI D ECS
NO 28
VLSI D ECS
NO 29
VLSI D ECS
Modeling of MOS transistors:
SPICE (Simulation Program with Integrated Circuit Emphasis) is a general-purpose
circuit simulator which is used very widely both in the microelectronics industry and in
educational institutions as an essential computer-aided design (CAD) tool for circuit design.
Spice has three built-in MOSFET models: LEVEL 1 (MOS1) is described by a
square-law current-voltage characteristic, LEVEL 2 (MOS2) is a detailed analytical
MOSFET model, and LEVEL 3 (MOS3) is a semi-empirical model. Both MOS2 and MOS3
include second-order effects such as the short-channel threshold voltage, subthreshold
conduction, scattering-limited velocity saturation, and charge-controlled capacitances.
The equivalent circuit structure of the NMOS LEVEL 1 model, which is the default
MOSFET model in SPICE, is shown in Fig. 4.1. This basic structure is also typical for the
LEVEL 2 and LEVEL 3 models. Note that the voltage-controlled current source ID
determines the steady-state current-voltage behavior of the device, while the voltage
controlled(nonlinear) capacitors connected between the terminals represent the parasitic
oxide-related and junction capacitances. The source-substrate and the drain-substrate
junctions, which are reverse-biased under normal operating conditions, are represented by
ideal diodes in this equivalent circuit. Finally, the parasitic source and drain resistances are
represented by the resistors RD and Rs, respectively, connected between the drain current
source and the respective terminals.
The basic geometry of an MOS transistor can be described by specifying the nominal
channel (gate) length L and the channel width W both of which are indicated on the element
description line. The channel width W is, by definition, the width of the area covered by the
NO 30
VLSI D ECS
thin gate oxide. Note that the effective channel length Lefi s defined as the distance on the
surface between the two (source and drain) diffusion regions. Thus, in order to find the
effective channel length, the gate-source overlap distance and the gate drain overlap distance
must be subtracted from the nominal (mask) gate length specified
on the device description line. The amount of gate overlap over the source and the drain can
be specified by using the lateral diffusion coefficient LD in SPICE.
NO 31
VLSI D ECS
In summary, for simple simulation problems the LEVEL 1 model offers a useful estimate of
the circuit performance without using a large number of device model parameters.
NO 32
VLSI D ECS
NO 33
VLSI D ECS
NO 34
VLSI D ECS
Design rules:
The design rules are usually described in two ways:
NO 35
VLSI D ECS
(i) Micron rules, in which the layout constraints such as minimum feature sizes and minimum
allowable feature separations are stated in terms of absolute dimensions in micrometers, or,
(ii) Lambda rules, which specify the layout constraints in terms of a single parameter
(lambda) and thus allow linear, proportional scaling of all geometrical constraints.
we present a sample set of the lambda-based layout design rules devised for the MOSIS
(MOS Implementation System) CMOS process:
NO 36
VLSI D ECS
NO 37
