III Semester
ANALOG AND DIGITAL ELECTRONICS
Course Code 21CS33 CIE Marks 50
Teaching Hours/Week (L:T:P: S) 3:0:2:0 SEE Marks 50
Total Hours of Pedagogy 40 T + 20 P Total Marks 100
Credits 04 Exam Hours 03
Course Learning Objectives:
CLO 1. Explain the use of photo electronics devices, 555 timer IC, Regulator ICs and uA741
CLO 2. Make use of simplifying techniques in the design of combinational circuits.
CLO 3. Illustrate combinational and sequential digital circuits
CLO 4. Demonstrate the use of flipflops and apply for registers
CLO 5. Design and test counters, Analog-to-Digital and Digital-to-Analog conversion techniques.
Teaching-Learning Process (General Instructions)
These are sample Strategies, which teachers can use to accelerate the attainment of the various course
outcomes.
1. Lecturer method (L) does not mean only traditional lecture method, but different type of
teaching methods may be adopted to develop the outcomes.
2. Show Video/animation films to explain functioning of various concepts.
3. Encourage collaborative (Group Learning) Learning in the class.
4. Ask at least three HOT (Higher order Thinking) questions in the class, which promotes critical
thinking.
5. Adopt Problem Based Learning (PBL), which fosters students’ Analytical skills, develop
thinking skills such as the ability to evaluate, generalize, and analyze information rather than
simply recall it.
6. Topics will be introduced in a multiple representation.
7. Show the different ways to solve the same problem and encourage the students to come up
with their own creative ways to solve them.
8. Discuss how every concept can be applied to the real world - and when that's possible, it helps
improve the students' understanding.
Module-1
BJT Biasing: Fixed bias, Collector to base Bias, voltage divider bias
Operational Amplifier Application Circuits: Peak Detector, Schmitt trigger, Active Filters, Non-Linear
Amplifier, Relaxation Oscillator, Current-to-Voltage and Voltage-to-Current Converter, Regulated
Power Supply Parameters, adjustable voltage regulator, D to A and A to D converter.
Textbook 1: Part A: Chapter 4 (Sections 4.2, 4.3, 4.4), Chapter 7 (Sections 7.4, 7.6 to 7.11), Chapter
8 (Sections 8.1 and 8.5), Chapter 9.
Laboratory Component:
1. Simulate BJT CE voltage divider biased voltage amplifier using any suitable circuit simulator.
2. Using ua 741 Opamp, design a 1 kHz Relaxation Oscillator with 50% duty cycle
3. Design an astable multivibrator circuit for three cases of duty cycle (50%, <50% and >50%)
using NE 555 timer IC.
4. Using ua 741 opamap, design a window comparator for any given UTP and LTP.
Teaching-Learning Process 1. Demonstration of circuits using simulation.
2. Project work: Design a integrated power supply and
function generator operating at audio frequency. Sine,
square and triangular functions are to be generated.
3. Chalk and Board for numerical
Module-2
Karnaugh maps: minimum forms of switching functions, two and three variable Karnaugh maps, four
variable Karnaugh maps, determination of minimum expressions using essential prime implicants,
Quine-McClusky Method: determination of prime implicants, the prime implicant chart, Petricks
method, simplification of incompletely specified functions, simplification using map-entered variables
Textbook 1: Part B: Chapter 5 (Sections 5.1 to 5.4) Chapter 6 (Sections 6.1 to 6.5)
Laboratory Component:
1. Given a 4-variable logic expression, simplify it using appropriate technique and inplement the
same using basic gates.
Teaching-Learning Process 1. Chalk and Board for numerical
2. Laboratory Demonstration
Module-3
Combinational circuit design and simulation using gates: Review of Combinational circuit design,
design of circuits with limited Gate Fan-in, Gate delays and Timing diagrams, Hazards in combinational
Logic, simulation and testing of logic circuits
Multiplexers, Decoders and Programmable Logic Devices: Multiplexers, three state buffers, decoders
and encoders, Programmable Logic devices.
Textbook 1: Part B: Chapter 8, Chapter 9 (Sections 9.1 to 9.6)
Laboratory Component:
1. Given a 4-variable logic expression, simplify it using appropriate technique and realize the
simplified logic expression using 8:1 multiplexer IC.
2. Design and implement code converter I) Binary to Gray (II) Gray to Binary Code
Teaching-Learning Process 1. Demonstration using simulator
2. Case study: Applications of Programmable Logic device
3. Chalk and Board for numerical
Module-4
Introduction to VHDL: VHDL description of combinational circuits, VHDL Models for multiplexers,
VHDL Modules.
Latches and Flip-Flops: Set Reset Latch, Gated Latches, Edge-Triggered D Flip Flop 3,SR Flip Flop, J K
Flip Flop, T Flip Flop.
Textbook 1: Part B: Chapter 10(Sections 10.1 to 10.3), Chapter 11 (Sections 11.1 to 11.7)
Laboratory Component:
1. Given a 4-variable logic expression, simplify it using appropriate technique and simulate the
same in HDL simulator
2. Realize a J-K Master / Slave Flip-Flop using NAND gates and verify its truth table. And
implement the same in HDL.
Teaching-Learning Process 1. Demonstration using simulator
2. Case study: Arithmetic and Logic unit in VHDL
3. Chalk and Board for numerical
Module-5
Registers and Counters: Registers and Register Transfers, Parallel Adder with accumulator, shift
registers, design of Binary counters, counters for other sequences, counter design using SR and J K Flip
Flops.
Textbook 1: Part B: Chapter 12 (Sections 12.1 to 12.5)
Laboratory Component:
1. Design and implement a mod-n (n<8) synchronous up counter using J-K Flip-Flop ICs and
demonstrate its working.
2. Design and implement an asynchronous counter using decade counter IC to count up from 0 to
n (n<=9) and demonstrate on 7-segment display (using IC-7447)
Teaching-Learning Process 1. Demonstration using simulator
2. Project Work: Designing any counter, use LED / Seven-
segment display to display the output
3. Chalk and Board for numerical
Course outcome (Course Skill Set)
At the end of the course the student will be able to:
CO 1. Design and analyze application of analog circuits using photo devices, timer IC, power supply
and regulator IC and op-amp.
CO 2. Explain the basic principles of A/D and D/A conversion circuits and develop the same.
CO 3. Simplify digital circuits using Karnaugh Map, and Quine-McClusky Methods
CO 4. Explain Gates and flip flops and make us in designing different data processing circuits,
registers and counters and compare the types.
CO 5. Develop simple HDL programs
Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%.
The minimum passing mark for the CIE is 40% of the maximum marks (20 marks). A student shall be
deemed to have satisfied the academic requirements and earned the credits allotted to each subject/
course if the student secures not less than 35% (18 Marks out of 50) in the semester-end examination
(SEE), and a minimum of 40% (40 marks out of 100) in the sum total of the CIE (Continuous Internal
Evaluation) and SEE (Semester End Examination) taken together
Continuous Internal Evaluation:
Three Unit Tests each of 20 Marks (duration 01 hour)
1. First test at the end of 5th week of the semester
2. Second test at the end of the 10th week of the semester
3. Third test at the end of the 15th week of the semester
Two assignments each of 10 Marks
4. First assignment at the end of 4th week of the semester
5. Second assignment at the end of 9th week of the semester
Practical Sessions need to be assessed by appropriate rubrics and viva-voce method. This will contribute
to 20 marks.
Rubrics for each Experiment taken average for all Lab components – 15 Marks.
Viva-Voce– 5 Marks (more emphasized on demonstration topics)
The sum of three tests, two assignments, and practical sessions will be out of 100 marks and will be
scaled down to 50 marks
(to have a less stressed CIE, the portion of the syllabus should not be common /repeated for any of the
methods of the CIE. Each method of CIE should have a different syllabus portion of the course).
CIE methods /question paper has to be designed to attain the different levels of Bloom’s
taxonomy as per the outcome defined for the course.
Semester End Examination:
Theory SEE will be conducted by University as per the scheduled timetable, with common question
papers for the subject (duration 03 hours)
1. The question paper will have ten questions. Each question is set for 20 marks. Marks scored
shall be proportionally reduced to 50 marks
2. There will be 2 questions from each module. Each of the two questions under a module (with a
maximum of 3 sub-questions), should have a mix of topics under that module.
The students have to answer 5 full questions, selecting one full question from each module.
Suggested Learning Resources:
Textbooks
1. Charles H Roth and Larry L Kinney and Raghunandan G H Analog and Digital Electronics,
Cengage Learning,2019
Reference Books
1. Anil K Maini, Varsha Agarwal, Electronic Devices and Circuits, Wiley, 2012.
2. Donald P Leach, Albert Paul Malvino & Goutam Saha, Digital Principles and Applications, 8th
Edition, Tata McGraw Hill, 2015.
3. M. Morris Mani, Digital Design, 4th Edition, Pearson Prentice Hall, 2008.
4. David A. Bell, Electronic Devices and Circuits, 5th Edition, Oxford University Press, 2008
Weblinks and Video Lectures (e-Resources):
1. Analog Electronic Circuits: https://nptel.ac.in/courses/108/102/108102112/
2. Digital Electronic Circuits: https://nptel.ac.in/courses/108/105/108105132/
3. Analog Electronics Lab: http://vlabs.iitkgp.ac.in/be/
4. Digital Electronics Lab: http://vlabs.iitkgp.ac.in/dec
Activity Based Learning (Suggested Activities in Class)/ Practical Based learning
1. Real world problem solving - applying the design concepts of oscillator, amplifier, switch, Digital
circuits using Opamps, 555 timer, transistor, Digital ICs and design a application like tone
generator, temperature sensor, digital clock, dancing lights etc.
