8086 interrupts

INTERRUPTS
There are two main types of interrupt in the 8086 microprocessor, internal and external hardware
interrupts. Hardware interrupts occur when a peripheral device asserts an interrupt input pin of the
microprocessor. Whereas internal interrupts are initiated by the state of the CPU (e.g. divide by zero
error) or by an instruction.
Provided the interrupt is permitted, it will be acknowledged by the processor at the end of the current
memory cycle. The processor then services the interrupt by branching to a special service routine
written to handle that particular interrupt. Upon servicing the device, the processor is then instructed
to continue with what is was doing previously by use of the "return from interrupt" instruction.
The status of the programme being executed must first be saved. The processors registers will be
saved on the stack, or, at very least, the programme counter will be saved. Preserving those registers
which are not saved will be the responsibility of the interrupt service routine. Once the programme
counter has been saved, the processor will branch to the address of the service routine.

Edge or Level sensitive Interrupts

Edge level interrupts are recognised on the falling or rising edge of the input signal. They are
generally used for high priority interrupts and are latched internally inside the processor. If this
latching was not done, the processor could easily miss the falling edge (due to its short duration) and
thus not respond to the interrupt request.
Level sensitive interrupts overcome the problem of latching, in that the requesting device holds the
interrupt line at a specified logic state (normally logic zero) till the processor acknowledges the
interrupt. This type of interrupt can be shared by other devices in a wired 'OR' configuration, which is
commonly used to support daisy chaining and other techniques.

Maskable Interrupts
The processor can inhibit certain types of interrupts by use of a special interrupt mask bit. This mask
bit is part of the flags/condition code register, or a special interrupt register. In the 8086

microprocessor if this bit is clear, and an interrupt request occurs on the Interrupt Request input, it is
ignored.
Non-Maskable Interrupts
There are some interrupts which cannot be masked out or ignored by the processor. These are
associated with high priority tasks which cannot be ignored (like memory parity or bus faults). In
general, most processors support the Non-Maskable Interrupt (NMI). This interrupt has absolute
priority, and when it occurs, the processor will finish the current memory cycle, then branch to a
special routine written to handle the interrupt request.
Advantages of Interrupts
Interrupts are used to ensure adequate service response times by the processing. Sometimes, with
software polling routines, service times by the processor cannot be guaranteed, and data may be lost.
The use of interrupts guarantees that the processor will service the request within a specified time
period, reducing the likelihood of lost data.
Interrupt Latency
The time interval from when the interrupt is first asserted to the time the CPU recognises it. This will
depend much upon whether interrupts are disabled, prioritized and what the processor is currently
executing. At times, a processor might ignore requests whilst executing some indivisible instruction
stream (read-write-modify cycle). The figure that matters most is the longest possible interrupt latency
time.
Interrupt Response Time
The time interval between the CPU recognising the interrupt to the time when the first instruction of
the interrupt service routine is executed. This is determined by the processor architecture and clock
speed.
The Operation of an Interrupt sequence on the 8086 Microprocessor:
1. External interface sends an interrupt signal, to the Interrupt Request (INTR) pin, or an internal
interrupt occurs.
2. The CPU finishes the present instruction (for a hardware interrupt) and sends Interrupt
Acknowledge (INTA) to hardware interface.
3. The interrupt type N is sent to the Central Processor Unit (CPU) via the Data bus from the
hardware interface.
4. The contents of the flag registers are pushed onto the stack.
5. Both the interrupt (IF) and (TF) flags are cleared. This disables the INTR pin and the trap or singlestep
feature.
6. The contents of the code segment register (CS) are pushed onto the Stack.
7. The contents of the instruction pointer (IP) are pushed onto the Stack.
8. The interrupt vector contents are fetched, from (4 x N) and then placed into the IP and from (4 x N
+2) into the CS so that the next instruction executes at the interrupt service procedure addressed by
the interrupt vector.
9. While returning from the interrupt-service routine by the Interrupt Return (IRET) instruction, the
IP, CS and Flag registers are popped from the Stack and return to their state prior to the interrupt

Need for Interrupt: Interrupts are particularly useful when interfacing I/O devices, that provide or
require data at relatively low data transfer rate.
Types of Interrupts: There are two types of Interrupts in 8086. They are:
(i)Hardware Interrupts and
(ii)Software Interrupts
(i) Hardware Interrupts (External Interrupts). The Intel microprocessors support hardware
interrupts through:
Two pins that allow interrupt requests, INTR and NMI
One pin that acknowledges, INTA, the interrupt requested on INTR.

INTR and NMI

INTR is a maskable hardware interrupt. The interrupt can be enabled/disabled using STI/CLI
instructions or using more complicated method of updating the FLAGS register with the help of
the POPF instruction.
When an interrupt occurs, the processor stores FLAGS register into stack, disables further
interrupts, fetches from the bus one byte representing interrupt type, and jumps to interrupt
processing routine address of which is stored in location 4 * <interrupt type>. Interrupt
processing routine should return with the IRET instruction.
NMI is a non-maskable interrupt. Interrupt is processed in the same way as the INTR
interrupt. Interrupt type of the NMI is 2, i.e. the address of the NMI processing routine is stored
in location 0008h. This interrupt has higher priority than the maskable interrupt.
– Ex: NMI, INTR.

(ii) Software Interrupts (Internal Interrupts and Instructions) .Software interrupts can be caused by:
INT instruction – breakpoint interrupt. This is a type 3 interrupt.
INT <interrupt number> instruction – any one interrupt from available 256 interrupts.
INTO instruction – interrupt on overflow
Single-step interrupt – generated if the TF flag is set. This is a type 1 interrupt. When the
CPU processes this interrupt it clears TF flag before calling the interrupt processing routine.
Processor exceptions: Divide Error (Type 0), Unused Opcode (type 6) and Escape opcode
(type 7).
Software interrupt processing is the same as for the hardware interrupts.
When an interrupt occurs (shown in figure 1), regardless of source, the 80x86 does the following:
1. The CPU pushes the flags register onto the stack.
2. The CPU pushes a far return address (segment:offset) onto the stack, segment value first.
3. The CPU determines the cause of the interrupt (i.e., the interrupt number) and fetches the four
byte interrupt vector from address 0:vector*4.
4. The CPU transfers control to the routine specified by the interrupt vector table entry.