B.

Tech: III YEAR

(ECE)

Microelectronics & VLSI Design

Department of Electronics and Communication Engineering

University of Allahabad
VLSI: Very Large Scale Integration

• Integration: Integrated Circuits

• multiple devices on one substrate
• How large is Very Large?
• SSI (small scale integration)
• 7400 series, 10-100 transistors
• MSI (medium scale)
• 74000 series 100-1000
• LSI 1,000-10,000 transistors
• VLSI > 10,000 transistors
• ULSI/SLSI (some disagreement)
Introduction
• Since two decades, digital electronics has been the important part of our lives
in terms of communication.
• It has made its influence in every sector like business, health care, agriculture
and communication.
• The advancement in technology leads to low power and high performance
Integrated Circuits (ICs).
• CMOS technology has facilitated the Si-based nano-electronics industries to
accommodate the market demand.
• CMOS technology offers billions of transistors to be integrated in an IC
[1,2].
• CMOS technology is the most useful technology for digital circuits due to its
property of low leakage.
• It requires to design an efficient transistor with less area and low cost.
• In CMOS technology, the principal module is Metal Oxide Semiconductor
Field Effect Transistor (MOSFET) which is used in the integrated circuit
design.

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Introduction
• To follow the design methodology, according to Moore’s law, International
Technology Roadmap for Semiconductor (ITRS) has been formed [5].
• It is the report produced by semiconductor industry, which survey the challenges
and opportunities comes in the future and possess the rule at every technology
node.
• ITRS employs metrics of power, core and density to standardize the technology
growth of integrated circuits.
• According to Moore’s law the number of transistors in a dense integrated
circuit doubles in every 18 months[6].
• With the latest Intel’s report (figure 1) of this packaging technology declares that
Moore’ law can be followed in the coming years also [7].
• The technology enhancement has followed the improved scaling guidelines
which help to reduce the device size with increase in density.
• By making the transistors and interconnects smaller, more circuits can be
fabricated on each silicon wafer and therefore each circuit becomes cheaper.

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Introduction

Fig. 1: Transistor density at every technology node [7].

5
Introduction
• The main reason to make transistors smaller is to pack more and more
devices in a chip with the same functionality in a smaller area and faster
switching.
• Scaling down the transistor size come to a limit where the original
characteristics of the device cannot be maintained.
• Downsizing the MOS transistor reduces the power dissipation and
capacitance which increases speed.
• Proportional adjustment of the dimensions of an electronic device is required
while maintaining the electrical properties of the device

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Scaling
• To make dense and fast ICs, transistor scaling is an important part of Very
Large Scale Integration (VLSI) design to improve the performance of the IC
designs.
• Microelectronics industry has been strengthened due to the miniaturization of
MOSFET since five decades.
• The lower manufacturing cost, enhanced computing power and data transfer
speed and capability to perform multiple task are the major advantage of
scaling.
• Proportional adjustment of the dimensions of an electronic device is required
while maintaining the electrical properties of the device
• Scaling is known as the reduction of the overall dimensions of the device
keeping the geometrical ratio constant.
• Due to scaling, operational characteristics of the device are changed and
device becomes fast.

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 MOSFET Scaling
• The main reason to make transistors smaller is to pack more and more devices in a chip
with the same functionality in a smaller area and faster switching [1]-[5].
• According to Moore’s law, number of Transistors on an integrated circuit chip doubles*
every 1.5 years [6].
• So, it is therefore necessary to further scale the device in order to save the chip area [7]-
[9].

•Merits:
• Increased Speed
• Increased Packing Density
• Reduced Power
•Challenges:
• Short Channel Effects
• Leakage

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Fig 2. Current Scaling Trend Contd..
VLSI Design Methodologies
Lecture Module

9
Performance Analysis

10
The Process of VLSI Design:
Consists of many different representations/Abstractions of
the system (chip) that is being designed.
• System Level Design
• Architecture / Algorithm Level Design
• Digital System Level Design
• Logical Level Design
• Electrical Level Design
• Layout Level Design
• Semiconductor Level Design (possibly more)

Each abstraction/view is itself a Design Hierarchy of

refinements which decompose the design.
 Design Abstraction Levels

SYSTEM

MODULE
+

GATE

CIRCUIT

DEVICE
G
S D
n+ n+

Digital Integrated Circuits Introduction © Prentice Hall 1995

 MOSFET
• The Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is the
fundamental building block of MOS and CMOS digital integrated circuits.
• Compared to the bipolar junction transistor (BJT), the MOS transistor
occupies a relatively smaller silicon area, and its fabrication involves fewer
processing steps.
• These technological advantages, together with the relative simplicity of
MOSFET operation, have helped make the MOS transistor the most
widely used switching device in LSI and VLSI circuits.
• Here, we will study the basic structure and the electrical behavior of
nMOS (-channel MOS), as well as pMOS (p channel MOS) devices.
• The nMOS transistor is used as the primary switching device in virtually all
digital circuit applications, whereas the pMOS transistor is used mostly in
conjunction with the nMOS device in CMOS circuits.
• However, the basic operation principles of both nMOS and pMOS
transistors are very similar to each other.

[Ref] CMOS Digital Integrated Circuits, Sung-Mo Kang and Yusuf Leblebici

13
 Commonly Used MOS Structure
• This four-terminal consists of a p-
type substrate, in which two n+
diffusion regions, the drain and the
Source is formed.
• The surface of the substrate region
between the drain and the source
with a thin oxide layer, and the
metal (or polysilicon) gate is
deposited on top dielectric.
• The midsection of the device can
easily be recognized as the basic
MOS structure which was examined
in the previous sections.
Fig. 1.2 : n-channel MOSFET
• The two n+ regions will be
conducting terminals of this device.
• The device structure is completely
symmetrical with respect to the
drain and source regions.
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 MOS Capacitance
• Capacitance = Charge / Volt = (C/V). L  LM  2LD

• As we've seen, the charge in a

semiconductor is a complex, 3-
dimensional, distribution due to the
materials, doping, and applied E-field.
• We develop simple approximations
for the MOSFET capacitances for use
in hand calculations.
• We define each of the following Fig. 10: Cross-sectional view and top view
lumped capacitance for an AC model (mask view) of a typical n-channel MOSFET.
of the transistors (Fig. 11).
• Each capacitance will have multiple Fig. 11:
contributions and different values Representation of
depending on the state of the the parasitic MOSFET
capacitances.
transistor (i.e., cutoff, linear,
saturation).
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[Ref] CMOS Digital Integrated Circuits, Sung-Mo Kang and Yusuf Leblebici
 MOS Capacitance
• Consider the capacitances which result from the interaction between the
gate voltage and the channel charge.
• Since the channel region is connected to the source, the drain, and the
substrate, we can identify three capacitances between the gate and these
regions, i.e., Cgs, Cgd and Cgb respectively.
• Notice that in reality, the gate-to-channel capacitance is distributed and
voltage-dependent.
• Then, the gate-to-source capacitance Cgs is actually the gate-to-channel
capacitance seen between the gate and the source terminals.
• The gate-to-drain capacitance Cgd is actually the gate-to-channel
capacitance seen between the gate and the drain terminals.
• A simplified view of their bias-dependence can be obtained by observing
the conditions in the channel region during cut-off, linear, and saturation
modes.

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[Ref] CMOS Digital Integrated Circuits, Sung-Mo Kang and Yusuf Leblebici
 MOS Capacitance
Table: Approximate oxide capacitance values for
three operating modes of the MOS transistor

Fig. 12 Representation of MOSFET oxide capacitances Fig. 13 Variation of the distributed (gate-to-
during (a) cut-off, (b) linear, and (c) saturation modes.. channel) oxide capacitances as functions of Vgs.
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[Ref] CMOS Digital Integrated Circuits, Sung-Mo Kang and Yusuf Leblebici
 Junction Capacitance
• Now we consider the voltage-dependent
source-substrate and drain-substrate
junction capacitances, Csb and Cdb,
respectively.
• Both of these capacitances are due to the
depletion charge surrounding the
respective source or drain diffusion
regions embedded in the substrate. Fig. 14 Three-dimensional view of the n+
• The calculation of the associated junction diffusion region within the p-type
capacitances is complicated by the three- substrate.
dimensional shape of the diffusion regions Table Types and areas of the pn-
that form the source-substrate and the junctions shown in Figure 14.
drain-substrate junctions.
• Note that both of these junctions are
reverse-biased under normal operating
conditions of the MOSFET and that the
amount of junction capacitance is a
function of the applied terminal voltages.

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[Ref] CMOS Digital Integrated Circuits, Sung-Mo Kang and Yusuf Leblebici
 Junction Capacitance
• To calculate the depletion capacitance of a reverse-biased abrupt pn-junction, consider
first the depletion region thickness, Xd.
• Assuming that the n-type and p-type doping densities are given by ND and NA,
respectively, and that the reverse bias voltage is given by V (negative), the depletion
region thickness can be found as follows:

• Where the built-in junction potential is calculated as

• Note that the junction is forward-biased for a positive bias voltage V, and reverse-
biased for a negative bias voltage. The depletion-region charge stored in this area can
be written in terms of the depletion region thickness, xd.

• Here, A indicates the junction area. The junction capacitance

associated with the depletion region is defined as:
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[Ref] CMOS Digital Integrated Circuits, Sung-Mo Kang and Yusuf Leblebici
 Junction Capacitance
• By differentiating with respect to the bias voltage V, we can now obtain the expression
for the junction capacitance as follows.

• This expression can be rewritten in a more general form, to account for the junction
grading.

• The parameter m is called the grading coefficient. Its value is equal to 1/2 for an abrupt
junction profile, and 1/3 for a linearly graded junction profile. The zero-bias junction
capacitance per unit area Cjo is defined as

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[Ref] CMOS Digital Integrated Circuits, Sung-Mo Kang and Yusuf Leblebici
 MOSFET Second Order Effects (SOEs)

Channel Length Modulation

-The 1st order I-V equations derived earlier are not 100% accurate. They are sufficient for 1st order hand calculations.

- We can modify these I-V equations to include other effects that alter the I-V characteristics of a
MOSFET

- Channel Length Modulation refers to additional IDS current that exists in the saturation mode
that is not modeled by the 1st order I-V equations

- When the channel is pinched off in saturation

by a distance L, a depletion region is created
next to the Drain that is L wide

- Given enough energy, electrons in the inversion

layer can move through this depletion region
and into the Drain thus adding additional
current to IDS
 MOSFET Second Order Effects (SOEs)

Channel Length Modulation

- We can model this additional saturation current by multiplying the I DS expression by:

1 VDS
- is called the channel length modulation coefficient and is determined via empirical methods

- This term alters the IDS-SAT expression to be:

k 2
I DS sat VGS VT 0 1 VDS
2
 MOSFET Second Order Effects (SOEs)

Substrate Bias Effect

- Another effect that the 1st order I-V equations don't model is substrate bias

- We have assumed that the Silicon substrate is at the same potential as the Source of the MOSFET

- If this is not the case, then the Threshold Voltage may increase and take more energy to induce
a channel

- We've already seen how we can model the change in threshold voltage due to substrate bias:

VT VT 0 . 2 f VSB 2 f

- For the I-V equations to accurately model the substrate bias effect, we must use VT instead of VT0

k 2
I DSlinear 2 VGS VT VDS VDS
2
k 2
I DS sat VGS VT 1 VDS
2
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 Short-Channel Effects (SCEs)
• When the geometry of the MOSFET is reduced, it is necessary to design the device in proportion without any
variation in channel behaviour.
• The channel is called short when the length of the channel of the MOSFET is approximately close to the sum of
depletion thickness of source and drain junction.
• Due to shortening of channel length, other dimensions of the MOSFET are reduced in proportion like oxide
thickness and other dimensions. It leads to performance deterioration.

Fig.: Types of Short Channel Effects

1
Contd..
 SCE: Threshold Voltage Roll-off
• Reduction of threshold voltage due to the
channel length reduction is known as
threshold voltage roll-off.

• Gate has less control of charge in the depletion

region due to the charge sharing effect
between the channel and source/drain depletion
region.

• So, potential barrier is reduced.

• Vth is further reduced by increment in drain Fig.: Threshold Voltage Roll-off

voltage.

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Contd..
SCE: Drain Induced Barrier Lowering
• In MOSFET, inversion layer is dependent on gate electrode potential.
• Potential barrier obstruct the current flow between source and drain region.
• In long channel MOSFET, only gate voltage is responsible for change in barrier height. There is no change in
barrier height when drain voltage is varied.
• So, threshold voltage does not vary with drain to source voltage.
• Channel length below 100nm is termed as short channel.
• Barrier height is small in the case of short channel MOSFET, yet it is control by gate voltage.
• At lower drain voltage, the characteristics of the device does not change. However, at higher value barrier height
changes when gate voltage is constant.
• Lowering of potential barrier due to induction of drain voltage is termed as Drain Induced barrier lowering
(DIBL).
• Due to the variation of drain voltage, threshold voltage is also changed. DIBL can be measured as:

Vth Vth1 − Vth 2

DIBL = = (2)
VDS VDS 1 − VDS 2
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Contd..
SCE: Drain Induced Barrier Lowering

Fig. : Impact of drain fluctuation on long channel MOSFET

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Fig.: Impact of drain fluctuation on short channel MOSFET
Contd.. 4
SCE: Hot Carrier Effects
• In scaled device, there is high electric field along longitudinal and transverse direction in pinch-off region and
across gate oxide respectively at high gate and drain voltage.
• Carriers travelling along channel region acquire high kinetic energy and act as hot carriers.

• These hot carriers hit the Si atoms and generate the

electron-hole pair called impact ionization.
• Electrons gain sufficient kinetic energy so that it crosses the
barrier of channel and oxide interface and injected into the
gate oxide.
• Electrons which do not trapped in the oxide layer become
the gate current.
• These trapped electrons degrade some parameters of the
MOSFET such as threshold voltage (Vth) and
transconductance (gm).
Fig.: Hot Carrier Effects in short channel MOSFET

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Contd..
SCE: Surface Scattering/Mobility Degradation
• Minority carriers in the channel are strongly attracted towards the oxide layer by increasing the gate bias.
• They collides at the Si/SiO2 interface and makes the silicon surface rough due to incomplete bonds.
• Hence, carrier mobility is reduced at the surface when carriers move in the channel from source to drain. It is
known as surface scattering.

• Carrier mobility is also reduced due to fixed oxide

charge at the interface.
• In short channel MOSFET, expansion of source
and drain depletion region increases the vertical
electric field Ey.
• It degrades the carrier mobility.

Fig.: Surface Scattering

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Contd..6
SCE: Velocity Saturation
• Carrier mobility depends on drain voltage which
creates lateral electric field.

• The carrier velocity in the transistor increases

linearly up to maximum value where it becomes
constant till saturated field (Esat)

• It is known as Velocity Saturation.

v =  E at E  Esat (3) Fig. : Velocity saturation at room temperature

v = vs at E  Esat (4)

• Carrier mobility degrades early in short channel transistor due to velocity saturation at low voltage.

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Contd..
Thank You!