Syllabus for Semester III, B. Tech.
(Electronics and Communication Engineering)
Course Code: 24EE05TH0301 Course: Digital System Design with HDL
L: 3 Hrs, T: 0 Hr, P: 0 Hrs. Per week Total Credits: 03
Course outcomes
At the end of this course students will demonstrate the ability to:
1. Understand the fundamentals of Verilog.
2. Describe Test Bench for testing Verilog designs effectively.
3. Design Finite State Machines using Verilog.
4. Design combinational and sequential circuits using Verilog.
5. Implement digital functions using Programmable Logic Devices.
Unit I :
Introduction to Verilog, Fundamentals of Verilog including language basics andrelation to
circuit implementation, Modules and Ports in Verilog, Modeling techniques in Verilog, Verilog
constructs and codes, Synthesis and Simulation.
Unit II :
Combinational Circuits Design in Verilog: Comparators, Multiplexers and De-multiplexer,
Encoder, Decoder, Half and Full Adders, Subtractors, Serial and Parallel Adders, BCD Adder,
Barrel shifter and ALU.
Unit III –
Sequential Circuits Design in Verilog: Latches/buffers and Flip-Flops as memory storage
elements, Counters, Shift registers, Memory and its internal organization.
Unit IV –
FSM design, Task and Functions, User Defined Primitive, Timing and delays, Test bench,
Advanced concepts.
Unit V -
Concepts and Generic architecture of PAL, PLA, PLD and FPGA, Synthesis and Implementation
of Boolean functions using programmable logic devices.
Text Books:
1. Samir Palnitkar, “Verilog HDL: A Guide to Digital Design and Synthesis”, Prentice
Hall; 2nd edition (21 February 2003)
2. Stephen Brown and ZvonkoVranesic, “Fundamentals of Digital Logic with Verilog
Design” TataMcGrawHill, 3rd ed, 2009.
Reference Books:
1. W.H. Gothmann, “Digital Electronics- An introduction to theory and practice” ,
PHI, 2nd edition ,2006
2. M. Morris Mano and Michael Ciletti,“Digital Design: With an Introduction to
Verilog HDL”, 5e, 2011
3. D.V. Hall, “Digital Circuits and Systems”, Tata McGraw Hill, 1989
Syllabus for Semester III, B. Tech. (Electronics and Communication Engineering)
Course Code: 24EE05PR0301 Course: Digital System Design with HDL Lab
L: 0 Hrs, T: 0 Hr, P: 2 Hrs. Per week Total Credits: 01
Course outcomes
At the end of this course students will demonstrate the ability to:
1. Examine functionality of digital integrated circuits.
2. Apply simulation tools to test the functionality of logical circuits.
3. Write and debug Hardware Description Language programs.
4. Perform simulation & synthesis of combinational and sequential circuits using Verilog.
5. Implement digital circuits on FPGA.
Experiments based on following topics:
1. Combinational and sequential circuits.
2. Different techniques of modeling.
3. Verilog statements and test benches.
4. Design of arithmetic blocks in Verilog and implement the same.
