3 ALU, Data-path & Control Unit

Chapter 3
Introduction:
y A computer is used for the execution of the program, which consists of
a set of instructions stored in the memory.
y The actual work of executing the instructions of the program is done by
the processor(CPU).
y To process an instruction, CPU uses three internal components named
as:
1) Registers
2) ALU (arithmetic and logic unit)
3) Control unit (CU)

Arithmetic and logic unit

Registers
Status Flags
Internal CPU Bus

Shifter

Complementer

Arithmetic and Control

Boolean logic unit

Control
paths

Fig. 3.1 Internal Structure of CPU

1) Register:
y A register is a storage component present inside the CPU which is
used to accept, store and transfer the data and instructions used by
ALU, Data-path & Control Unit

the CPU.
y Registers are very fast computer memory units because they are
made up of a group of flip flops and gates.
y Flip Flops are used to store the binary information, and gates control
the transfer of information in and out of registers.
2) ALU (arithmetic and logic unit):
y The arithmetic and logical operations on data items inside the
computer are performed by ALU.

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y All the other components like control unit, registers, memory, and
I/O bring the data for processing into the ALU and then take the
result back out.
y Data to be processed is forwarded to registers and ALU, and the
result of ALU operation is stored in specified registers.
y Based on the computation result, the ALU can also set flags.
For example, if the result of an ALU operation which is to be stored in
a register exceeds the length of that register, then overflow is set to 1.
y The control unit sends the signals that control the operation of the ALU
and also controls the movement of the data into and out of the ALU.

Control unit Flags

ALU
Registers Registers

Fig. 3.2 ALU Inputs and Outputs

3) Control unit (CU):

y Control unit is that component of the processor that causes things
to happen, i.e. it directs the operation of the processor.
y Control unit converts the information that is being received into the
control signals and then transfers the control signals to the central
processor.
y This processor then tells the hardware what operations are to be
performed based on the control signals.
y Control unit consists of inputs such as instruction registers, flags
and control signals from external sources (e.g. interrupt signals).

Instruction Decoder

Control signals
within CPU

Flags Control signals from

C ontrol bus

Control control bus

ALU, Data-path & Control Unit

Unit

Clock
Control signals to
control bus

Fig. 3.3 Block Diagram of Control Unit

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Control unit functions:
y In order to exchange data between memory and I/O modules, control
signals are being issued by the control unit external to the processor.
y Control signals internal to the processor are being issued by the control
unit for ALU to perform the specified operation, move the data between
the registers and to regulate other internal operations.
y Control unit handles tasks such as fetching, decoding, executing and
storage of results of the micro-operations.
y It regulates that the data inside the processor will be executed in what
sequence and will be stored in which register, i.e. it directs the data
flow sequence inside the processor as well as outside the processor.
y The two basic tasks performed by the control unit are:
1) Sequencing: The control unit makes the processor move through a
series of micro-operations in the proper sequence based on which
the program is being executed.
2) Execution: The control unit is also responsible for each micro-
operation to be performed.

Micro-operations:
y Execution of a program comprises sequential execution of instructions.
y Execution of each instruction is done during an instruction cycle which is
made up of shorter sub cycles (e.g. fetch cycle, execute cycle, interrupt
cycle).
y Execution of each sub cycle consists of one or more shorter operations,
called micro-operations.
y Micro-operations are the functional or atomic operations of a processor
that finishes its execution in 1 clock cycle.

ALU, Data-path & Control Unit

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Program Execution

Instruction cycle Instruction cycle Instruction cycle

Indirect/ Interrupt
Fetch Execute
Direct

µ OP µ OP µ OP µ OP

Fig. 3.4 Constituent Elements of Execution of Program

Note:
Register to Register transfer operation is a µ-operation from the user's
point of view.

Example: Following is the micro-operation to move the content from one

register to another which will be completed in one clock cycle.

Mov r3, r4

Register : r3 r4
transfer language

r3 in
H/W Design : T3
ALU, Data-path & Control Unit

r4 out
T4

µ-operation list : T 1 : r4 o ut , r3 i n

Control signals

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Micro-instruction:

Note: Definitions
Micro-instruction designed with one micro-
Micro-instruction is a collection
operation or more than 1 µ-operation, will
of micro-operations.
always takes 1 cycle to complete.

Micro-program:
y Sequence of µ-instructions which are used to execute a task in the
hardware is known as µ-program.
Example: In order to execute an instruction, the instruction must be
brought to the processor from the memory. To complete this task following
micro-program is used:
t1: MAR ← (PC)
t2: MBR ← Memory
PC ← (PC) + step size
t3: IR ← (MBR)
The above micro-program consists of four micro-instructions, which takes
three clock cycles.

The fetch cycle:

y Every instruction is placed in the main memory.
y In order to execute an instruction, it must be brought into the CPU from
the main memory.
y Thus, the fetch cycle appears at the starting of every instruction cycle
and causes an instruction to be fetched from memory.
y Following are the sequence of events for the fetch cycle:
1) Program Counter(PC) consist of the address of the next instruction
which is to be executed, and this address is moved to the memory
address register (MAR).
ALU, Data-path & Control Unit

Fig. 3.5 Orientation of PC and MAR

2) Next step is to bring the instruction from the memory.

The MAR contains the instruction address, which is placed on the
address bus and control unit sends the READ command on the control

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bus, and the fetched instruction appears on the data bus, which is then
copied to memory buffer register (MBR)

Fig. 3.6 Orientation of MAR and MBR

Since read from memory and incrementing PC to the instruction size

does not affect each other, so in this step, PC (program counter) can
also be incremented.
3) Now, the data is placed from the MBR to IR.

Fig. 3.7 Orientation of MBR and IR

Thus, the fetch cycle has four micro operations, which can be completed
in three clock cycles where each micro operation involves movement of
data in and out of registers.

Hardware design:
PCout PC

MARin
MARout MAR

Address Control
bus bus
ALU, Data-path & Control Unit

Memory
Memory

Data bus

MBRin MBR
MBRout

IR in IR
Fig. 3.8 Hardware Design of IF Cycle

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IF µ-program:
t1: MAR ← (PC)
t2: MBR ← Memory
PC ← (PC) + I
t3: IR ← (MBR)

Where I is the instruction length and t1, t2, and t3 are the time units.
First time unit (t1): MARin, PCout
Second time unit (t2): MARout, Memory, MBRin
PCout, Increment, PCin
Third time unit (t3): MBRout, IRin

The operand fetch cycle:

y After the instruction is fetched, the source operands must also be
fetched.
y If the instruction specifies a direct/indirect address, then a direct/
indirect cycle must precede accordingly before the execute cycle.

a) Direct addressing mode:

Let us assume a one-address instruction format with direct addressing
mode.

Instruction:

Opcode Address

IR(Instruction Effective
Register) Address

y During the instruction fetch, the instruction is placed in the IR(Instruction

Register).
y The address field of the instruction is moved to the memory address
register (MAR).
ALU, Data-path & Control Unit

y Then, this address is used to fetch the operand from the memory that
is stored in the corresponding address.
y The operand which is fetched from memory is kept on the data bus and
is then placed in the memory buffer register (MBR).
y The memory buffer register (MBR) places the operand in the accumulator
register for further processing.

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Hardware design:

IRout IR[Address]

MARin
MARout MAR

Address Control
bus bus

Memory
Memory

Data bus

MBRin MBR
MBRout

IRin IR
Fig. 3.9 Hardware Design of Direct Operand Fetch Cycle

Micro-program of direct operand fetch cycle:

t1: MAR ← IR[Address]
t2: MBR ← M[MAR]
t3: AC ← MBR

b) Indirect addressing mode:

An example of a one-address instruction format that uses indirect addressing
mode is considered for the detailed analysis below.
Instruction:

opcode Address
ALU, Data-path & Control Unit

Instruction Address of effective

register address

y The address field of the instruction placed in the instruction register

(IR) is transferred to the memory address register (MAR).
y The operand's effective address is achieved by accessing the memory
address mentioned in the address field of the given instruction format.
y The effective address(EA) which is being fetched is placed in the
MBR and the address field of the instruction register is replaced by

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the effective address(EA), so now, instead of an indirect address, the
address field contains a direct address.
y Then again, the address field of IR is transferred to MAR, and this
address is used to fetch the operand from the corresponding memory
location.
y The fetched operand appears on the data bus and is then placed in
MBR.
y Then, from the memory buffer register (MBR), the operand is placed in
accumulator register(AC) for further processing / execution.

Hardware design:
IRout IR [Address]

MARin
MARout MAR

Address Control
lines lines

Memory Memory

Data lines

MBRin
MBRout MBR {Effective Address}

MARin
MARout MAR

Address Control
lines lines

Memory Memory

Data lines

MBRin
MBRout MBR {operand}

ACCin
Accumulator
ALU, Data-path & Control Unit

Fig. 3.10 Hardware Design of Indirect Operand Fetch Cycle

Microprogram of indirect operand fetch cycle:

t1: MAR ← (IR (address) )
t2: MBR ← Memory
t3: MAR ← MBR
t4: MBR ← Memory
t5: Accumulator ← MBR

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The execute cycle:

y The micro-operations in the execution cycle vary as they depend on the
type of the opcode.
y Consider the following MUL instruction using direct addressing mode:
MUL R1, A
y It multiplies the contents of location A to the contents of register R1
and store the result in R1.

The following sequence of micro-operations occur:

1) The instruction register (IR) contains the MUL instruction. The address
part of IR is loaded into the MAR.
2) Then, the memory location corresponding to the address in MAR is
read.
3) Then, the data present in location A is transferred to MBR (memory
buffer register).
4) The ALU then multiplies the contents of register R1 and MBR.

Hardware design:

IRout IR[Address]

MARin
MARout MAR RD

Address Control
bus bus

Memory
Memory

Data bus
ALU, Data-path & Control Unit

MBRin MBR
MBRout

ACin AC R1

ALU
Fig. 3.11 Hardware Design of Execute Cycle

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Micro-program:
t1: MAR ← (IR Address)
t2: MBR ← Memory
t3: Accumulator ← MBR
t4: R1 ← (R1) * (AC)

Write back micro-program:

y After the execution of the instruction, the result might be required to
be stored in memory location.

The following sequence of micro-operation occurs:

1) After the execution, the result is stored in the register (accumulator),
this result is transferred to the memory buffer register (MBR).
2) IR contains the instruction and the address field of the instruction,
which contains the address of the memory location where the result
needs to be stored is transferred to MAR.
3) The data present in MBR is stored in the memory location whose address
is present in MAR.

ACout Accumulator IRout IR[Address]

{Data} {Address}

MBRin MARin
MBR MAR WR
MBRout MARout

Data bus Address bus Control bus

Memory
Fig. 3.12 Hardware Design of Write Back ALU, Data-path & Control Unit

Micro program:
t1: MBR ← Accumulator
t2: MAR ← IR [Address]
t3: Memory ← MBR

The interrupt cycle:

y After the completion of execute cycle, it is checked whether any enabled
interrupts have occurred or not.

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Instruction Cycle
Instruction
Cycle

No
INT

Yes Interrupt
Cycle
Service the Interrupt

Fig. 3.13 Interrupt Servicing Mechanism

y If interrupts occur, the following sequence of micro-operations takes
place:
1) The next instruction address which is to be executed is present
inside the PC. When an interrupt occurs, the address present inside
the PC is sent to the memory buffer register(MBR) so that it can be
saved for return from the interrupt.
2) The memory address at which the contents of the PC are to be
stored is loaded in MAR.
3) The starting address of the interrupt processing routine is loaded on
the PC.
4) The last step is to load the contents of MBR, which contains the old
value of PC, into the memory whose address is present in the MAR.

Hardware design:
PCout PC SPout SP
{return address} {TOS address}

MBRin MARin
MBR MAR WR Routine
MBRout MARout addressout Routine address

Data bus Address bus Control bus

PCin PC
ALU, Data-path & Control Unit

Memory
Fig. 3.14 Hardware Design of Interrupt Cycle

Micro-program:
t1: MBR ← (PC)
t2: MAR ← Save-address
PC ← Routine address
t3: Memory ← (MBR)

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PRACTICE QUESTIONS

Q1 Consider a one-word long instruction:

MOV [2000], @3000
If the processor fetches, decodes, operand fetches, executes and writes
back the result of the instruction to the memory. Then the number of times
the memory is referred by the processor?

Sol: Fetch: 1 memory reference will be required for fetching the instruction.
Decode: Since the instruction is 1 word long, no memory reference is
required during decode.
Operand fetch: Since operand fetch, indirect addressing mode is used, so
two memory references will be required.
1 MR for getting the effective address, i.e. address of the operand.
1 MR for getting the operand.
Execute: No memory reference for execute cycle because given instruction is
MOV instruction only.
Write Back: One memory reference to write the operand at memory location
[2000]
Total memory references = 1 + 2 + 1 = 4

Q2 For the operand fetch using indirect addressing mode, how many number of
cycles are required to bring the operand to the CPU?

Sol: Ans. 4
The microprogram for operand fetch using indirect addressing mode is as
follows:
t1: MAR ← IR [Address]
t2: MBR ← Memory
ALU, Data-path & Control Unit

Thus, in these two cycles effective address, i.e., the address of the operand,
is brought to the CPU.
t3: MAR ← MBR
t4: MBR ← Memory
These two cycles are required to bring the operand from memory to the CPU.
So, total of 4 cycles is required.

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Q3 The fetch cycle consists of four micro-operations, and these four micro-op-
erations can be completed in three units of time__________.
Which among the four micro-operations can be completed in a single time
unit in the fetch cycle?
I) MAR ← (PC)
II) MBR ← Memory
III) IR ← (MBR)
IV) PC ← (PC) + Instruction size (I)
a) I and II can be completed in a single time unit.
b) II and IV can be completed in a single time unit.
c) III and IV can be completed in a single time unit.
d) I and IV can be completed in a single time unit.

Sol: Ans. b), c)

MBR ← Memory
PC ← (PC) + instruction size (I)
Both these micro-operations can be completed in a single cycle because
these two actions, read a word from memory and add instruction size (I) to
PC, do not interfere with each other.
IR ← (MBR)
PC ← (PC) + instruction size (I)
Both these micro-operations can be completed in a single cycle because
they both do not interfere with each other.
Conflicts occur when reading and writing are done on the same register in
single time unit.

Bus architecture:
y Two or more devices in a computer are connected through a common
ALU, Data-path & Control Unit

transmission medium known as a bus.

y There are many devices that are connected to the bus, and if any device
sends the signal, it can be received by all the other devices connected
to the bus.
y Signals that represent binary 1 and binary 0 are transmitted via bus,
which contains multiple communication lines.

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Previous Years’ Question

Consider the following sequence of micro-operations,  (GATE CS 2013)

MBR ← PC
MAR ← X
PC ← Y
Memory ← MBR
Which one of the following is a possible operation performed by this sequence?
a) Instruction fetch b) Operand fetch
c) Conditional branch d) Initiation of interrupt service
Sol: d)

System bus:
y The major units of a system, like memory, CPU and I/O are connected
by a system bus.
y Typically, the system bus contains the following lines:
a) Data lines: Data is transferred between various system modules
through data lines.
Data lines altogether are known as the data bus.
b) Address lines: The address of the data which is present on the data
bus is contained by address lines.
Address lines altogether are known as address bus.
c) Control lines: The control lines are bearers of control signals that
effectively establish the communication of control commands and
timing signals among different system components.
y The validity of address and data information is specified by timing
signals.
y Control signals describe the operation to be performed like memory
ALU, Data-path & Control Unit

write, memory read, I/O write, I/O read etc.

Note:

1) The word length of the CPU can be described based on the width of
the data bus.
2) The memory capacity of the system can be described based on the
width of the address bus and data bus.

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Bus architecture:

Bus Architecture

Single Bus Multi Bus

Architecture Architecture

Fig. 3.15 Bus Architecture

1) Single bus architecture:

y To form an operational system, the functional individual units must
be connected in some organized way.
y The single bus architecture is the easiest way to interconnect all the
functional units.

Input Output Memory Processor

System Bus

Fig. 3.16 Single-Bus Structure

y Both the instructions and data are transferred through this single bus.
Advantages:
y The single bus architecture is not an expensive design.
y Less number of registers are associated.
y Flexible for attaching new peripheral devices.
Disadvantages:
y Only single transmission can be done by the bus at a given point in
time, i.e. only two units can actively use the bus at any given time.
y Less concurrency in operations.
y Requires a greater number of cycles for execution, thus making execution
ALU, Data-path & Control Unit

of process slow.

Multi bus architecture:

y The performance of single bus architecture is affected if many devices
are connected to the bus.
y With the increase in the count of the components connected to the bus
architecture, propagation delay increases. Therefore, devices will take a
large amount of time to synchronize the use of the bus.

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y Also, when the aggregate data transfer demand becomes so large that it
reaches the capacity of the bus and thus bus may become a bottleneck.
y The above problems may not always be overcome by single bus architecture.
y This problem can be solved by using multiple buses, generally laid out
in a hierarchy.
y Multiple buses allow the devices to work simultaneously, thus improving
the CPU’s speed.

ALU, Data-path & Control Unit

Fig. 3.17 Three Bus Organisation of Data Path

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y Buses P and Q are used to transmit the source operands to the P and Q
inputs of ALU, where an arithmetic or logic operation can be performed.
y The result is transmitted to the destination over bus S.
y Whenever required, the ALU can forward one of its two input operands,
not modified, to bus S.
Advantages:
y The number of cycles required for the execution of the process is less.
y More concurrency in operations.
Disadvantage:
y Multibus architecture is an expensive design.

Control signals:
y Every micro-operation is performed by activating some control signals.
y Control signals are put in directly as binary inputs to the independent
logic gates.
y Control signals can be used to activate an ALU function, a data path or
other external interfaces.
y The CPU consists of some general purpose and some special purpose
registers.
y All the registers are connected to a common data path known as BUS.
y For transferring the information from one register to another, each
register has two control signals Rin and Rout.
y When the content of the bus is loaded into the register R, then Rin must
be set to 1.
y When the content from the register R is loaded into the bus, then Rout
must be set to 1.

y Let us consider Fetch Cycle:

Following is the micro-program for the fetch cycle:
t1: MAR ← (PC)
The control unit turns on the control signals that unlock the gates between
the PC and MAR permitting the bits in PC onto MAR.
t2: MBR ← Memory
ALU, Data-path & Control Unit

PC ← (PC) + 1

For this micro-operation control unit activates the following control signals:
1) A control signal that unlocks the gates and permits the contents present
in MAR onto the address bus.
2) A control signal to read the memory location and transfer the data onto
the data bus.

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3) A control signal that unlocks the gates and permits the contents on the
data bus to be transferred onto the MBR.
4) A control signal that increments the PC value by the instruction length
and stores it on PC.
t3: IR ← (MBR)
A control signal that allows the contents of MBR to be transferred to IR.

PCout
I1 IF PC→MAR
I2 ID Mem→MDR MARin
.
OF PC+1→PC
.
PD MDR→IR
.
In WB

Fig. 3.18 Fetch Cycle

y These control signals can be activated by:

a) Hardwired control unit design
b) Micro-programmed control unit design.

Control unit design:

y The implementation of the control unit requires the following information:
1) Number of instructions implemented in base hardware.
2) Number of micro-operations required for each instruction.
3) The control signals which are required for micro-operation.
y The control unit in the CPU is responsible for decoding the instructions
and generating the control signals corresponding to the sequence of
micro-instructions involved in the instruction.
y There are two approaches to implement control unit:
1) Hardwired control unit
2) Micro-programmed control unit

1) Hardwired control unit:

y The hardwired control unit is a sequential state machine to generate
the specific fixed sequences of control signals.
ALU, Data-path & Control Unit

y In this design, control signals are expressed in the sum of product

expression format.
y Gates ,decoders, flip flops and other digital circuits are used to
implement control logic.
y To generate the control signals, fixed logic circuits that directly
correspond to Boolean expressions are used.
Advantages:
y Since logic gates and flip flops are used to design control units, so it is
the fastest control unit.

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Disadvantage:
y It is not flexible because even very small changes in the Boolean
expression requires redesign and reconnection of a logic circuit.

Fig. 3.19 Control Unit Organisation

y The blocks of decoder and encoder are combinational circuits that are
used to produce the desired control outputs.
y In control sequence, a different signal line for every step is provided by
the step decoder.
y While loading any instruction in IR (Instruction Register), one of the
output lines INS1 through INSk are set to 1, and all other lines are set to 0.
ALU, Data-path & Control Unit

y The input signals to the encoder block are combined to generate the
individual control signals Yin, PCout, Add, End etc.
eg. Zin = T1 + T6 ⋅ ADD + T4 ⋅ BR + .......
y The signal is asserted during time slot T1 for all instructions, during T6
for an ADD instruction during T4 for an unconditional branch instruction
and so on.

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Branch ADD
T4 T6

T1

Zin

Fig. 3.20 Generation of Zin Control Signal

Note:

Hardwired control unit is used in designing RISC architecture.

PRACTICE QUESTIONS

Q4 Consider a system in which we have 4 control signals S0, S1, S2, S3 and 3 dif-
ferent instruction I1, I2, I3 and 4 µ-operations T1, T2, T3, T4. Following are the
control signals which are required for a particular instruction at different
µ-operation timings:

µ-operation/Instruction I1 I2 I3

T1 S0 S2, S3 S0, S1, S2, S3

T2 S0, S2 S3 S1, S3

T3 S3, S2, S0 S0, S3 S1

ALU, Data-path & Control Unit

T4 S0, S1, S2 S3, S2, S1 S2

The expressions for the control signals will be?

Sol: The expression for control signal S0 will be,

S0 = T1 (I1 + I3 ) + T2 (I1 ) + T3 (I1 + I2 ) + T4 (I1 )

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The expression for control signal S1 will be,

S1 = T1 (I3 ) + T2 (I3 ) + T3 (I3 ) + T4 (I1 + I2 )
The expression for control signal S2 will be,
S2 = T1 (I2 + I3 ) + T2 (I1 ) + T3 (I1 ) + T4 (I1 + I2 + I3 )
The expression for control signal S3 will be:
S3 = T1 (I2 + I3 ) + T2 (I2 + I3 ) + T3 (I1 + I2 ) + T4 (I2 )

Q5 Following is the expression for control signal Z, present in a hardware:

Z = T1(I1 + I4) + T2 + T3 + T4 (I1 + I2 + I3 + I4)
Given that the system has 5 different instructions I1, I2, I3, I4, I5 and each
instruction has 4 micro-operations T1, T2, T3, T4. During the execution of
instruction I5, in which micro-operation of the control signal is enabled in the
hardware?
a) T1 and T2 b) T2 and T3
c) T1, T2, T3 and T4 d) None Sol.

Sol: Z = T1(I1 + I4) + T 2 + T3 + T4 (I1 + I2 + I3 + I4 )

I1 I1 I1 I1
I4 I2 I2 I2
I3 I3 I3
I4 I4 I4
I5 I5

So, option ‘b’ is correct.

ALU, Data-path & Control Unit

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Previous Years’ Question

A hardwired CPU uses 10 control signals S1 to S10, in various time steps T1 to T5, to
implement 4 instructions I1 to I4 as shown below: (GATE CS 2005)

T1 T2 T3 T4 T5

I1 S1, S3, S5 S2, S4, S6 S1, S7 S10 S3, S8

I2 S1, S3, S5 S8, S9, S10 S5, S6, S7 S6 S10

I3 S1, S3, S5 S7, S8, S10 S2, S6, S9 S10 S1, S3

I4 S1, S3, S5 S2, S6, S7 S5, S10 S6, S9 S10

Which of the following pairs of expressions represent the circuit for generating control
signals S5 and S10, respectively?
((Ij + Ik)Tn indicates that the control signal should be generated in time step Tn if the
instruction being executed is Ij or Ik).
a) S5 = T1 + I2 ⋅ T3 and
S10 = (I1 + I3 ) ⋅ T4 + (I2 + I4 ) ⋅ T5
b) S5 = T1 + (I2 + I4 ) ⋅ T3 and
S10 = (I1 + I3 ) ⋅ T4 + (I2 + I4 ) ⋅ T5
c) S5 = T1 + (I2 + I4 )T3 and
S10 = (I2 + I3 + I4 ) ⋅ T2 + (I1 + I3 ) ⋅ T4 + (I2 + I4 ) ⋅ T5
d) S5 = T1 + (I2 + I4 ) ⋅ T3 and
S10 = (I2 + I3 ) ⋅ T2 + I4 ⋅ T3 + (I1 + I3 ) ⋅ T4 + (I2 + I4 ) ⋅ T5
Sol: d)
ALU, Data-path & Control Unit

Micro-programmed control unit:

y Control Memory is a permanent memory, i.e ROM.
y In this design, micro-programs are used to program the control memory.
y The behaviour of the control unit is depicted by the program present in
the control memory.
y Thus, by simply executing that program, the control unit can be
implemented.
y The set of micro-instructions is stored in the control memory.

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Fig. 3.21 Functioning of Microprogrammed Control Unit

y The address of the next micro instruction to be read is present inside

the control address register (CAR).
y After reading micro instruction from the control memory, the micro
instruction is transmitted to the buffer register known as a control data
ALU, Data-path & Control Unit

register(CDR).
y The sequencing unit loads the control address register and issues a
read command.
y Following are the functions of the control unit:
1) The READ command to the control memory is being issued by the
sequencing logic in order to execute an instruction.
2) The word whose address is given in the control register is read into
the control buffer register.

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3) Control signals and next address information are generated by the
content of the control buffer register.
4) Based on the next address information present inside the CDR and
ALU flags, a new address is being loaded by the sequencing the logic
unit in the CAR.
y The upper decoder converts the opcode of IR into the control memory
address.
y The lower decoder is not used for horizontal micro instructions, but for
vertical micro-instructions.
y Control Memory is associated with CAR (Control Memory address register)
and CDR (Control Memory data register) registers which are used to hold
the control memory address and control memory content, respectively.

Hardware design:
PC {Instruction Address}

MAR {Memory Address Register}

Memory

MBR

IR {opcode}

Decoder

µ Sequence {µ-Instruction
unit address}

CAR
µ Programmed
CU
ROM {Control Memory}

CDR {µ-Instruction}
ALU, Data-path & Control Unit

Base H/w

Fig. 3.22 Hardware Design implementing Microprogrammed Control Unit

Advantages:
y The use of micro-programming for implementing the control unit
simplifies the design of control unit.

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y It's implementation is cheaper and is less error-prone.

Disadvantages:
y Micro-programmed control unit is slower than hard-wired control unit
of comparable technology.

Note:
The Micro–programmed control unit is used for designing CISC architectures.

Instruction format:
The µ-Instruction in control memory is stored in the following format:
Control Word

Branch Condition Flag Control Field Control Memory

Address

Branch logic Flag Information Control Next micro-instruction

Signals address

log2 log2
(no. of Branch (no. of flags) log2 (Cache size)
Conditions)

Decoded Encoded
Binary Format Binary Format

Horizontal Vertical

n bits for n log2 n bits for

control signals ‘n’ control signals

Fig. 3.23 Control Word Design

Note:

Fields (branch condition, flag, control memory address) are used for
ALU, Data-path & Control Unit

jumping conditions.
Example: JNZ4004
In this we require three things
1) Condition: Jump if non zero
2) Flag: Zero flag
3) Address: 4004

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Micro-instruction sequencing:
The micro-programmed control unit carries out the two important
operations listed below as:
1) Microinstruction sequencing: It fetches the subsequent micro-
instruction from the control memory.
2) Microinstruction execution: It is the procedure of generating the control
signals to carry out the execution of the pre-fetched micro-instruction.

Example: Consider the following micro instruction with “Nonzero” branch

logic and having target address of 4000.
B.C. Flag C.F. CMA
10 01 PCout , MARin 4000

NZ zero flag

Where {PCout, MARin} are control signals.

Sol: This micro instruction will be executed as follows:
1) Micro instruction sequencing:
Fetch the µ-instruction from the ROM
2) Micro-instruction execution:

10 01 PCout , MARin 4000

NZ zero flag
Hardware
=

True False
µ-sequencer unit No change in the
is loaded with target address µ-sequencer unit
4000

Base
µ-sequencer unit CAR ROM CDR
ALU, Data-path & Control Unit

H/w

µ-Programmed CU

Fig. 3.24 Execution of Micro-Instruction

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PRACTICE QUESTIONS

Q6 Vertical micro-programming, horizontal micro-programming and hardwired

control are used for control unit design. Which among them has the highest
and lowest operational speed, respectively?
a) Highest: Hardwired control
b) Highest: Vertical micro-programming
c) Lowest: Vertical micro-programming
d) Lowest: Horizontal micro-programming

Sol: a), c)
Highest: hardwired control
lowest: vertical micro-programming.
y In hardwired, the control logic is implemented using gates and flipflops.
So, it is the fastest.
y In horizontal microprogramming, for each control signal, a separate bit
is used.
y In vertical microprogramming, control signals are expressed in the form
of encoded binary format.
Thus, a decoder is used.
So, for ‘n’ control signals, log2n bits are used, so it has the slowest
operational speed.

Q7 Consider a control memory unit in which a 22-bit micro-instruction is

stored.
The micro-instruction has three fields, the “next address” field of size ‘X’
bits, the “branch condition” field of 8 bits and the hardware containing 16
flags.
Then what is the size of the control memory?
ALU, Data-path & Control Unit

Sol: Ans. 2816 bytes

µ-Instruction format:
22 bit

Branch Condition Flag Next Address

8 X

16 flags
log2 (16) = 4 bits

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Number of bits for next address field (X)
= 22 – (8 + 4)
= 10 bits
Size of control Memory = 210 * 22 bits = (210) * 22/8 = 2816 bytes.

Horizontal micro-programmed control unit:

y Control signals in horizontal micro programmed control units are
expressed in the decoded binary format.
y In this control unit design, each control signal is associated with 1 bit.
y Hence, 'n' number of control signals will require decoding of 'n' bits.

Control field

n-bits

Sn ... S2 S1 S0

Fig. 3.25 Hardware Design of Microprogrammed Control Unit

y This micro-programmed control unit is fast, as all the control signals

are enabled altogether.

Vertical micro-programmed control unit:

y Control signals in vertical micro programmed control units are expressed
in encoded binary format.
y Hence, 'n' number of control signals will require encoding of 'log2n' bits.

Control field

log2n bits

ALU, Data-path & Control Unit

Decoder

Sn ... S2 S1 S0

Fig. 3.26 Hardware Design of Vertical Microprogrammed Control Unit

y This micro-programmed control unit is slow since any one control signal
can be enabled altogether.

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Micro-instruction design using horizontal micro-programming:

y If for instruction ‘I’, T is one of the micro instructions having 4 control
signals (S0, S1, S2, S3).
y Suppose the following control signals are enabled.
T: {S0, S1, S3}

µ-instruction design:
S3S2SS
1 0

- - 1011 -
⇒
ROM
Fig. 3.27 Microinstruction Design Example

Execution:
y Fetch T from the control memory (ROM)

- - 1011 -

S3S2S1S0
Hardware

Fig. 3.28 Hardware Execution

Since no branch condition is given, so,

µ-sequencer unit → CAR (control address register)

Micro-instruction design using vertical microprogramming:

y If for instruction I, T is one of the micro-instruction having 4 control
signals (S0, S1, S2, S3).
y If the following control signals are enabled
T {S0, S1, S3}
ALU, Data-path & Control Unit

y µ-Instruction format:

- - 00 01 11 -
⇒

ROM

Fig. 3.29 Vertical Microinstruction Design Example

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Execution:

- - 00 01 11 -

Select MUX
logic

11, 01, 00

Decoder

S3 S2 S1 S0

Fig. 3.30 Hardware Execution

Note:

1) Control field in the horizontal micro programming control unit is fixed.

2) Control field in the vertical micro programming control unit is variable,
i.e. it depends on the number of function code.

Horizontal micro-programming Vertical micro-programming

1) In horizontal micro- 1) In vertical micro-programming,

programming, the control the control signals are
signals are expressed in expressed in encoded binary
decoded binary format. format.

2) High degree of parallelism is 2) It allows a low degree of

allowed, as in this none or parallelism, as in this control
ALU, Data-path & Control Unit

more than one signal can be unit none or only one signal
enabled at any instance of can be enabled at any instance
time. of time.

3) It is faster as each control 3) It is slower as ‘n’ control

signal is denoted by a bit. So, signals require log2n bits. So, a
an external decoder is not external decoder is required to
needed. generate control signals.

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Horizontal micro-programming Vertical micro-programming

4) It is less flexible 4) It is more flexible.

5) The control unit, using 5) The control unit, using

horizontal micro- vertical micro-programming
programming is very complex is comparatively easy and
and expensive to design. cheaper to design.

6) It supports longer control 6) It supports shorter control

word. word.
Table 3.1 Comparison between Horizontal and Vertical Microprogramming

PRACTICE QUESTIONS

Q8 Consider a hypothetical control unit, which has a total of 233 control signals.
How many bits are required in control memory word for horizontal mi-
cro-programming and vertical microprogramming, respectively?
a) 233, 233 b) 233, 1 c) 8, 8 d) 233, 8

Sol: Ans. d)
Horizontal micro-programming:
In horizontal micro-programming, for each control signal one bit is used.

233 Control signals

233 bits

Vertical micro-programming:
In vertical micro-programming, for n control signals, log2n control bits are
ALU, Data-path & Control Unit

required because in this design, control signals are expressed in an encoded

binary format.

233 Control signals

log2 233 bits

Therefore, log2 233 = 8 bits are required.

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Q9 Consider a micro-programmed control unit design which supports 7 groups
of mutually exclusive control signals.

Groups Gr1 Gr2 Gr3 Gr4 Gr5 Gr6 Gr7

Control signals 2 10 4 1 18 23 6

How many more control bits are required using horizontal micro-program-
ming over vertical micro-programming?

Sol: Ans. 43
For vertical micro programming:
Micro-Instruction format:

- - Gr1 Gr2 Gr3 Gr4 Gr5 Gr6 Gr7 -

log2 2 log2 10 log2 4 log2 1 log2 18 log2 23 log2 6

Total control bits required = 1 + 4 + 2 + 1 + 5 + 5 + 3.

= 21 bits
[For horizontal micro-programming]
Micro instruction format:

- - Gr1 Gr2 Gr3 Gr4 Gr5 Gr6 Gr7 -

2 10 4 1 18 23 6

Total bits required = 2 + 10 + 4 +1 + 18 + 23 + 6

= 64 bits
So, horizontal micro programming requires 64-21 = 43, more bits.

Previous Years’ Question ALU, Data-path & Control Unit

Consider a CPU where all the instructions require 7 clock cycles to complete execution.
There are 140 instructions in the instruction set. It is found that 125 control signals
are needed to be generated by the control unit. While designing the horizontal micro-
programmed control unit, a single address field format is used for branch control logic.
What is the minimum size of the control word and control address register?
a) 125, 7 b) 125, 10 c) 135, 9 d) 135, 10
Sol: d) (GATE CS 2008 (IT))

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Q10 Consider a hypothetical control unit, which supports 512 bytes of the con-
trol word memory. If the control word is 20 bits long and hardware contains
4 flags and supports 16 branch conditions. What is the maximum number of
control signals that can be generated at a time using horizontal micro-pro-
gramming and vertical micro-programming, respectively?
a) 1, 1 b) 32, 32 c) 32, 1 d) 1, 32

Sol: Ans. c)
µ-instruction design:
20 bits
Branch Control Memory
Flag Control field
Condition Address

4 bits 2 bits 9 bits

Control word memory = 512 bytes

So, control memory address field requires = 9 bits
Number of flags = 4
So, number of flag bits required = 2
Number of branch conditions = 16
So, number of branch condition bits required = 4
Number of bits required for control field = 20 – (4 + 2 + 9) = 5
Therefore, the number of control signals that can be generated = 25 = 32
In horizontal micro-programming, for each control signal, 1 bit is there,
So, all control signals can be activated at a time.
∴ Maximum degree of parallelism for horizontal microprogramming = 32
In vertical micro programming only 1 control signal can be activated at a time.
∴ Maximum degree of parallelism for vertical micro-programming = 1
∴ Option c) is correct.
ALU, Data-path & Control Unit

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Chapter summary

� Introduction: To process the instructions, the CPU uses three components:

� Registers
� ALU (arithmetic and logic unit)
� Control unit (CU)
y Control unit functions: Two basic tasks performed by the control unit are:
� Sequencing
� Execution
y Micro-operations: Micro-operations are functional or atomic operations of a
processor that completes its execution in 1 cycle.
y Micro-program: Sequence of micro-instructions used to execute a task.
It includes the following cycles:
1) Fetch cycle
� Instruction Fetch
� Operand fetch
2) Execute cycle
3) Write back
4) Interrupt cycle
y Bus architecture: To form an operational system, functional individual units
must be converted in some organized way:
1) Single bus architecture
2) Multi bus architecture
y Control unit Design
1) Hard wired control unit
2) Micro programmed control unit
y Hard wired control unit: Control logic is implemented with logic gates, flip-
flops and other digital circuits
y Micro-programmed control unit: In this micro-program is used to program
control memory.
1) Horizontal micro-programmed control unit.
2) Vertical micro-programmed control unit.
ALU, Data-path & Control Unit

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