A Dual-Boost Converter with Zero Voltage

Transition

Yao C. Hsieh*, Te C. Hsueh* and Hau C. Yen**

*
Department of Electrical Engineering, National Dong Hwa University, Hualien, Taiwan
**
Department of Electrical Engineering, Fortune Institute of Technology, Kaohsiung County, Taiwan

Abstract-This paper proposes a novel soft-switching topology is complicated and not easy to analyze.
dual-boost converter which is composed of two shunted Auxiliary active snubbers are also developed to reduce
elementary boost converters and an auxiliary inductor.
switching losses [8]. These snubbers have additional
This converter is able to turn on both the active power
switches at zero voltages to reduce their switching losses circuits to gate the auxiliary switch and synchronize with
and evidently raise the conversion efficiency. Since the two main switch and, besides, the switching loss on the
parallel-operated elementary boost converters are identical, auxiliary switch should be carefully restrained.
operation analysis and design for the converter module
becomes quite simple. A laboratorial test circuit is built and Converters with interleaved operation are fascinating
the circuit operation shows satisfactory agreement to the techniques nowadays. Interleaved boost converter is
theoretical analysis. The experimental results show that this applied as PFC front end [9,10]. Interleaved converter
converter module performs very well with the output
with coupled-winding are proposed to provide lossless
efficiency as high as 95%.
clamp [11,12]. Additional active switches are also
appended to provide soft switching characteristics [13].
These converters are able to provide higher output power
I. INTRODUCTION and lower output ripple.
Boost converters are popularly employed on
equipments for different applications. For high power This paper proposes a soft-switching dual-boost
factor requirements, boost converters are the most converter with the interleaved feature, which is
popular candidates, especially for applications with dc composed of two shunted elementary boost converters
bus voltage well higher than line input. Boost converters and an auxiliary inductor. This converter module is able
are usually applied as pre-regulators or even are to turn on both the active power switches at zero voltages
integrated with the latter-stage circuits or rectifiers into to reduce their switching losses and evidently raise the
single-stage circuits [1,2]. Most renewable power conversion efficiency. Since the two parallel-operated
sources have quite low voltage output, such as boost converters are identical, operation analysis and
photovoltaic power systems and fuel cells, and claim for design for the converter module becomes quite simple. In
series-connection or voltage booster to provide enough laboratory, a test circuit is built to provide 500W power
voltage output [3,4]. output. The experimental results show that this converter
module performs very well with the output efficiency as
Several soft-switching techniques, gaining the features high as 95%.
of zero-voltage switching (ZVS) or zero-current
switching (ZCS) for DC/DC converters, have been II. CIRCUIT CONFIGURATION
proposed to substantially reduce switching losses and, Figure. 1 shows the proposed soft-switching converter
hence, attain high efficiency at increased frequencies. module. Inductor L1, MOSFET active switch S1 and
There are many resonant or quasi-resonant converters diode D1, comprise one step-up conversion unit; while
with the advantages of ZVS or ZCS presented before the components with subscript “2” form the other. DSx
[5,6]. The main problem of these kinds of converters is and CSx are the intrinsic anti-parallel diode and output
that the voltage stresses on the power switches are too capacitance of MOSFET Sx. The voltage source Vin, via
high in the resonant converters, especially for the the two paralleled converters, replenishes output
high-input DC voltage applications. Passive snubbers capacitor Co and the load. Inductor Ls is shunted with the
achieving ZVS are attractive [7], since no extra active two active MOSFET switches to release the electric
switches are needed and therefore featuring simpler charge stored within the output capacitor CSx prior to the
control scheme and lower cost. However, the circuit turn-on of Sx to fulfill zero voltage turn on (ZVS), and

978-1-4244-1668-4/08/$25.00 ©2008 IEEE 692

 L1 D1 to Vo at t0. At the beginning of this mode, current flowing
through S2 completely commutates to D2 to supply the
L2 D2 load. Current iS1 returns from negative value to zero, IL1
flows through Ls. Due to the zero voltage on vDS1, the
Ls voltage across inductor LS is Vo. That is, iLs will decrease
Co RL Vo
linearly at the rate Vo/Ls. In the meanwhile, the current
Vin flowing through S1 ramps up linearly. As iLs drops to zero,
current iS1 contains only IL1, while iD2 equals to IL2.
S1 S2
DS1 CS1 DS2 CS2 Current iLs will reverse its direction and flow through S1
together will IL1. As iLs increases in negative direction,
iD2 consistently reduces to zero. At this instant, iLs equals
Figure 1. Proposed dual-boost converter to -iL2, diode D2 turns off, and ends this mode up.
therefore, raises the converter efficiency. To simplify the Current iLs, iS1 and iD2 can be depicted as the following
analysis, L1, L1, and Co are replaced by current and equations.
voltage sources respectively as in Figure. 2.
Vo
III. CIRCUIT OPERATION ANALYSIS iLs (t ) IL - t (1)
LS
Before analysis on the circuit, the following
assumptions are presumed. Vo
iS1 (t ) t (2)
LS
1. The output capacitor Co is large enough, to
reasonably neglect the output voltage ripple. Vo
iD2 (t ) 2I L - t (3)
2. The forward voltage drops on MOSFET S1, S2 and LS
diodes D1, D2 are neglected.

3. Inductors L1 and L2 have large inductance, and the B. Mode II {t1 < t < t2, referring to Figure. 3(b)}
inductor currents are constants and are the same.
That is, IL1 = IL2 = IL. Whereas diode D2 stops conducting, capacitor CS2 is
not clamped to Vo anymore. The current through LS, iLS,
4. Output capacitances of switches, CS1 and CS2 have continues increasing and commences to discharge CS2.
the same value, that is, CS1 = CS2 = CS. This mode will terminate as voltage on switch S2, vDS2,
drops to zero. Voltage vDS2 and current iLs can be equated
The two active switches, S1 and S2, are operated with
as:
pulse-width-modulation (PWM) control signals. They
are gated with identical frequencies and duty ratios. The
v DS2 ( t ) Vo cos( Zt ) (4)
rising edges of the two gating signals are separated apart
for half a switching cycle. The operation of the converter iLs ( t ) -VoZC S sin( Zt ) - I L (5)
can be divided into eight modes, the equivalent circuits
and the theoretical waveforms are illustrated in Figures. 1
3 and 4. where Z
LS C S

A. Mode I {t0 < t < t1, referring to Figure. 3(a)}

Prior to this mode, the gating signal for switch S2 has C. Mode III {t2 < t < t3, referring to Figure. 3(c)}
already transited to low state, and the voltage VDS2 rises
At t = t2, voltage vDS2 decreases to zero. After this
IL1 iD1 D1 instant, DS2, anti-parallel diode of S2, begins to conduct
current. The negative directional inductor current iLs
iD2 D2 freewheels through S1 and DS2, and holds at a magnitude,
IL2
which equals to iLs(t2), a little higher than IL. During this
Ls iLs mode, the voltage on switch S2 is clamped to zero, and it
is adequate to gate S2 at zero voltage turn on.
Vo

S1 S2 D. Mode IV {t3 < t < t4, referring to Figure. 3(d)}

DS1 CS1 vDS1 DS2 CS2 vDS2
The switch S1 turns off at t = t3. Current iLs begins to
charge the capacitor CS1. The charging current includes
Figure 2. Simplified circuit diagram

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IL1 and iLs. Since the capacitor CS1 retrieves the electric vGS1
current imposed on iLs by discharging CS2, iLs decreases a
little and resonates toward -IL2. The voltage on switch S1 Deff
v GS2
and current through LS can be depicted as:

iLs (t2 ) v DS1

vDS1 (t )  sin(Zt ) (6)
ZCS
v DS2
iLs (t ) iLs (t 2 )cos(Zt ) (7)
i S1
I L1 iD1 D1
i S2
I L2 iD2 D2
Ls iLs i D1

Vo
i D2
S1 S2
DS1 CS1 vDS1 DS2 CS2 vDS2
i Ls I L1

(a)
- I L2
I L1 iD1 D1
t0 t1 t2 t3 t4 t 5 t6 t7 t8 Time
I L2 iD2 D2
Figure 4. Theoretical waveforms
Ls iLs
While the capacitor voltage vCS1 ramps to Vo, D1 will
Vo be forward biased and ends this mode.
S1 S2
DS1 CS1 vDS1 DS2 CS2 vDS2 Mode I to Mode IV describe the scenario of switch S2
between off state proceeding to ZVS turn-on. Operations
from Mode V to Mode VIII are the counterparts for
(b) switch S1. Due to the similarity, they are omitted here.
I L1 iD1 D1 IV. CIRCUIT DESIGN

iD2 D2 The proposed circuit is focused on higher power

I L2
demand applications. The inductors L1 and L2 are likely
Ls iLs to operate under continuous conduction mode (CCM);
therefore, the peak inductor current can be alleviated,
Vo along with less conduction losses on active switches.
S2 Under CCM operation, the inductances of L1 and L2 are
S1 DS1 CS1 vDS1 DS2 CS2 vDS2 only related to the current ripple specification. What
dominates the output power range and ZVS operation is
the inductance of LS.
(c)

iD1 D1 As the description in Mode II, prior to the turn-on of

I L1
switch S2, iLs will discharge CS2, the output capacitor of
iD2 D2 switch S2; and therefore surpasses IL2. In order to turn on
I L2
S2 at ZVS condition, switch S1 has to keep conduct
Ls iLs current to allow iLs to flow through anti-parallel diode
DS2. While DS2 clamps the switch voltage at zero, the
Vo gating signal vGS2 can comfortably impose on S2. This
S2 means vGS2 should shift to high state before vGS1 goes low.
S1 DS1 CS1 vDS1 DS2 CS2 vDS2 Therefore, for ZVS and symmetrical operations of both
switches, the duty ratios of both switches should be
greater than 0.5.
(d)
Figure 3. Circuit topologies under different operation modes As for the design of LS, it can be noticed that, current

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iLs will drop from IL1 down to -IL2 approximately during Since the load and output capacitor receive the current
Mode I and II. The current swing span should be a little summation from diodes D1 and D2, the frequency of the
more than 2IL to discharge CS2; and therefore, reduces output ripple current becomes twice as high as the
vDS2 to zero before turn on S2. Consequently, equation (8) switching frequency. Therefore, the output ripple voltage
can be formulated to estimate the current variation ratio: can be reduced. The output ripple voltage 'Vo can be
estimated by evaluating the joint contributions from the
Vo 2I L I in capacitance and the equivalent series resistance (ESR).
(8)
LS (1 - Deff )Ts (1 - Deff )Ts 2 2
I o Deff TS Vo Deff TS
where Ts is the switching period, Iin is input current, 'VC (15)
2Co 2RC o
Deff is effective duty ratio of both switches, which is
longer than the actual duty ratio. 'VESR I in u ESR (16)
Observing, for example, the voltage across inductor L2
holds at Vin for duration of DeffTs (i.e. Mode III to Mode 'Vo # 'VC 2  'VESR 2 (17)
VII); its value is (Vin – Vo) for (1-Deff)Ts (i.e. Mode VIII
and I). Applying voltage-second balance principle on V. EXPERIMENTAL RESULTS
inductor L2, we can obtain that,
An experimental circuit is built to verify the feasibility
1 of this circuit topology. The circuit parameters are listed
Vo Vin (9) in Table I.
1 - Deff
Assuming that the converter efficiency is K, the input TABLE I.. CIRCUIT PARAMETERS
and load current are related as the following: Parameter Value
Inductors L1 and L2 165mH
Io K (1 - Deff )I in (10) Inductor Ls 270PH
Therefore, Capacitor Co 330PF
Switching frequency fs 100kHz
KVoTs (1 - Deff )2 Input voltage Vin 120V
LS (11) Output voltage Vo 300V
Io
Output power Po 500W
Combining eqs. (9) and (11), we can rewrite the
relationship between input voltage Vin and output voltage Figures 5, 6, and 7 illustrate the experimental
Vo into: waveforms. Figure. 5 shows vGS and vDS of each switch.
The gating signal is imposed on the switch after its
Ts 2 RTs voltage falls down to zero. Figure. 6 depicts relationships
Vo Vin Vin (12) between current iL1, iS1, and iLs, where the ripple current
I o Ls Ls
of iL1 is not significant. Current iLs together with iL1 flow
For normal operations of a converter, the output through switch S1 during its turn-on period. Figure. 7
voltage Vo is expected to be a constant. Therefore, for a demonstrates the commutation between switch and diode
fixed Ls value, switching period Ts should be modulated current.
to cope with the variations of load current Io or input
voltage Vin. This indicates that this converter will be vGS1
v GS2
operated under adaptable frequency to provide constant
vDS1
output voltage.
v DS2
Similarly, the input current Iin with respect to output
current Io can be depicted as: (vGS1, vGS2: 20V/div vDS1, vDS1: 500V/div time: 2Ps/div)
Figure 5. Voltages vGS and vDS of each switch

1 Vo I oTs
I in (13) vDS1
K Ls
i S1
And the output power Po is: i L1
i Ls
Ts 2 L
Po Vin K s I in 2
2
(14) (voltage: 500V/div current: 2A/div time: 2Ps/div)
Ls TS Figure 6. Current relationships between iL1, iS1, and iLs

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 vDS2
96

i S2
94
iD1
iD2
92

(voltage: 500V/div current: 5A/div time: 2Ps/div)

Figure 7. Current commutation between iS2 and iD2 90

200 250 300 350 400 450 500 550

Figure. 8 illustrate the output ripple voltage 'vo and
diode currents iD1, iD2. The result manifests the ripple Figure 10. Efficiency variation at different output power
voltage ratio 'Vo/Vo is less than 0.7%. The control unit
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