ISSN (Print) : 0974-6846

Indian Journal of Science and Technology, Vol 10(13), DOI: 10.17485/ijst/2017/v10i13/87202, April 2017 ISSN (Online) : 0974-5645

Tunnel Field Effect Transistors for Digital and Analog

Applications: A Review
S. Poorvasha*, M. Pown and B. Lakshmi
School of Electronics Engineering, VIT University, Chennai – 600127, Tamil Nadu, India; [email protected],
[email protected], [email protected]

Abstract
Objectives: This paper presents the review of Tunnel FET (TFET) to overcome the major challenges faced by the
­conventional MOSFET. Analysis: Various device structures and characteristics of TFET along with different material and
doping to improve efficiency are discussed in detail. In recent years, TFET seems to be an attractive device for analog/
mixed-signal applications due to their advantages such as high ON current (ION), low leakage current (IOFF), reduced values
of threshold voltage (VT) and low Subthreshold Swing (SS).

Keywords: Asymmetric Gate Oxide, Band-to-Band Tunneling, Double Gate, Gate on Drain Overlap, Subthreshold Swing,
Tunnel FET

1. Introduction 2. Characteristics of TFET

As MOSFET’s size scales down, the low power dissipation Figures 1 (a) and (b) illustrate the general schematic of
in the circuit is maintained by reduced supply voltage. The TFET and its energy band diagram. TFET comprises p+
electrical parameters such as Subthreshold Swing (SS) source, intrinsic channel and n+ drain. During the OFF-
and threshold voltage (Vt) should be very less. But the SS state (Vg = 0 V), the width of the tunneling barrier is large
is limited to 60 mV/decade in MOSFETs1. To overcome enough to provide low IOFF values. In the presence of
this, several novel devices with various transport mecha- gate voltage (Vg = 1 V), the band bending in the intrinsic
nism have been reported. Tunnel Field Effect Transistor region causes the barrier width to get reduced, allowing
(TFET), which is one such novel device, employs the car- the electrons to tunnel from source to channel.
rier transport mechanism of Band-to-Band Tunneling
(BTBT). 2.1 Subthreshold Swing (SS)
TFET is a gated p-i-n diode which is turned on Subthreshold Swing (SS) is one of the most important
by applying necessary gate bias. At sufficient bias the characteristics of TFET. It is defined as the change in gate
BTBT takes place, allowing the electrons to tunnel voltage required for one order of magnitude change in
from valance band of p-region to conduction band of drain current. The SS of MOSFET is limited and cannot
intrinsic region, resulting in flow of current across the be reduced below 60 mV/decade at room temperature.
device. TFETs are widely preferred due to their least The Subthreshold Swing for MOSFET and Tunnel FET
SS, less leakage current (IOFF) and low threshold voltage (TFET) at room temperature is defined as follows5.
(V T)2–4.
SMOSFET = ln(10)kT/q (mV / dec) (1)
In this paper, a review on TFETs is presented. Section
2 deals with the characteristics of TFET. Various design
Vgs2
consideration and optimization of the TFETs are analyzed STFET = (2)
in Section 3. The conclusion is given in Section 4. 5.75(Vgs + Const)

*Author for correspondence

 Tunnel Field Effect Transistors for Digital and Analog Applications: A Review

Figure 1. (a) Schematic view (b) Energy band diagram.

Where k is Boltzmann constant, T is temperature (300 K),

q is electron charge, Vgs is applied gate-to-source voltage,
Const is determined by the device dimensions. The SS
value became smaller as gate oxide thickness, Silicon on
Insulator (SOI) layer thickness are decreased in TFET6.
The effective subthreshold slope (reciprocal value of SS)
has been reduced by lowering the channel length and
Figure 2. Effective subthreshold slope for different Lch and
using high k materials as gate dielectrics, which is shown
high k dielectrics7.
in Figure 27. The TFET device is made without junctions
called Junctionless Field Effect Transistor (JLTFET)8,9 to
achieve steep slope. A vertical Si based nanowire TFET
with source side dopant segregated silicidation has been
fabricated with low SS of 30 mV/dec10.

2.2 Improved ION/IOFF Ratio

Due to reduced leakage current (IOFF), TFET is found to be
more suitable for low power applications. Furthermore,
Krishna K. Bhuwalka et al. reported that drive current
(ION) and very low IOFF in TFET can be achieved with
gate work function engineering11. Id – Vg characteristic
of Silicon (Si) based SINGLE GATE (SG) SOI TFET is
shown in Figure 3. It can be inferred that drain current
(Id) increases exponentially with increasing gate voltage
at constant drain bias 12 and this is due to high electron
tunneling at the source side.
For TFET, ION is directly proportional to the tunneling
probability T(E) and it is given by:
È 4 m ∗E 3/2 ˘ Figure 3. Id – Vg characteristics of Si based single- gate
eSi
T (E ) = exp Í t Si t ox ˙ ∆ϕ (3)
g
SOI–TFET12.
Î g ( )
Í 3 e  E + Dϕ eox ˙
˚
where m∗ is the carrier effective mass, Eg is the band gap, reducing tox, increasing εox, and reducing Eg, will enhance
e is the electron charge, ΔΦ is the potential difference the device performance 13. Sweta Chander et al. reported
between source valence band and channel conduction that Silicon Germanium on Insulator (SGOI) TFET of
band, and tox, tSi are the oxide and silicon film thickness gate length (Lg) 30 nm offers more ION/IOFF ratio14 up to
and εox, εSi are dielectric constants of oxide and silicon, 3.4 × 109. Higher ION/IOFF ratio is also obtained for dual
respectively. From the above equation, it is evident that material gate TFET and p-n-i-n TFET15,16.

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 S. Poorvasha, M. Pown and B. Lakshmi

2.3 Threshold Voltage (VT)

Threshold voltage (VT) plays an important role in deter-
mining the device performance. Many approaches were
developed for the enhancement of VT. Gate All Around
(GAA) vertical n-type and p-type TFETs offers reduced
VT in the range of 0.13–0.22 V2. A vertical TFET with
SiGe delta doped layer offers less threshold voltage with
increasing mole fraction (x). The VT variation with
respect to VDS is shown in Figure 4. VT is extracted by
using constant current method. It can be observed from
the graph that, VT is dependent on VDS in the initial state
later exhibiting the saturation behavior17.
Figure 5. Simulated structure of Tunnel FETs (a) Single-
3. Design Consideration and gate (b) Double gate5.

Optimization of TFETs reported in26 has been designed with strained silicon with
3.1 Single Gate and Double Gate TFETs fractional ­germanium content for circuit applications.
The double gate increases the performance by offering
Single gate TFETs possesses low IOFF and also low ION18– improved transconductance and reduced threshold volt-
20
. Increasing the number of gates in the device offers age27. Comparing to conventional MOSFET, DG TFETs
better electrostatic control over the channel. In order offers very low threshold voltage roll-off28, higher ION
to improve ION, second gate is created at the bottom of and decreased IOFF by careful selection of a gate dielec-
single gate TFETs21–25. Figure 5 shows the structure of tric5. Vertical architecture provides an added advantage
nTFET. Double Gate (DG) TFETs Strained DG TFET in terms of reduced Short Channel Effects (SCE)29. For
circuit application, the supply voltage was limited to 0.5 V
when using Ge based TFET30.
Compared to 7T TFET SRAM design, 6T TFET SRAM
design offers better noise margin and improved perfor-
mance. Figures 6(a) and (b) represents the DG TFET
structure and the 6T SRAM design. The graphical repre-
sentation shown in Figure 6(c) denotes the standby leakage
comparison between TFET and CMOS SRAM design.
TFET based SRAM design have reduced leakage over
CMOS based SRAM31. Since the performance of TFET
devices are mainly focused for digital applications, the ana-
log performances are investigated by introducing gate stack
architecture shown in Figure 732. TFET devices are now
becoming a promising candidate for analog applications33–36.

3.2 III-V Material based TFET

Enhancement in ION and SS of DG TFET can be achieved
by introducing Dual Material Gate (DMG) in the device by
using different work functions to the gates37. The device is
also found to be immune to DIBL effects. Figure 8 repre-
sents the top and bottom gates comprising of two different
work functions. The gate nearer to source is called as tunnel
Figure 4. VT as a function of VDS17. gate while the gate nearer to the drain is called as auxiliary

Vol 10 (13) | April 2017 | www.indjst.org Indian Journal of Science and Technology 3
 Tunnel Field Effect Transistors for Digital and Analog Applications: A Review

Figure 8. Structure of dual material DG TFET41.

Figure 6. (a) DG TFET structure (b) 6T SRAM design
based DG TFET (c) Standby leakage comparison of DG
TFET over CMOS SRAM design31.

Figure 9. Structure of an asymmetric gate oxide DG

TFET46.

Figure 7. (a) Gate stack DG TFET structure (b)

Transconductance gm variation with Vgs of GS-DG TFET
over DG TFET32.

gate. Due to indirect bandgap material and lower tunnel-

ing probability, Silicon (Si) based DG TFETs38 suffers from
lesser ION, which can be further improved by using lower
band gap material like Silicon-Germanium (SiGe)39-42.
Figure 10. Gate on drain overlap structure of DG TFET48.
Si1-xGex TFET exhibited the better performance with low
SS by optimizing the mole fraction (x)43. Small band gap
material at the drain. Further to control the high gate
materials were used to improve the carrier tunneling by
drain capacitance problem, low oxide material (SiO2) is
reducing the width of the tunneling barrier44. Additionally,
replaced by air (k = 1) at the drain side of the device and
a smaller bandgap material, In GaAs is used at the source
thereby resulting in improved cut off frequency. Further
of Si-based p-TFET to boost the ON current45.
the energy dissipation per cycle and the reduced propaga-
tion delay obtained from circuit level performance results
3.3 Asymmetric Gate Oxide in better switching characteristics and thereby making
Rakhi Narang et al. had reported that the performance the asymmetric gate oxide DG TFET more suitable for
enhancement of an asymmetric gate oxide DG TFET is low power digital applications. Figure 9 shows the struc-
observed with a high-k dielectric at the source and low-k ture of an asymmetric gate oxide DG TFET46.

4 Vol 10 (13) | April 2017 | www.indjst.org Indian Journal of Science and Technology
 S. Poorvasha, M. Pown and B. Lakshmi

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