Asynchronous FIFO Design using Verilog-HDL
Project Timeline and Synopsis
1 Synopsis
The project aims to design and implement an Asynchronous FIFO (First-In First-
Out) buffer using Verilog-HDL at the RTL level. An asynchronous FIFO enables safe
data transfer between two subsystems operating on different clock domains, while
preserving data order. It is commonly used in digital systems where producers and
consumers operate at different speeds, such as processor-to-UART communication, DMA
transfers, or clock domain crossing interfaces.
The FIFO will be realized as a memory array controlled by independent write and
read logic, with reliable full and empty detection achieved using pointer synchroniza-
tion through Gray code representation. The design will be modular and verified using
simulation testbenches under varying clock frequencies and corner-case scenarios.
2 Objectives
• To understand the concept of synchronous vs. asynchronous FIFOs.
• To design the RTL architecture of an asynchronous FIFO.
• To implement separate write and read control modules, operating on different
clock domains.
• To ensure reliable full and empty detection through pointer synchronization.
• To verify the design through comprehensive simulation testbenches.
3 Project Modules
3.1 Memory Array (Dual-Port RAM)
Description: Stores the data elements written into the FIFO.
Implementation: A simple dual-port memory allowing simultaneous read and write
operations.
3.2 Write Control Logic
Description: Manages writing of data into the memory array.
Functionality:
• Maintains a write pointer in binary form for arithmetic increments.
• Converts this pointer into Gray code before transmitting to the read clock domain,
ensuring only one bit changes per increment.
• Receives the synchronized read pointer from the other domain to compute the full
condition.
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3.3 Read Control Logic
Description: Manages reading of data from the memory array.
Functionality:
• Maintains a read pointer in binary form for arithmetic increments.
• Converts this pointer into Gray code before transmitting to the write clock do-
main.
• Receives the synchronized write pointer to compute the empty condition.
3.4 Pointer Synchronization and Status Flags
Since write and read pointers belong to different clock domains, direct comparison is
unsafe. Synchronization ensures reliable detection of full and empty states.
Method:
• Gray-coded pointers are passed across clock domains.
• Two-stage flip-flop synchronizers are used to protect against metastability.
• In the local domain, synchronized Gray-coded pointers may optionally be converted
back to binary for comparison.
Empty Condition: FIFO is empty when write and read pointers are equal, with
identical wrap bits.
Full Condition: FIFO is full when write and read pointers are equal, but the wrap bits
differ, indicating a complete traversal of the buffer.
3.5 Top-Level Integration and Testbench
The top-level FIFO integrates memory, write control, read control, and synchronization.
A simulation testbench will:
• Generate two clocks (wr clk and rd clk) of different frequencies.
• Stimulate data writes and reads, verifying that FIFO preserves order.
• Test corner cases: empty read, full write, and simultaneous read/write operations.
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4 Project Timeline
[Link]. Task Deliverables
1 Literature study on synchronous vs. Notes, discussion
asynchronous FIFOs
2 RTL design planning, module alloca- Block diagram
tion
3 Memory module implementation Dual-port RAM code
4 Write control logic with Gray encod- RTL code with pointer handling
ing
5 Read control logic with Gray encod- RTL code with pointer handling
ing
6 Synchronization and full/empty de- Verified logic and flags
tection
7 Top-level FIFO integration Unified RTL FIFO module
8 Testbench development and simula- Functional verification results
tion
9 Final documentation and presenta- Report, simulation waveforms
tion
5 Expected Outcomes
• A functional asynchronous FIFO design in Verilog-HDL.
• Verified simulation showing correct data transfer between different clock domains.
• Understanding of Gray-coded pointer synchronization as a method to achieve reli-
able communication across asynchronous boundaries.
• Modular project structure enabling parallel development.
