and Issues

2 Unit II
Digital Design

Syllabus Machines, FIFO

Sequential synchronous
machine design, Moore and Mealy machines, HDL code for
Hazards, Clock distribution,
Meta-stability
Clock jitter, SuppBy
Fan-out, Skew, Timing considerations,
techniques,
and
Wire parasitic, ground
solutions. Noise margin, Interconnect routing
bounce, Power distribution techniques,
Power optimization. Signa
integrity issues. VOarchitecture

2.1 Sequential Circuits

types combinational circuits and sequential circuits. The o
Digital circuits can be broadly classified into two present values of input applied to it.
of combinational logic circuits are determined completely by the
sequential logic circuit on the other hand depends not only on the present input applied tothe ci
Output of
on the history of past inputs applied to
but also on the present state of the circuit which in turn depends
circuit.
required. Thus, sequential logic circ
In order to store the history of the past inputs some kind of memory is
and memory elements
are composed of combinational logic circuits to evaluate the next state and output logic
store the present state of the circuit.
Memories can be implemented in the form of flip-flops. The value stored in the flip flop tells the state of :
circuit.

Sequential circuits are formally called finite state machines (FSM). It is called so since the behaviour of s
circuits can be represented using a finite number of states. Usually, any sequential logic circuit is either a N
machine or Moore's Machine. Fig, 2.1.1 (a) and (b) shows the block diagram of the Mealy and Moore's mac
respectively.
Pimary
nput Combinational Output
Combinational Memors Logic cit
Lagic crcit (Fåp topst (outut
Seoondary bgic)
0nput

(a) Mealy Model

Primary
input
Combinationai Combinational
Login cRU omory Logic cicut
(Fip tops
Secondary (output
input bgic)

(b) Moore Model

Fig. 2.1.1
VLSIDesign & leChhUI
another.
from one node to
machines. One and the rays directed unique
There are two sets of inputs to each represents a
from the Each node in state machine
is called the primary input that comes rays are labeled by the
state of the machine. The
external world while the other is called secondary the state transition.
input conditions responsible for state in FSM
input that is feedback from the memory to the input The transition from one
state to other
combinational logiccircuit. signal (either positive or
is controlled by the clock
The sequential logic circuits whose output depends negative edge trigger).
is
on both present state and the primary inputs Diagram
called Mealy machine. As seen in the Fig. 2.1.1(a), 2.1.1 Mealy Machine State
circuit machine state diagram is
the inputs to the output combinational logic States in a Mealy
The letter written
are both the primary inputs and the output of the represented by nodes (circle). Transitions
name of the state.
flip flops working as memory inferring the present inside the node is the
by the directed arcs.
state of the circuit. Such circuits are
called Mealy between the states is shown separated
of two digits
machine. Each are has label consisting input
digit tells the current
The formal definition of the Mealy
machine can be by a slash. The first
the second digit
mathematically expressed as, applied to the círcuit and circuit Fig. 2.1.2
corresponds to the output of the
NS = f (PS, PI) diagram consisting of four
shows a Mealy state
Output =f2 (PS, PI) states S0, S1, S2 and S3.
Where, NS refers next state O/0
the circuit
PS refersthe present state of
Plrefers to the present input. 1/0
that both next state and
The above expression says
function of both present
the output of the circuit are
1/0 }1/0
it.
state and present input applied to
circuits whose output
Whereas, the sequential
state of the circuit are S2
depends on only the present output
O/0
input to the
called Moore machine. The Fig. 2.1.2 : Mealy state diagram
is only the
combinational circuit is Fig. 2.1.1(b) indirectly isapplied to the input of the circuit when
block, which If logic "1'
output of the memory circuit goes to state S1. This
inputs applied to the it is in S0 state, the
depends on the primary shown by an arc
definition of the
Moore's transition state from S0 to S1 is
circuit. The formal arc has a label 1/0
expressed as, pointing towards S1 state. This
machine can be mathematically saying that input is 1 and the
output generated by
hand, if a 0 input is
NS = f (PS, PI) the circuit is 0. On the other
remnains in the same
Output = f2 (PS) received when it isin S0 state it
function thus label associated
equation says that the next state is state and produces 0 output,
The first the state diagram for the
current state and primary
inputs while with this arc is 0/0. This is a
of both sequence coming
function of present state
only. circuit that could detect 1101
output is the state
begins by drawing through its input line.
The FSM design graphical
describes the circuit in
diagram which
pictorial way to describe 2.1.2 Moore State Diagram
a
form. State diagram is circuit. It depicts state diagram, states are represented
by
behavior of the Like Mealy state
the the input. A
state circle is the
application of node (circle) and the letter inside the
transitions on
information about the the
complete state name. The output value produced by
dlagram conveys circuit at each clock
tick
inside the node separated
from the
output of the circuit is written
next state and of inputs. The state
combination state name with a slash.
Tor all possible nodes represented by circuit Tech Knowled
dlagram consists of
 Digital
VLSI Design &Technology (SPPU)
2-3
state
Design and ls uw
Transitions of state is represented using directed (1) Construct the diagramn from
description. he wo
arc that carry label. The label now consist of a single
digit referring the input applied to the circuit (2) Form thestate/output table.
Fig. 2.1.3 shows a Moore's state diagram.
(3) Assign state variable combinations to each
build a transition/output table. state an,
(soro (4) choose the type of flip-flop.
(5) Number of flip-flop requirement
The relationship depends
number of states.
between
numbe
of states and number of fip-tlop 1s n : logTh
with n number of flip-flops 2n states are
possible.
(6) Using flip-flop excitation table
Fig. 2.1.3 : Moore state diagram
The output of the circuit becomes 1, only when it is values required to obtain a desired next
determine
each combination of present state and input.
state
in state S3. Thus the node corresponding to state S3
contain 1 inside it. Both the FSM models have (7) Derive expression for each flip-flop input.
similar computational capacity. Mealy model
typically requires less number of states and thus (8) Derive the output equation from
lesser hardware to realize the circuit. transition/output table.
2.2 (9) Draw the logicdiagram.
Analysis of Synchronous Sequential
Circuit Let us design a Moore model that detects three
more consecutive zero's coming through its input lineX
Analysis of a sequential logic circuit refers to the
complete study of the circuit so as to understand the We start from the reset state S0. If the
first inpu
behavior and purpose of the circuit. Analysis is done by received is 0', the circuit goes to state S1 indicati:
determining the next state and output equations of the arrival of first desired bit. Being in state S1 if the ner
circuit. The information obtained from these input received is again '0', the circuit goes to next stat
then presented in graphical form calledequations
is
the state S2 indicating arrival of two bits of
diagram. Following are the steps involved in analysis desired sequene
When in state S2 if the next input received is
process: again
the circuit goes to next state S3
(1) indicating arrival ot tu
Determine flip flop input equations and output desired sequence. Now since three consecutive '° D:
equation. are received, output at this state becomes high. The st
(2) Evaluate the next state equations. dlagram is partially complete. We need to consider :
(3) Using the above equation build a remaining possibilities. Let us start from the reset SE
state/output table
that specifies the next state and output S0 and assume that a 1' bit is
of the circuit received. Circuit stays
for each
combination present state and present
of the same state S0
waiting for the first desired bit t
input.
come. When in state S1 (meaning first '1' bittis received
(4) The information available in the above step if the next input bit
presented in a graphical form called state diagram. is received is '0,the circuit mus.
by going back to state SO and must wait for the firstbit!
2.3 the desird Sequence. When in state $2 (after receptie
Synchronous Sequential Machine of two consecutive 1's) if the third input is 0, theciru
(Circuit) Design
must reset and go back to state S0.
Sequential circuit design
word description and is usually starts from the The state diagram is
depicted in Fig.
[Link]
concluded by the circuit diagra
diagram. The steps involved in the state/output table
can be easily [Link]
to this state
sequential circuit design in listed below : synchronous
 VLSIDesign &Technology (SPPU) 2-4 Digital Design and Issues

Present state Next state (NS)

PS) Output
SO/O s1/0 InputX=0 X=1

1 0

0 1 1

{s2/0 1 0 1 1 0

1 1 1 1 1
Fig. 2.3.1
Present state Next state (NS) Since the flip flop used is D-flip flop, we will be using
Output excitation table to D flip flop to determine the
(PS)
Input X=0 X=1 expression of flip flop inputs.
SO SO S1 0 Excitation table ofD-flip flop is given below.
S1 SO PS NS D-input
D
S2 SO
0
S3 SO S3 1
1 1
This table is converted into transition table by
1 0
assigning binary values to each of the alphanumeric
1 1 1
name. For example 00 is assigned to state S0, 01 is
assigned to state S1, 10 is assigned to state S2 and 11 to The first row of table implies that to have a
state S3. The transition table is shown below. transition from state '0' to state '0', we need to apply 0'
to D-input. Second row says that to have a transition
from state 0 to state '1', we need to apply "1 to D-input of
the flip-flop. Similar interpretation is for row 3 and 4.
Thus we can say that whatever next state is required, we
need to apply same value to D-input. This forces circuit
to the required next state at the following clock tick.
the given circuit.
Using this table we will build an esxcitation table for
PS Input Next state Flip flop Inputs Output
DA DB

1 0 1 1 0

0
1

1 1 0 1 0
1
0
1
1 1 1 1 1
1
0 1
1 1
1 1 1 1
1 1 1
1
TedkKnoued:
 Digital Design and
2-5 ls ue
VLSI Desig
(SPPU) D-input.
VLSIDesign &Technology minimized
expressionfor
01 11 10
00 PS
obtaín
Now using K-map, we X

01 11 10
X 00 1

= (Q + QB) X 0
(Q4+ Og) X
DA =Q4 X+Qg X= 1
11 10
00 01 1
0
Using
1 excitation ta
PS Ir
Y=Qa Qg
received is 1
So is the reset state. If the first bit
following
Realizing these equations yields the circuit goes to next
state S1 indicating reception of f
0
the new
circuit diagram. desired bit of the sequence. Being on state S1, if
stat
input received is again 1, circuit moves to the next
$2 indicating reception of first two desired bits of the 1

sequence. Being in state SZ if a "0' is received at the innut 1

it goes to S3 state indicating reception of three desiret 1 0
bits. Now if a'1' is received, this completes the desired
sequence and hence the output of the circuit becomes 1.
1

Circuit has moved to state S1 since this 1' received 1 1

becomes the first bit of the desired sequence and infers 1 1

that first desired bit of the sequence is received. Now le
us consider the remaining cases. When in reset state, ia
'0' is received it must stay in the same state waiting tor
Ciock the desired bit to be received. When that happens it goës
Fig. 2.3.2 to S1 state. Now if a 0 is recei2ved, circuit again goes 0
Design Examples : SOstate. Similarly complete the state diagram.
We willwrite state table for the same circuit.
Ex. 2.3.1 : Design a Mealy sequential circuit using D-flip
flop for detecting an overlapping sequence 1101. PS NS output
Soln. :
X=1
Westart by drawing the sate diagram
SO S1, 0
O/0 SO, 0
S1 S0, 0 S2, 0
1/0
S2 S3, 0 S1,0
1/0 4/0 S3, 0 S1, 1
Since there are 4 states, two flip-flops arerequired
Let us say QA and QR are the state Alipflop
of each the
each of
Fig. P. 2.3.1 respectively. Assigning state variables to S1,10toS
alphanumeric names
and 11 to S3, we get the
such as 00 to S0, 01 to
transition table.
echknowlel
Pu1rati0
 VLSIDesign &Technology (SPPU) 2-6 Digital Design and Issues
PS NS
11 00 01 11 10

X=0 X= 1 0

00, 0 01,
0 1 00, 10, Ex. 2.3.2:Design a mealy sequential circuit for detecting the
1 0 11, 01, same overlapping sequence 1101 solved in Example 2.3.1,
1 1 00, 01, 1 using JK flip flops.
Soln. : The state diagram will remain same as in Example
Using excitation table of D-flip-flop, we built the
2.3.1 and is redrawn in Fig, P. 2.3.2.
excitation table of the circuit. O/0

PS Input| Next state Flip flop inputs |Output

1/0
le
X D D
St 0 0 0 1/0 1/o
xt
0 0 1 1 1 0
te
0 1 0 0 O/0

It, Fig. P. 2.3.2

1 1 1 1
d
0 1 1 1 1 0
State/output table for this state diagram is given
ed below:
1. 1 1 1 1
PS NS output
1 1 0 0 X= 0 X=1 QAQB
X 00 01 11 10
rs
1 1 1 0 1 1 1
et
SO S0, 0 S1, 0
S1 So, 0 S2, 0
S2 S3, 0 s3, 0
S3 S0, 0 S1, 1 y=OQg X

DA

Da QR

d.

Clock

2 Fig. P. 2.3.2(a)
TechKnewledge
Puntation
 Digital Design and
2-7
00 11
Is ues
11 10 10
(SPPU)
Design &Technology
00
VLSI 3
X
NS
PS 4
X=0
Jg Q+X Kg =ã+
0 01 11 10
0 01. 00
0 00,
10,
1 00,
01, 0
1 0 11,
0 01, 1
1 1 00,
be using
flop flip to be used is JK, we will
Since the the
table of IK flip-flop to determine
excitation
expressionsof flip flop inputs.
given below:
Excitation table of JKflip flop is
PS NS JKInput
K
0 X

0 1 1 X

1 0 X 1

1 1 X 0

Excitation table of JKflip-flop:

Using the above table we will build excitation table
for the given circuit Clock
PS Fplopinputs Output
Fig. P. 2.3.2(b)

X X 2.4 VHDL for Finite State Machines

1 1 X 1
Basically FSM consist of a combinational logic anda
X 1 memory element to store the state of the circut
1 X Combinational logic is used to decide the next state o
1 1
the FSM.
1 1 1 X
There are two types of state machines:
X 1
Mealy state machine : Its output depends on bot
current state and current inputs applied to it.
1 1 X th:
Moore state machine : Its output depends on
1 X

01
current state of the machine only.
11 10 00 01 11 10 The machine
X 10
methodology for writing
as follows:
finite state

10 1( X 1) Draw the state diagram. Label all conditions, lab?

encoding
all output value and also label the state
Ky =Qg +X 2) Use parameter toencode the states.

TechKnewl
Puhlratlp!
Ssues
VLSI Design &Technology (SPPU) 2-8 Digital Design and Issues

3) Use two processes or always statement one

else
sequential and one combination.
NS <= S0;
4) The combinational process normally has one big
case statement in it. Put default values at the End If;
beginning When S1=>
Example : Y<='0';
The HDL description of the state diagram of IfX=0' then
Fig. 2.4.1 is given in the example. Fig. 2.4.1 is the state NS <= S2;
diagram of a circuit that detects 3 or more consecutive else
zeros in a string of bits coming through its input line. NS<= S1;
End if;
When S2 = >
Soro Si/0 Y<=0'
IfX =0' then
NS<=
else
NS <=
(S3/1
End if;
When S3 =>
Fig. 2.4.1:Moore state diagram Y<=1;
Ex. 2.4.1 :Sequence detector. Ifx=0' then

Soln. : NS<
/ moore state diagram else
NS <=;
Library IEEE;
Use [Link] logic [Link]; End if;
When others >null;
Entity seq-det is
Port (X: in std logic; End case;

Clk:in std_logic; End process;

Process (clk)
Y: out std _logic
If clk event and clk ='0' then
and a End sep det;
Architecture ckt of seq_det is PS< NS;
circuit.
state of End if;
Type state is (S0,S2, S2, S3);
End process;
Slgnal PS, NS: state;
End ckt;
nboth Begin declared
In the above example X, clk and reset are
Process (PS, X) flip flops is
as input, y is the output. The state of the
These variables hold
on the
Begin declared with identifiers PS and NS.
Case PS is
the state of the sequential circuit.
blocks that
chineis
When SO => The HDLdescription uses two process the
block determines
execute concurrently The first
and input x.
s ,label Y<='0 value of NS and output as a function of PS
at every clock
oding. IfX= 0' then The second block PS becomes equal to NS
NS <= S1, tick.
TechKowledge
puallratnns
 2-9
Digital Design and
VLSI Design &Technology (SPPU)
detector
y <= '0'; Is ues
EX. 2,4.2 : Wnite VHDL code for 101 sequence ifX="0' then
using Moore state diagram. NS <=SO;

State diagram : else

NS <=S3;
End if;
SOo) S1/0) When S3 =>
y<=1
if X = "0' then
NS <= S2;
else
S2/0
NS <= S1;
End if;
Fig. P. 2.4.2 when others => null;

Soln. :VHDL Code: End case;

End process;
Library IEEE; Process (clk)
Use IEEE, Std_logic [Link]; Begin
Use IEEE. Std_logic [Link]; If clk event and clk=0' then ...falling edge of clok
Entity seq_detect is PS <= NS;
port (X,clk :in std_logic; End if,
Y:out std _logic);
End process;
End seq_ deted; End moore;
Architecture Moore of seq_detect is
type state is (S0, S1, S2, S3); Ex. 2.4.3: Write VHDL cOde for 101 sequence detectr
signal PS, NS : state; using Mealy state diagram.
Begin State diagram :
PROCESs (PS,X)
Begin
Case PS is 1/0
when SO =>
y <= "0;
ifX= 0 then oo
NS <= S0;
eise,
NS <= S1; Fig. P. 2.4.3
End if; Soln. : VHDL code:
when S1 =>
y<=0'; Library IEEE;
ifX='0' then |Use IEEE.std_logic [Link];
NS <= S2; Entity seq-detector is
else Port (X, clk:in std_logic;
NS <= S1; Y :out std_logic);
End if; Endseqdetector;
when S2 => |Architecture Mealy of seq_detector is
type state is (S0, S1, S2) TechKnowlei
 Digital Design and Issues
VLSIDesign &Technology (SPPU) 2-10

signal PS, NS: state ;

1 S1/0
Begin so0
process (PS, X)
Begin
(S4/1)
case state is
when SO =>
s3/1 S2/0)
ifX = 0' then
y<=»0';
NS <= S0;
else
y <= 0' Fig. P. 24.4

NS <= S1; Soln. :VHDL Code :

End if; |Library IEEE;

when S1 => Use IEEE.std_logic_1164.all;
ifX= 0' then Entity seq_detector is
port (X,clk :in std_logic;
y <= 0';
y:out std Jogic);
NS <= S2;
End seq_detector ;
else Architecture moore of seq_detector is
y=0'; Type PS, NS : state;
NS <= S1;
Begin
End if; process (PS, X)
when S2 => Begin
if X= 0' then case PS is

y <= "0'; when SO =>

NS <= S0; y<='0'

IfX = "0' then
else
NS <= S0:
y<="1;
else
NS <= S1;
NS <= S1;
End if ;
End if;
When others => null ;
when S1 =>
End case; y<='0';
End process ; if X= '0' then
process (clk) NS <= S2;
Begin else
if clk event and clk=0' then NS <= S0;
PS <= NS; End if;
End if; when S2 =>

End process; y <=S0;

else
End mealy;
detector
NS <= S3;
Ex. 2.4.4: Write VHDL Code for 1011 sequence End if;
using Moore model. when S3 =>
TechKnowledg
Puhcatio
 2-11

VLSI Design &Technology (SPPU) Library lEEE

_logic_1164 all,
y <='0; Use 1EEE. Std
ifX= '0' then
NS K= S2; entityJKFF in
port J,K, Clock, Reset, Clear; in std_logic;
else
NS <= S4; QQ bar i out std_logic);
End if; Jend JKFE;
when S4 =>
y='1' archítecture JKFF of]KFF is
ifX = "0' then type state is (S0, S1);
NS <=S0:
Else begin
process(Clock)
NS <= S1;
begin
End if; if (Clock even and clock = '0)then
when others => null;
PS = NS;
End case;
end if;
End process ;
end process;
process (clk) process(PS,J, K, Present, Clear)
Begin
If clk event and clk=0' then begin
if (Present = 0' and clear ='1) then
PS <= NS;
Q=1
End if ;
PS = S1;
End process ;
else if(Present = "1' and clear= 0)then
End moore;
Q=0'
Ex. 2.4.5: Write a VHDL COde for JK flip flop. PS -S0;
K Q(PS) Q (NS) Else
case PS is
0 0
1 1
when S0’if (( = '1) then
Q=1.
1
PS = S1;
1 1 Else
1 1 Q=0
1 -
1 1 end if;
1
1
when S1’if (k= '1) then
Q=0'
1 1
PS = S0;
State diagram for JK flip tlop in given below: Else
01/11 (Ju X, k= 1) Q=1
00/01
end if;
)0010 end case;
(J # and k X) end if;
10/11 S, (JX, k 0)
(J 1, k X) end process;
QUAR ¢ not Q;
(0-544)Fig.P.2.4.5 end JKFF;
 VLSIDesign &Technology (SPPU) 2-12 Digital Design and Issues
2.5 FIFO
VHDL Ccode for FIFO:
In adigital system often there is an exchange of data library IEEE;
between printed circuit boards (PCBs). If the two |use IEEE.STD_L0GIC_1164.ALL;
PCBs are working at different speeds, then we use IEEE.NUMERIC_STD.ALL;
require intermediate storage or buffer.
A FIFO is a special type of buffer. The name FIF0 entity FlFO is
stands for first in first out which means that the data generic (depth : integer := 16); --depth of fifo
written into the buffer first comes out of it first. port (clk: instd_logic;
Jf the tWo systems connected by FIFO can
work out reset: in std_logic;
of synchronism, the FIFO is called
concurrent enr:in std_logic; --enable read,should be '0'when not
in use.
read/write FIFO. In concurrent read/write FIFOs,
there is no dependence between the writing and enw: in std_logic; --enable write,should be '0' when not
in use.
reading of data. Simultaneous writing and reading
are possible in an overlapping fashion Or data_in : in std_logic_vector (7 downto 0); --input data
successively. data_out :out std_logic_vector(7 downto 0); --output
data
The concurrent read/write FIFOs, depending on the fifo_empty :out stdJogic; --set as'1' when the queue is
control signals for writing and reading, fall into two
empty
groups:
|fifo_full : out std_logic --set as '1' when the queue is full
Synchronous FIFOs
):
Asynchronous FIFOs end FIFO;
In a synchronous FIFO, the two ports can be
designed to operate with a common clock or larchitecture Behavioral of FIFO is
different clocks.
type memory_type is array (0to depth-1) of
FIFOs alsohave a width, which represents the width std_logic_vector(7 downto 0);
of the data (in number of bits) that enters the FIFO.
signal memory : memory_type :=(others => (others =>
The Write Enable, Write Data, and FIFO Full signals |'0)): --memory for queue.
are available at write side. Below is an image of the signal readptr, writeptr: integer := 0; --read and write
basic interface of any FIFO. pointers.
signal empty,full : std_logic := '0';
Read_enable
Write_enable |begin
Write_data FIFO Read_data
fifo _empty <= empty:
FIFO_empty
FIFO_Full fifo _full<=full;
process(CIk,reset)
Fig.2.5.1: Basic Interface Signals of a FIFO --this is the number of elements stored in fifo at a time.
problem. An
FIFO may suffer with overflow --this variable is used to decide whether the fifo is empty
made to write
Overflow occurs when an attempt is or full.
new data to a full FIFO. variable num_elem : integer := 0;
FIF0 Empty
The Read Enable, Read Data, and begin
signalsare available at the read side. |if(reset = "1)then
problem. When an
FIFOmay suffer with underflow On a read data_out <= (others => '0);
empty FIFO has no data to provide empty <='0';
request, results in an underflow. full <='0';
Tech Knowledge
 maximu VLS
2-13 the
Where, V,is logic0.
interpretedas Th
VLSI Design &
Technology (SPPU) be minimum input voltage which can be lo:
VH is the logic1. hi
readptr <=0; interpretedas
maximum output voltage
when
writeptr <= 0;
Vor isthe
the outp 2.8
num_elem := 0;
logic 0.
elsif(rising edge(Clk)) then Vo#isisthe
level minimum output voltage when the outpu Se
empty= '0) then --read til
if(enr ="1' andmemory(readptr);
data_out<=
is logic1. be
level
readptr <= readptr + 1; Vin H
num_elem := num_elem-1; 4
VoD d
to
end if; --write
if(enw ='1' and full= '0) then T
memory[writeptr) <=data_in; VgH
writeptr <= Writeptr + 1;
elem+1;
num_elem := num_ VL Clocl
end if; --resettingread pointer. NM
if(readptr= depth-1) then
readptr <= 0;
voltage noise marain
end if; -resetting write Fig. 2.6.1: Definition of the
if(writeptr =depth-1) then Due to noise the signal value may
differ at the twn D
inp
pointer. us consider tn
writeptr <= 0; ends of an interconnect line. Let
cascaded identical inverters to illustrate the effect o
end if; circuit.
--setting empty and full flags. noise on the correct functioning of the
if(num_elem =0) then Vo1 =Vo Ving Vu Vo2 =VoH 2.8.:
empty <= '1; |Uni
else Interconnect
empty <= '0'; Fig. 2.6.2
end if;
if(num_elem = depth) then The input to the 1st inverter is V1H ie. logic 1, so t
full <='1'; Produces a logic "0' output (VoL). Now this outputS
else given to the input of 2nd inverter via interconnect
full <= '0'; The signal while travelling through interconned
noise resus
end if;
may get perturbed due to noise. If the
Jend if;
In changing the signal value smaller then Vou
the
end process;
would still be recognized correctly as logic»0'by
end Behavioral;
second inverter.
thanV
2.6 Noise Margin But if the signal value happens to belarger secon
the
it would not be recognized as logic '0' by voltag'
Noise margin gives the measure of input
sensitivity of a inverter. Thus, V. is the maximum
gate to noise. It that can be interpreted as logic '0'.
essentially
noise that can be accepted represents the level of
when gates are cascaded. 2.7 Fan out
It is specified
with two definet
Low (NM,) and Noise parameters Noise Margin Fan out a logic gate parameter that
Margin High (NM;). System
NM, =V-VoL number of gates if can drive. In a digital
and connected
NMå = VOH- VIH able to drive number of circuit outpu
levels
without degrade the convert logic the gate.
ck
 VLSIDesign &Technology (SPPU) 2-14 Digital Design and Issues
The maximum fan out of an output measures its
Q. What is meant by metastability? Explain any one
Joad driving capability. Higher the value of fan out
solution in detail. SPPU - Aug. 17, 5 Marks
higher the current supply capacity.
Q. Explain metastability with timing diagram.
2.8 Timing Considerations
SPPU- Dec. 17,6 Marks
Set up time:Set up time is the minimum amount of
Q. What is role of synchronizer in metastability problem?
time the input data signal must be held steady Explain any one synchronizer with timing diagram.
before the clock tick.
SPPU- Dec. 14, 9Marks
Holdtime is the minimum amount of time the input
a. Wite short note on metastabilityand synchronizers.
data signal must be held steady after the clock tick
SPPU - Aug. 18, 5 Marks
to ensure reliable sampling of data. Q. Explain what is metastability and solution for it.
The Fig. 2.8.1 shown below reflects these two
parameters: SPPU- Oct 19, 6 marks
A
bistable device can exist in either of the two stable
states logic '0' as logic '1. If the data signal value
Clock
changes at the same time during the clock tick, then
the flip flop goes to an metastable state which is an
lgetup thokd unstable state. At the end of the metastable state,
the flip flop settles down to one of the stable states.

D
In order to understand the ways to avoid
input metastability two parameters must be defined :
1 setup time and hold time,
Fig. 2.8.1 When the input signal(shown in Fig. 2.8.1) change
within time t, the output can become metastable
2.8.1 Metastability and Solution and will drift between the high and low states.
UniversityQuestions Fig. 2.8.2 illustrates the setup and hold violations.
Q. Write a short note on Metastability. Whenever there are setup and hold time violations
SPPU - May 12, Dec. 12, 8 Marks in any flip flop, it enters into metastable state.

setup 'hold

t Clock
S
t Data 0 Valid

Valid
Data
d

Setup violation
Data 2

Hold violation
Data 3
e

Fig. 2.8.2
of Techknowtedye
 Digital Design and
2-15
the data 0ssuey
VLSIDesign &Technology
(SPPU) This is
achieved by passing
flip-flops connected input throug,
in serics.
two buffered
after tw,The
output will be Correct
second flip-flop occurrence of two
Clock
clocks as the
metastable states is almost impossible). The
flops must be provided by the same system cloc
consecutive
rest of the circuit.
that is running

Output
Asynchronous
Inpul
D Syncouthropnut
Meta stable
output

Fig. 2.8.3
asynchronous
Metastability occurs whenever two
that the resulting
signals combine in such a way CLk
Fig. 2.8.5
intermediate state. This is
output goes to an
hill (shown in
analogous to a ball on top of the
represents the metastable 2.9 Timing issues in Synchronous
Fig. 2.8.4). Top of the hill Sequential Design
represents the
state, whereas each side of the hill
metastable
stable state. Whenever output goes to Clock skew and clock jitter are the major timing
goes to one
state after some finite amount of time it issues in synchronous circuit design.
situation that
of the stable states. It is similar to the
2.9.1 Clock Skew
aslight air would rolldown the ball lying at the peak
of the hill to either of one side. University Questions
Q. Explain the following: Clock Skew.
SPPU - Dec. 11, May 15,May 17, Oct. 19,3 Marks
0. What is Clock Skew.
SPPU- May 12, Dec. 12, Dec. 13, Aug. 18,4 Marks
Q. Explain Clock skew with an example. How to
minimize the effect of clock skew ?
Stable state Meta stable
state
Stable state SPPU - May 13, May19,8 Marks
Q. What is clock skew ? Explain the solutions to it.
Fig. 2.8.4
SPPU- May 16, 6 Marks
Metastability for example occurs in alatch or flip
flop when it violates setup and hold time
Q. What is clock skew? What are techniqueS to minimize?
SPPU- Aug. 16,5 Marks
specifications. The metastability event can lead to
failure if the output does not resolve itself and go to Q. What is the reason of clock skew? List various clock
some valid state. Flip-flops take some additional distribution techniques. Explain any one of them.
time to settle to a stable output. SPPU - Aug. 17.5Marks
How to avoid metastability ? Q. Explain positive and negative clock skew. Briely
By synchronizing any explain the sources of clock skew.
least one or two asynchronous
input though at SPPU- Dec.17. 6 Marks
series connected flip-flops Q.
metastability can be avoide. Explain different technigues of clock distribution.
The data input to the flip-flop is SPPU-May 12, Dec. 12, 4 MarKS
clock. Since the time when input asynchronous to the Q. Explain clock skew and write in detail about positive
with respect to clock is not data will arrive and negative clock skew. SPPU- Dec. 18, 6 Marks
be chances of known, thus there could clocki
In a synchronous design
metastability.
data input metastability By
could be synchronising the routed approach, a single
generation
avoided, throughout the chip. Thus clock
and distribution plays an important role in such
type of system design.
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VLSI Design &Technology (SPPU) 2-16 Digital Design and lssues
Clock distribution has to be balanced so that phase
of clock (i.e. position of clock edge with When select input (select) is high it would sample
respect to new data otherwise it would hold the data
reference) at different places in the system is
irrespective of the value of the clock signal.
exactly same i.e. phase difference is zero).
Fig. 2.9.2 is the circuit which can hold its content for
However this is not practically achievable and more than one clock periods.
results into clock skew. The spatial variation in
clock transition time on an Integrated Circuit (1C) is
called clock skew. D
2:1
For example, if clock transition reaches at
point A on
1C at time t, with respect to reference clock and it
MUX
Data
reaches point B at time t, with respect to references
clock than clock skew between the two points Select
Clock
is t -ta (CIk)
Reference clock Fig.2.9.2 : Data storage for multiple clocks
Another approach which is although rarely used but
results in reduction of hardware Cost is
accomplished by using clock gating. The clock pulse
to the storage element is permitted for loading and
suppressed for holding data.
Data

Fig. 2.9.1: Clock skew

Enable
An example illustrating clock skewing is the clock
gating circuit. Many atime in adigital circuit it is Ciock
(Ck)
desirable to hold the content of the storage element
Fig.2.9.3: Clock gating
for more than one clock period.
D-latch which is most popular and widely used The clock is applied to the memory element through
the AND gate. Only when the enable input is high, it
storage element, characteristically can hold value receives the clock input else it hold the stored data.
only for one clock period. One way to make it hold To understand these issues related to synchronous
information for more than one clock period is by circuit design, it is necessary to known the following
introducing a feedback mechanism. parameters :
the
By providing a feedback path from the output of Set-up time is the time during which D-input must
between
flip flop to its input with a multiplexer inthe
be stable before the clock transition happens.
which will decide whether to hold or update Hold time is the minimum time the D-flip flop must
stored data. be held constant after the transition occurs.

CIk Hold
Setup time
time

important parameters
Fia. 2.9.4:Waveform showing Tech Knewledge
Puolir at ions
 Digital Design and
Issuee
2-17 2.9.7 shows
skew : Fig.
VLSIDesign &Technology (SPPU)
combinational
Negative
clock skew.
clock
The positive
clock edge CLK2 negatOCcuirvse
the edge ofCLK1,
propagation delay of before the rising
tpd he
logic circuit. Combinational
a signal to Data
maximum time it takes for logic circuit
Tpc-Q is the transition occurs. B
propagate after the clock CLK2
the synchronous
maximum clock frequency of CLKI
Thus,
tset-up, tpdi tpc-Q:
system is determined by
-CLK
T 2 tset-up +tpdt tpc-Q
tpco)
tpd s Te- (tset-up+ satisfied for correct To+ (8 isnegative)
needsto be
The above condition
working of the system. between
combinational logic circuit
If there is no minimum clock period is
only
two stages then the CLK1
sum of set up timne and tpc-Q.
discussed earlier can be either
The clock skew
depending on routing direction
positive or negative CLK2
and position of the clock source.
synchronous circuit can be
The structure ofa typical
described by Fig. 2.9.5. Designing of such Fig. 2.9.7 : (a) and (b) Negative clock skew
synchronous circuit involves timing issues related Effect of positive skew :
logic circuit
to worst case delay of the combinational
Let us consider the circuit of Fig. 2.9.6, where th:
and delays involved with the flip flops.
Combiaiónal output of combinational logic circuit is connected to
ogic ccut
the data input of second flip flop. Therefore the
clock period must be high enough to keep the inpu
data valid of second flip flop for at least hold time.
Cock
That is the computation of combinational logt
Fig. 2.9.5 : Structure of a typical synchronous circuit circuit providing the correct data input to the
Positive clock skew : When the clock edge is second flip flop and delay through the first flip op
delayed by a positive 8at the other node than it is must be long enough to avoid race around condition
referred as positive clock skew. i.e. in the Fig. 2.9.6, (flip-flops are assumed to be positive edg
CLK2 is delayed by 8. triggered.
Data DQ Since the rising edge of CLK 2 is delayed by :
|Cloglc
ombinational
dircuit positive 8 , the time available for a signal
CLK2 propagate from first flip flop to second is inccrease
by 8 time.
cloci
-CK Therefore, the constraint on the minimum
period and hold timecan be derived as follows:
T + 8 2 tset-upt tpdt tpC-Q
CLK1
Te 2 tset-up+ tpdt tpc-Q -. skewY
The above equation infers that the positive cicu
the
CLK2.
essentially improving the performance of
Fig. 2.9.6: (a) and (b)
Positive clock skew
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 VLSIDesign &Technology (SPPU) 2-18 Digital Design and Issues
ve
Effect of negative skew: In Fig. 2.9.8, dark line indicates reference clock
rs waveform having clock period of Te. The dotted lines
Since the rising edge of CLK2 arrives earlier with at the edges depict the jitter of the signal. When
respect to the reference, the time available for a jitter is present, a transition can occur slightly early
signal to propagate from first flip flop to the next is or slightly late.
decreased by 6.(Refer Fig. 2.9.7) This can cause bit errors at the receiving end of the
In order to avoid race, we must ensure that the
system where a data signal is sampled by the clock
minimum delay through the first flip flop and the signal.
combinational logic is long enough that the inputs The clock period (Fig.2.9.8) starts at time t, and
to second flip flop are valid for a hold time after the
ends at time t, having a period of Te.
rising edge of CLK2.
The worst case situation would be when the jitter
Therefore, the constraint on the minimum clock causes the leading edge to be delayed making it
period and hold time can be derived as follows: start at time ta, while the next leading edge of the
Te -8 tset-upt tpdt tpc-Q next clock period occurs at t. This results in
reduction of clock period by 2. tjter.
Te 2 tset-upt tpdt tpc-Q tß.
Therefore,
Negative clock skew degrades performance, since T -2 tjtter 2 tset-upt tpdt tpcQ
the minimum clockperiod required is increased by 8.
T > tet-upt tpdt tpc-o + 2 titter
2.9.2 Clock Jitter
2.9.3 Combined Estimation of Clock Skew
and Jitter
University Questions
he Q. Explain the following clock Jitter. Let us say that, there is negative clock skew of 8
to between the two nodes A and B. Also, the two clocks
SPPU- Dec. 11. May 13, May 15, May 17,
che
Oct 19, 3 Marks experience ajitter of titar-(Refer Fig. 2.9.9).
out
Let us now determine the limitation imposed on the
Q. What is ClockJitter ? minimum clock period. The worst case would be the
SPPU- May 12, Dec. 12, 4 Marks
gic situation when the leading edge of current clock
the Clock jitter is the timing variation in a signal at a period on CLK1 is delayed at t, and the leading edge
lop given point in the chip. It can be regarded as the of next cycle of CLK2 happens early at tio(Refer
ion inaccuracy in the clock edge introduced by the clock Fig. 2.9.9).
dge signal generation circuit. Fig. 2.9,8 shows clock T: + 6 -[Link] 2tset-upt tpdt tpc-Q
jitter. T: tset-upt tpdt tpc-Q - + [Link]:
Data
Combinational Although the skew can provide a performance
logio circuit
to advantage, jitter always has a negative impact on
sed the minimum clock period.
CLK
For positive skew, the clock period constraint would
ock T be:
Te - 8- [Link] tsetr-upt tpdt tpc-.
Te 2 tset- upt tpdt tpc-Q +8 + [Link]

w is
cuit iter -fittor

Fig. 2.9.8: Clock jitter

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 (SPPU) tËt
VLSI Design &Technology
2.1

ToLK

CLK1

CLK2

t
TCLK +8
t
and negative skew
Fig. 2.9.9: Circuit with jitter
time of individual memory element. This is cal.
constraints on
set up time and hold time in poses clock skew.
the digital circuit that drives the input of flip flop. These delays slightly differ from one clock cydes
The circuit must be designed in such a way that the the other giving rise to clock jitter. Fig. 2.10.1:
clock
flip flop input arrives at least set up time before the illustrates clock skew, duty cycle and rise /
transition and does not change until hold time. If any of times.
these conditions are not satisfied the flip flop goes into
Rice time Falltime
metastatic state.
(t (t)
These restrictions impose limitations to maximum
operating frequency for a sequential circuit.
Clk
2.10 Clock Distribution

University Questions
Tnigh Tngn = Toy , .. Duty cyce =50%
Q. Explain techniques of clock distribution in detail.
SPPU - Dec. 13, Aug. 18, Dec. 19, 5 Marks
(a) Waveform showing delays
Q. What is the need of clock 2.1
distribution? Explain
techniques of clock distribution.
Reference
SPPU- Dec. 16, 6 Marks dock
Q. Writeshortnoteoncockdistributiontechnique.
End
SPPU - Dec. 18,7 Marks dock
Clock signals are very important in
for achieving digital
systems
synchronization.
clock signal is always of Therefore, stability of 'skew
prime
Real clock signals results in concern. (b) Waveform showing clock skew
skews when distributed
through the chip, have specified duty cycle which
Fig. 2.10.1
clocksignal
can also vary and have Skew is the spatial variation of the clock
i

Most of the clock noticeable and fall time,

rise
distributed through chip. When achipi tg
signals are applied to
storage elements spread
the propagation delay out in the entire IC. Since
several distributed to different location of
same, this would cause along various path are not the delayed. Fig.? 2.10.1(b) shows clockskew. ot
Signal
It is always clock
variation in the desirable to distribute
switching the chip area with a uniform delay.
 VLSI Design &Technology (SPPU) 2-20 Digital Design and Issues
2.10.1 Buffered clock network
In order to handle high fan-out loads, the clock
signals must be buffered in multiple stages.
Buffered clock network consists of a global clock
signal that is buffered at several points at
interconnects to boost the clock signal.
It is also important that every buffer stage drives
the same number of fan out gate so that clock delays
are always buffered. Fig. 2.10.2 shows the buffered
clock distribution tree.

Master Fig. 2.10.3 Grid type clock distribution

dock
2.10.3 Balanced Tree clock distribution
network

The balanced clock distribution networks are

Fig. 2.10.2: Buffered clock distribution tree
designed in such a way that they exhibit minimum
Buffers amplify degraded clock signals. skew thus enhancing the efficiency of the chip.
Due to the variation of the active device
In general, a balanced tree is designed such that it
characteristics buffers are a primary source of clock
transmits the clock signals to all the clock regions of
skew for a well balanced clock tree.
the die in both horizontal and vertical dimensions.
Buffers provide sufficient currents to drive the
Balanced tree network achieves routing in the
network capacitance and maintain high quality
clock waveforms. symmetric way such that the skew is zero.
The disadvantage with the use of these buffers is With identical buffer and interconnect segments,
this tree exhibits zero structural skew and good
such that they can introduce delay to the clock
signals on their path. tracking.
It is not possible to produce ideal zero skews
2.10.2 Grid type clock distribution network practically, but the block size is taken such that this
skew becomes insignificant.
The clock signals are routed through the branches,
in tree style dístribution network. But the high There are different types of balanced distribution
density complex designs typically have a large networks depending upon the type of arrangement
number of functional blocks resulting in large delays of the clock routing paths and they are, H-tree and X
tree.
and cdock skew.
This drawback of tree network is overcome by grid Symmetric H-tree clock distribution network:
connected
ype network which comprises of fully Fig. 2.10.4 shows general layout of H-tree clock
clock tracks in X andYdirections. distribution network.
Fig 2.10.3 shows the layout of the grid-type clock Input is applied at the centre of H and outputs are
distribution network. taken at the tips of the H.
Since the distance from the centre to all branch
points are same, the signalsdelay is same.

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