Unit-3

Basic Computer Organization and Design

 Instruction Set
• An instruction is a command given to the computer to perform a specified operation on a
given data.
• Instruction have two parts:
• Opcode (Operation code)- It specifies the task to be performed.
• Operand – It specifies the data to be operated on and is defined in various forms such as:
a. 8 bit or 16 bit data
b. 8 bit or 16 bit address
c. Internal register or a memory location
• The instruction set is the collection of instructions which the microprocessor is designed
to execute.
• The assembly language program comprises of the collection of instructions to perform a
certain operation.
• Different companies such as Intel, Motorola, etc. have different instruction set.
 Instruction

Type of operation size of Address

Data transfer/ Copy Instruction Zero-address instructions
Arithmetic Instruction One-address instructions
Logical Instruction
Two-address instructions
Branching Instruction
Three-address instructions
Machine control Instruction
instructions
• Zero-address instructions
They are simple and can be executed quickly since they do not require any operand fetching or
addressing. They also take up less memory space.
• One-address instructions
They allow for a wide range of addressing modes, making them more flexible than zero-address
instructions. They also require less memory space than two or three-address instructions.
• Two-address instructions
• They allow for more complex operations and can be more efficient than one-address instructions
since they allow for two operands to be processed in a single instruction. They also allow for a wide
range of addressing modes.
• Three-address instructions
They allow for even more complex operations and can be more efficient than two-address instructions
since they allow for three operands to be processed in a single instruction. They also allow for a wide
range of addressing modes.
INSTRUCTION FORMATS
• The most common fields found in instruction format are:-
• (1) An operation code field that specified the operation to be
performed
• (2) An address field that designates a memory address or a processor
registers.
• (3) A mode field that specifies the way the operand or the effective
address is determined. Computers may have instructions of several
different lengths containing varying number of addresses.
INSTRUCTION FORMATS
The number of address field in the instruction format of a computer
depends on the internal organization of its registers.

Most computers fall into one of three types of CPU organization.

(1) Single Accumulator organization ADD X AC (AC + M [×])

(2) General Register Organization ADD R1, R2, R3 (R1 @ R2 + R3)
(3) Stack Organization PUSH X
Zero – Address Instruction
• These instructions do not specify any operands or addresses. Instead, they operate
on data stored in registers or memory locations implicitly defined by the
instruction.
PUSH A TOP = A
• A stack organized computer
PUSH B TOP = B
does not use an address field
ADD TOP = A+B
for the instruction ADD and
PUSH C TOP = C
MUL.
PUSH D TOP = D
Expression: X = (A+B)*(C+D)
Postfixed : X = AB+CD+* ADD TOP = C+D
TOP means top of stack
M[X] is any memory location MUL TOP = (C+D)*(A+B)

POP X M[X] = TOP

One Address Instructions

• These instructions specify one operand or address, which typically

refers to a memory location or register. The instruction operates on the
contents of that operand, and the result may be stored in the same or a
different location. For example, a one-address instruction might load
the contents of a memory location into a register.
• This uses an implied ACCUMULATOR register for data manipulation.
One operand is in the accumulator and the other is in the register or
memory location. Implied means that the CPU already knows that one
operand is in the accumulator so there is no need to specify it.
 •Expression: X = (A+B)*(C+D)
One Address Instructions AC is accumulator
M[] is any memory location
M[T] is temporary location

LOAD A AC = M[A]

ADD B AC = AC + M[B]

STORE T M[T] = AC

LOAD C AC = M[C]

ADD D AC = AC + M[D]

MUL T AC = AC * M[T]

STORE X M[X] = AC
Two Address Instructions

• These instructions specify two operands or addresses, which may be

memory locations or registers. The instruction operates on the contents of
both operands, and the result may be stored in the same or a different
location. For example, a two-address instruction might add the contents of
two registers together and store the result in one of the registers.
• This is common in commercial computers. Here two addresses can be
specified in the instruction. Unlike earlier in one address instruction, the
result was stored in the accumulator, here the result can be stored at different
locations rather than just accumulators, but require more number of bit to
represent the address.
 •Here destination address can also contain an operand.
Two Address •Expression: X = (A+B)*(C+D)
Instructions R1, R2 are registers
M[] is any memory location

MOV R1, A R1 = M[A]

ADD R1, B R1 = R1 + M[B]

MOV R2, C R2 = M[C]

ADD R2, D R2 = R2 + M[D]

MUL R1, R2 R1 = R1 * R2

MOV X, R1 M[X] = R1
Three Address Instructions

• These instructions specify three operands or addresses, which may be memory

locations or registers. The instruction operates on the contents of all three operands,
and the result may be stored in the same or a different location. For example, a
three-address instruction might multiply the contents of two registers together and
add the contents of a third register, storing the result in a fourth register.
• This has three address fields to specify a register or a memory location. Programs
created are much short in size but number of bits per instruction increases. These
instructions make the creation of the program much easier but it does not mean that
program will run much faster because now instructions only contain more
information but each micro-operation (changing the content of the register, loading
address in the address bus etc.) will be performed in one cycle only.
Three Address •Expression: X = (A+B)*(C+D)
Instructions R1, R2 are registers
M[] is any memory location

ADD R1, A, B R1 = M[A] + M[B]

ADD R2, C, D R2 = M[C] + M[D]

MUL X, R1, R2 M[X] = R1 * R2

Advantages of Zero, One, Two Three-Address
Instructions
• Zero-address instructions
• Simple and can be executed quickly since they do not require any operand fetching or addressing.
• Occupy less memory space.
• One-address instructions
• Allows a wide range of addressing modes, making them more flexible than zero-address instructions.
• Require less memory space than two or three-address instructions.
• Two-address instructions
• Allow for more complex operations and is more efficient than one-address instructions since they
allow for two operands to be processed in a single instruction.
• They also allow for a wide range of addressing modes.
• Three-address instructions
• Allows more complex operations and is more efficient than two-address instructions since they
allow for three operands to be processed in a single instruction.
• They also allow for a wide range of addressing modes.
Disadvantages
• Zero-address instructions
• They can be limited in their functionality and do not allow for much flexibility in terms of addressing
modes or operand types.
• One-address instructions
• They can be slower to execute since they require operand fetching and addressing.
• Two-address instructions
• They require more memory space than one-address instructions and can be slower to execute since
they require operand fetching and addressing.
• Three-address instructions
• They require even more memory space than two-address instructions and can be slower to execute
since they require operand fetching and addressing.
• Overall, the choice of instruction format depends on the specific requirements of the computer
architecture and the trade-offs between code size, execution time, and flexibility
Communication inside a computer..
• A computer program consists of both instructions and
data. The program is fed into the computer through
the input unit and stored in the memory.
• In order to execute the program, the instructions have
to be fetched from memory one by one.
• This fetching of instructions is done by the control
unit.
• After an instruction is fetched, the control unit
decodes the instruction.
• According to the instruction, the control unit issues
control signals to other units.
Communication inside a computer..
o After an instruction is executed, the result of the
instruction is stored in memory or stored
temporarily in the control unit or ALU, so that
this can be used by the next instruction.
o The results of a program are taken out of the
computer through the output unit.
o The control unit, ALU and registers are
collectively known as Central Processing Unit
(CPU)
Instruction cycle
• Instructions are fetched and executed by the
control unit one by one. The sequences involved
for the fetch of one instruction and its execution
are known as instruction cycle.
 Microprocessor Communication and Bus timings
• A program constitutes a set of Instructions. The
processor fetches one instruction from the memory at
a time and executes it.
• The necessary steps that a processor carries out to
fetch an instruction and data from memory and I/O
devices, constitutes an instruction cycle.
Fetch cycle Processor fetches opcode from memory

Execute cycle Processor gets data from memory or I/O devices and
perform specific operation

Instruction cycle Fetch cycle + Execution cycle

•
 Memory
Instruction MDR Data Bus
Register
Memory
Instruction Address
Program Bus
Decoder MAR
Counter
Control

Flow of Instruction code

Send address Memory gets opcode Transfer opcode to

to memory from memory location processor
Clock

Time
A Typical Fetch Cycle
• Execute Operation
• After the instruction is being decoded, execution
begins.
• If the operand is in the GPR (one byte instruction),
then execution is immediately performed and the time
taken is one clock cycle.
• If the instruction contains data or memory address
(two or three byte instruction).
• Processor performs read operation and gets data from
the memory.
• In some instruction write operation is performed.
Instruction Cycle
Instruction Cycle Steps
Computer Registers
• A register is a very small amount of very fast memory that is built
into the CPU (central processing unit) in order to speed up its
operations by providing quick access to commonly used values.
• Small, permanent storage locations within the CPU used for a
particular purpose
• Manipulated directly by the Control Unit
• Wired for specific function
• Size in bits or bytes (not MB like memory)
• Can hold data, an address or an instruction
• Scratchpad for currently executing program
• Holds data needed quickly or frequently
• Stores information about status of CPU and currently executing program
• Address of next program instruction
• Registers are normally measured by the number of bits they can hold.
• Registers are used to store data temporarily during the execution of a
program.
• Some of the registers are accessible to the user through instructions.
• Data and instructions must be put into the system. So we need registers
for this.
General Purpose Registers:
• There are four General Purpose Registers named as follows:
• 1. AX (Accumulator Register): is commonly used for arithmetic &
logic data transfer.
• 2. BX (Base Address Register): is used to save the address of memory
location from where data is being read from or written to.
• 3. CX (Count Register): keeps record of iterations while a LOOP
instruction is running.
• 4. DX (Data Register): holds data of the instruction currently being
executed.
Pointer Registers:
• There are three pointer registers that are used to point towards a
particular memory address.
• BP (Base Pointer): points to the base element of the stack.
• SP (Stack Pointer): always points to the top element of the stack.
• IP (Instruction Pointer): stores the address of the next instruction to be
executed.
• Index Registers: An index register is a crucial component in a computer's
CPU that facilitates efficient data management and quick access to memory
locations. By holding offsets, it streamlines the process of calculating
addresses, enhancing program execution.
• Most commonly, an index register holds the current offset of a memory
location, with another register holding the base address, so the combination
of the two registers creates a completed memory address.
• There are two sets of index registers:
• SI (Source Index): used as source index for string operations.
• DI (Destination Index): used as destination index for string operations.
• Segment Registers: Segments are specific areas for containing data,
code and stack.
• There are three main segments:
• Code Segment: It contains all the instructions to be executed. CS
register stores the starting address of the code segment.
• Data Segment: It contains data, constants and work areas. DS register
stores the starting address of the data segment.
• Stack Segment: It contains data and return addresses of procedures or
subroutines. The Stack Segment register or SS register stores the
starting address of the stack.
Flag Registers:

• The FLAG register is the status register that contains the current state of a
CPU.
• The common flag bits are:
• Overflow Flag (OF)
• Direction Flag (DF)
• Interrupt Flag (IF)
• Trap Flag (TF)
• Sign Flag (SF)
• Auxiliary Carry Flag (AF)
• Parity Flag (PF)
• Carry Flag (CF)
• Zero Flag (ZF)
• Overflow Flag: The overflow flag is set when the arithmetic result is too
large to fit in the allocated space. the overflow flag (sometimes called the V
flag) is usually a single bit in a system status register used to indicate when
an arithmetic overflow has occurred in an operation, indicating that the
signed two's-complement result would not fit in the number of bits used for
the result.
• Direction Flag: The direction flag (DF) is a CPU flag that controls the
direction of string processing in CPUs.
• If directional flag is set (1), then access the string data from higher memory
location towards lower memory location. If directional flag is reset (0), then
access the string data from lower memory location towards higher memory
location.
• Interrupt Flag: This flag is for interrupts. If interrupt flag is set (1), the
microprocessor will recognize interrupt requests from the peripherals. If
interrupt flag is reset (0), the microprocessor will not recognize any interrupt
requests and will ignore them.
• Trap Flag: This flag is used for on-chip debugging. If trap flag is set (1),
the CPU automatically generates an internal interrupt after each instruction,
allowing a program to be inspected as it executes instruction by instruction.
If trap flag is reset (0), no debugging is performed.
• Flag Register
– 8 bit register – shows the status of the microprocessor before/after
an operation
– S (sign flag), Z (zero flag), AC (auxillary carry flag), P (parity flag) &
CY (carry flag)

D7 D6 D5 D4 D3 D2 D1 D0

S Z X AC X P X CY

– Sign Flag
• Used for indicating the sign of the data in the accumulator
• The sign flag is set if negative (1 – negative)
• The sign flag is reset if positive (0 –positive)
• Zero Flag
– Is set if result obtained after an operation is 0

10110011
+ 01001101

1
• Carry Flag 00000000
– Is set if there is a carry or borrow from arithmetic
operation

1011 0101 1011 0101

+ 0110 - 1100 1100
1100
Carry 1 0010 0001 Borrow 1 1110 1001
 • Auxillary Carry Flag
– Is set if there is a carry out of bit 3
• Auxiliary carry – 1; if there is a carry from D3 bit to D4
bit.
– 0; o/w

• Parity Flag
– Is set if parity is even
– Is cleared if parity is odd

• Parity flag – 1; if the no. of binary “one” is even in A.

0; if the no. of binary “one” is odd in A.
ADDRESSING MODES
• Instruction has opcode and operand. There are
different techniques to specify operand in an
instruction. These techniques are called as addressing
modes.
• Direct addressing mode
• Immediate addressing mode
• Register addressing mode
• Register indirect addressing mode(Indirect addressing
mode)
• Implicit/Implied addressing mode
Direct addressing mode
• Address of the operand (data) is given in the
instruction itself.
• Example-

LDA 6000H Load the accumulator with the contents of

the memory location 6000H
STA 2400H Store the contents of the accumulator in the
memory location 2400H
IN 02 The data available on the 8 bit address of the
input port is moved to the accumulator
Immediate addressing mode
• In this addressing mode the operand (data) is specified
within the instruction itself.
• Example

MVI A,05 Move the data 05 into the accumulator

ADI 06 Add 06 to the content of the accumulator

LXI H, 2500 2500 is 16 bit data and is loaded into H-L pair
Register addressing mode
• Operand is one of the GPR or the accumulator.
• Opcode specifies the operation to be performed and
address of the registers.
• Operation takes place between registers.
• Example-
MOV A, B Move the content of the register B to register A

ADD B Add the content of the register B to the content of

the register A
Register Indirect addressing mode
• Address of the data is present as the content of the
another register pair.
• Example
LXI H, 2500H Load H-L pair with 2500 H

MOV A,M Move the content of the memory location whose address is
in H-L pair to the accumulator
HLT Halt
• Indirect Addressing Mode
• Using data in memory directly (without loading
first into a Microprocessor’s register) is called
Indirect Addressing.

• Indirect addressing uses the data in a register pair

as a 16-bit address to identify the memory location
being accessed.
– The HL register pair is always used in conjunction with
the memory register “M”.
– The BC and DE register pairs can be used to load
data into the Accumultor using indirect addressing.
Implicit/ Implied addressing mode
• In this type of instruction, operand is the content of
the accumulator.
• No data, address of data, register are present in the
instruction.
• Example
CMA Complement the content of the accumulator

RAL Rotate accumulator left through carry

RAR Rotate accumulator right through carry

RLC Rotate accumulator left

Interrupts
• 1. Hardware Interrupts
• If a processor receives the interrupt request from an external I/O device it is termed as a hardware
interrupt. Hardware interrupts are further divided into maskable and non-maskable interrupt.
• Maskable Interrupt: The hardware interrupt that can be ignored or delayed for some time if the
processor is executing a program with higher priority are termed as maskable interrupts.
• Non-Maskable Interrupt: The hardware interrupts that can neither be ignored nor delayed and must
immediately be serviced by the processor are termed as non-maskable interrupts.
• 2. Software Interrupts
• The software interrupts are the interrupts that occur when a condition is met or a system call occurs.
For example, a system call is a software interrupt that requests a service from the operating system,
such as opening a file, printing a message, or allocating memory.
• Interrupt Cycle
• A normal instruction cycle starts with the instruction fetch and execute. But, to accommodate the
occurrence of the interrupts while normal processing of the instructions, the interrupt cycle is added
to the normal instruction cycle as shown in the figure below.
Interrupts in instruction cycle
Contd.
• After the execution of the current instruction, the processor
verifies the interrupt signal to check whether any interrupt is
pending. If no interrupt is pending then the processor proceeds to
fetch the next instruction in the sequence.
• If the processor finds the pending interrupts, it suspends the
execution of the current program by saving the address of the
next instruction that has to be executed and it updates the
program counter with the starting address of the interrupt
service routine to service the occurred interrupt.
• After the interrupt is serviced completely the processor resumes
the execution of the program it has suspended.
Enabling and Disabling Interrupts in Computer
Architecture
• Modern computers have facilities to enable or disable interrupts. A
programmer must have control over the events during the execution of the
program.
• For example, consider the situation, that a particular sequence of instructions
must be executed without any interruption. As it may happen that the
execution of the interrupt service routine may change the data used by the
sequence of instruction. So the programmer must have the facility to enable
and disable interrupt in order to control the events during the execution of
the program.
• One can enable and disable the interrupts on both ends i.e. either at the
processor end or at the I/O device end. With this facility, if the interrupts are
enabled or disabled at the processor end the processor can accept or reject
the interrupt request. And if the I/O devices are allowed to enable or disable
interrupts at their end then either I/O devices are allowed to raise an
interrupt request or prevented from raising an interrupt request.
Contd.
• To enable or disable interrupt at the processor end, one bit of its
status register i.e. IE (Interrupt Enable) is used. When the IE flag is
set to 1 the processor accepts the occurred interrupts. IF IE flag is
set to 0 processor ignore the requested interrupts.
• To enable and disable interrupts at the I/O device end, the control
register present at the interface of the I/O device is used. One bit
of this control register is used to regulate the enabling and
disabling of interrupts for the I/O device end.
• 2x86 (CISC) processor
• ARM (RISC) processor
• x86 and ARM instructions
• Intel x86 v/s ARM
• Intel x86:
• is a generic name given to Intel processors beginning with the 8086 processor
released in 1978.
• Since the earliest machines were programmed in assembly language and
memory was slow and expensive, the CISC was implemented in computers.
• Intel x86 uses CISC (Complex Instruction Set Computer) and are chips that are
easy to program and which make efficient use of memory.
• ARM:
• ARM was first known as Acron RISC Machine, but now its known as Advanced
RISC Machine. ARM was developed in late 70s and 80s.
• This RISC Architecture utilizes a small, highly-optimized set of instructions,
rather than a more specialized set of instructions often found in other types of
architectures.
Intel x86 (CISC) .
• Processor
• x86 is a 16, 32bit CISC processor.
• It has limited number of registers.
• Load and store are incorporated in the instructions itself.
• It has complex instructions.
• Efficiency when compared to ARM is less.
• Different machine programs can be executed on CISC machine.
ARM (RISC) processor
• ARM is a 32 bit RICS processor.
It has high code density.
• Load and store architecture.
• 16 bit THUMB instructions.
• Uses simple instructions.
• Conditional execution.
• Inline barrel shifter.
x86 and ARM Instructions(comparison)
• Intel x86:
• If any one of the operand needs to be used for another computation, the
processors must re-load the data from memory into the register. The
length of the code is relatively short.
Very little RAM is required to store instructions.
It requires more transistors, more hardware space, therefore power
consumption is more.

• ARM: Operand will remain in the register until another value is loaded in
its place. More number of code lines. RAM used is more. It requires less
transistors so less hardware space therefore power consumption is less
• Intel x86 v/s ARM Intel x86:
• More emphasis on speed and performance than power
consumption.
• Is compatible with most of the operating systems like Windows 7,
Windows XP, LINUX, Android, Windows Vista, etc.. And these
consumes loads of power.
• Intel x86 is used in laptops, desktops and servers.
• ARM: Focuses mainly on low power consumption.
• It supports LINUX and Android.
• It is used in all smart phones, iPads tablets etc.
References(processor 86 and ARM)
• [1] Emily Blem and Jaikrishnan Menon A Detailed Analysis of Contemporary ARM and
x86 Architectures University of Wisconsin – Madison
• [2] Mjfern (December 21, 2012) The End of x86? An Update (Online) available from<
[Link] >[22nd February 2013]
• [3] TECH POWER UP (1st December 2011) The Move Away From x86 To ARM Processors
On The Desktop To Start Soon – Survey (Online) available from<
[Link]
[Link]> [22nd February 2013]
• [4] Rachel Courtland (May 2012) The Battle Between ARM and Intel Gets Real (Online)
available from<
[Link]
-gets-real> [23rd February 2013]
• [5] Van’s Hardware Journal (n.d) Mirror The Coming War ARM versus x86 (Online)
available from<
[Link] > [23rd
February 2013]