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Digital Circuits Assignment 4

The document contains an assignment for a Digital Circuits course at IIT Kharagpur, consisting of 15 multiple-choice questions focused on Boolean expressions, logic gates, and circuit implementations. Each question includes the correct answer and a detailed solution explaining the reasoning behind it. The assignment aims to assess students' understanding of digital circuit concepts and their applications.

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0% found this document useful (0 votes)
86 views14 pages

Digital Circuits Assignment 4

The document contains an assignment for a Digital Circuits course at IIT Kharagpur, consisting of 15 multiple-choice questions focused on Boolean expressions, logic gates, and circuit implementations. Each question includes the correct answer and a detailed solution explaining the reasoning behind it. The assignment aims to assess students' understanding of digital circuit concepts and their applications.

Uploaded by

01abhinay11
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

NPTEL Online Certification Courses

Indian Institute of Technology Kharagpur

Digital Circuits
Assignment- Week 4
TYPE OF QUESTION: MCQ
Number of questions: 15 Total mark: 15 X 1 = 15

QUESTION 1:

The boolean expression 𝐴̅ 𝐵 + 𝐴𝐵̅ + 𝐴𝐵 is equivalent to?

a) 𝐴+𝐵
b) 𝐴̅ . 𝐵
c) ̅̅̅̅̅̅̅̅
𝐴+𝐵
d) 𝐴.𝐵

Correct Answer: A

Detailed Solution:

𝐹 = 𝐴̅ 𝐵 + 𝐴 𝐵̅ + 𝐴𝐵

= 𝐵 (𝐴 + 𝐴̅ ) + 𝐴 𝐵̅ = 𝐴 ( 𝐵 + 𝐵̅ ) + 𝐴̅ 𝐵

= 𝐵 + 𝐴 𝐵̅ = 𝐴 + 𝐴̅ 𝐵

= (𝐵 + 𝐵̅ )(𝐴 + 𝐵) = (𝐴 + 𝐴̅ )(𝐴 + 𝐵)
= (𝐴 + 𝐵) = (𝐴 + 𝐵)

Question 2:

The input to a logic gate is A = 1100 and B = 1010. What will be the output, if the logic gate
is NAND gate?
a) 1101
b) 0111
c) 0110
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d) 1011

Correct Answer: b

Detailed Solution:

We are given inputs:

 A=1100
 B=1010
 The logic gate is a NAND gate.

Question 3

The combinational circuit implementation of the following boolean function


F(A,B,C) = Σ(1,2,4,7)
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(a)

(b) A

B
C

A
(c)
B

(d)

Correct Answer: (a) A BC

Detailed Solution:
F(A,B,C) = Σ(1,2,4,7)
=(ABC+ABC+ ABC+ABC)
=(AB+AB)C+ (AB+AB)C
=(AB+AB)C+ (AB+AB)C= (AB+AB)  C=A B C

Question 4:

For following logic diagram which expression is true?


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̅̅̅̅̅̅̅̅̅̅̅̅
A) ̅̅̅̅
𝐴𝐵 + 𝐴𝐵
B) ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅ 𝐵̅ . 𝐴. 𝐵
𝐴.
C) ̅̅̅̅̅
𝐴𝐵. 𝐴𝐵
D) (A.B) (𝐴.̅̅̅̅̅̅̅
𝐵)

Correct Answer: B

Detailed Solution:

QUESTION 5:
The output of the logic gate in the figure below is :

(A) 0
(B) 1
(C) A
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(D) A̅

Corrected Answer: d

Detailed Solution:

1) If B is always LOW, the OUTPUT is the inverted value of the INPUT A, i.e A’
2) The OUTPUT is LOW when both the inputs are different.
3) The OUTPUT is HIGH when both the inputs are the SAME.

QUESTION 6:
The number of inputs and outputs in a half adder circuit are?
a) 2 and 1
b) 4 and 2
c) 1 and 1
d) 2 and 2

Correct Answer: d

Detailed Solution:

A half adder is a combinational circuit that performs the addition of two single-bit binary
numbers.

 2 inputs:
o A (first bit)
o B (second bit)

 2 outputs:
o Sum (S): XOR of A and B

S=A⊕B

o Carry (C): AND of A and B

C=A⋅B

 Number of inputs: 2
 Number of outputs: 2
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QUESTION 7:

The output Y in the circuit below is always ‘1’ when

a) Two or more of the inputs P, Q, R are ‘0’


b) Two or more of the inputs P, Q, R are ‘1’
c) Any odd number of the inputs P,Q, R is ‘0’
d) Any odd number of the inputs P,Q, R is ‘1’

Correct Answer: b

Detailed Solution:
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If any two or more inputs are ‘1’ , then output will be 1.

QUESTION 8:
In the circuit shown in the figure, if C = 0, the expression for Y is

a) Y = AB’ + A’B
b) Y=A+B
c) Y = A’ + B’
d) Y = AB

Correct Answer: a

Detailed Solution:
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NPTEL Online Certification Courses
Indian Institute of Technology Kharagpur

QUESTION 9:
In the figure shown, the output Y is required to be Y = 𝐴 . 𝐵 + 𝐶̅ 𝐷
̅ . The gates G1 and G2
must be respectively?

A) NOR, OR
B) OR, NAND
C) NAND, OR
D) AND, NAND

Correct Answer: A

Detailed Solution:

QUESTION 10:
What is the primary cause of glitches in digital circuits?
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A) Manufacturing defects in the integrated circuits.

B) Variations in gate delays due to process variations.

C) Incorrect connections in the circuit layout.

D) Inadequate power supply voltage.

Correct Answer: B

Detailed Solution:

Glitches in digital circuits are primarily caused by variations in gate delays due to process
variations in integrated circuits. These variations can lead to differences in signal arrival
times, causing temporary and unwanted changes in the output signal. Glitches are transient
errors that occur due to the non-ideal behavior of the digital components, such as gates and
flip-flops, in the presence of varying delays.

QUESTION 11:
The output Y of the logic circuit given below is:

(A) 1
(B) 0
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(C) X
(D) X̅

Corrected Answer: A

Detailed Solution:

QUESTION 12:

Identify the logical operations performed by the given circuits?


a) a) AND gate , b) OR gate
b) a)NAND gate , b) OR gate
c) a) OR gate , b) AND gate
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d) a) NAND gate , b) NOR gate


Correct Answer: A

Detailed Solution:

𝐴 . 𝐵 ; 𝑌 = 𝑋̅ = ̅̅̅̅̅̅
𝑋 = ̅̅̅̅̅̅ 𝐴.𝐵 = 𝐴.𝐵 ( AND gate)

𝑃 = 𝐴̅ ; 𝑄 = 𝐵̅ ; 𝑃 . 𝑄 = ̅̅̅̅̅̅̅
𝑌 = ̅̅̅̅̅̅ ̅̅̅
𝐴 . 𝐵̅ = A + B (OR gate)

QUESTION 13:
The Boolean function Y = AB + CD is to be realized using only 2-input NAND gates. The
minimum number of gates required is:

a) 2

b) 3

c) 4

d) 5

Correct Answer: b

Detailed Solution:

QUESTION 14:
Which of the following Boolean Expressions correctly represents the relation between P, Q,
R and Y ?
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A) Y = ( P OR Q) XOR R
B) Y = ( P AND Q) XOR R
C) Y = ( P NOR Q) XOR R
D) Y = ( P XOR Q) XOR R

Correct Answer: (D)

Detailed Solution:

QUESTION 15:

Which of the following terms refers to the maximum amount of unwanted voltage (noise)
that can be present at the input of a digital logic gate without causing a change in its output
logic level?

A) Noise Margin
B) Noise Immunity
C) White Noise
D) Signal-to-Noise Ratio
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Correct Answer: A

Detailed Solution

Noise Margin is the measure of how much noise voltage a digital logic circuit can tolerate at
its input without changing the intended output. It defines the safety buffer for logical high
and low levels.

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