Sandip Foundation’s

Sandip Institute of Engineering and Management,

Mahiravani, Trimbak Road, Nashik- 422 213

Department: Electronics and Telecommunication Engineering. Academic Year: 2025-26

Unit-III

Subject- Digital Electronics Subject Code- PCC-203-ETC SEM-III

Q-Define State, State Table, State Diagram and State assignment?

Ans: 1. State

A state is a specific condition or situation of a system at a particular time, defined by the values
of its internal memory elements (e.g., flip-flops).
In the context of a finite state machine (FSM), a state represents a snapshot of the system's
history and determines how the system behaves in response to inputs.

🔹 Example: In a traffic light controller, the states might be:

 Green Light
 Yellow Light
 Red Light

2. State Table

A state table is a tabular representation of a finite state machine's behavior. It lists:

 The current state

 The input(s)
 The corresponding next state
 The output(s) (if any)

It helps in designing and analyzing sequential circuits.

3. State Diagram

A state diagram is a graphical representation of a state machine. It shows:

  States as circles/nodes
 Transitions as arrows between states
 Input/output labels on the transitions

It provides an intuitive way to understand how the system moves from one state to another.

State Assignment

State assignment is the process of assigning binary codes to the symbolic states in a state
machine so they can be implemented using digital logic (flip-flops and gates).
Since digital circuits only understand binary values, symbolic states like A, B, C must be
represented as binary patterns.

Q- What is FSM? Compare Moore & Mealy FSM?

Ans:
A synchronous sequential circuit is also called as Finite State Machine FSMFSM, if it has finite
number of states. There are two types of FSMs.

 Mealy State Machine

 Moore State Machine
Now, let us discuss about these two state machines one by one.

Mealy State Machine

A Finite State Machine is said to be Mealy state machine, if outputs depend on both present
inputs & present states. The block diagram of Mealy state machine is shown in the following
figure.

As shown in figure, there are two parts present in Mealy state machine. Those are
combinational logic and memory. Memory is useful to provide some or part of previous
outputs present states as inputs of combinational logic.
So, based on the present inputs and present states, the Mealy state machine produces outputs.
Therefore, the outputs will be valid only at positive or negative transition of the clock signal.
The state diagram of Mealy state machine is shown in the following figure.
In the above figure, there are three states, namely A, B & C. These states are labelled inside the
circles & each circle corresponds to one state. Transitions between these states are represented
with directed lines. Here, 0 / 0, 1 / 0 & 1 / 1 denotes input / output. In the above figure, there are
two transitions from each state based on the value of input, x.
In general, the number of states required in Mealy state machine is less than or equal to the
number of states required in Moore state machine. There is an equivalent Moore state machine
for each Mealy state machine.

Moore State Machine

A Finite State Machine is said to be Moore state machine, if outputs depend only on present
states. The block diagram of Moore state machine is shown in the following figure.

As shown in figure, there are two parts present in Moore state machine. Those are
combinational logic and memory. In this case, the present inputs and present states determine
the next states. So, based on next states, Moore state machine produces the outputs. Therefore,
the outputs will be valid only after transition of the state.
The state diagram of Moore state machine is shown in the following figure.
In the above figure, there are four states, namely A, B, C & D. These states and the respective
outputs are labelled inside the circles. Here, only the input value is labeled on each transition.
In the above figure, there are two transitions from each state based on the value of input, x.
In general, the number of states required in Moore state machine is more than or equal to the
number of states required in Mealy state machine. There is an equivalent Mealy state machine
for each Moore state machine. So, based on the requirement we can use one of them.

Difference Between Mealy and Moore FSM

S. No. Moore FSM Mealy FSM

The Final output depends on the present
The Final output depends only on the
1 state of memory elements and the external
present state of memory elements
inputs
The output changes only after the The output can changes in between the
2
active clock edge clock edges if the external inputs change.
The implementation of a logic The implementation of the same logic
3 function needs more number of states function requires less number of states
than Mealy FSM than Moore FSM

Q-Explain how output generation differs in Moore and Mealy machines?

Ans: In Moore machines, the output depends only on the current state, making the output
change at the clock edge and providing a stable but delayed response. In Mealy machines, the
output depends on both the current state and the current input, leading to a more immediate
output but potentially introducing glitches as the output can change whenever the input
changes.

The key difference between Moore and Mealy machines lies in how and when outputs are
generated:

Moore Machine:

 Output depends only on the current state.

 The output is associated with states, not transitions.
 Output changes only when the state changes.

Mealy Machine:

 Output depends on both the current state and the current input.
 The output is associated with transitions, not just states.
 Output can change in the middle of a state if the input changes, allowing for faster
response.

Q- Explain the concept of state minimization in Moore and Mealy machines?

Ans: State minimization in both Moore and Mealy machines is the process of reducing the
number of states in a finite state machine (FSM) without changing its overall behavior, resulting
in a more efficient design that uses fewer flip-flops and potentially less hardware. States are
considered equivalent and can be merged if they produce the same outputs for all input
sequences and have equivalent next states for each corresponding input.
Moore Machines:

Output Dependency: In a Moore machine, the output is solely a function of the current state.

Minimization Strategy: Identify equivalent states: States are equivalent if they have the same
output and their next states are also equivalent (meaning they will produce the same outputs
for the rest of the input sequence).
Merge states: Combine all equivalent states into a single state in the minimized machine.

Mealy Machines:

Output Dependency:In a Mealy machine, the output is a function of both the current state and
the input.
Minimization Strategy:Identify non-equivalent outputs: The first step is to determine if a
state produces multiple different outputs for different inputs.
Split states based on output: If a state produces different outputs for different inputs, it needs
to be split into multiple states, each representing a unique output.
Merge equivalent states: Similar to Moore machines, equivalent states that produce the same
outputs and have equivalent successors are merged.
Q- Why is state reduction important in designing FSMs?
Ans: State reduction is important in FSM design to minimize hardware, reduce implementation
costs, and simplify verification and testing by eliminating redundant states that do not alter the
FSM's overall input-output behavior. Fewer states require fewer flip-flops for state assignment
and less combinational logic, leading to more efficient, less complex, and more maintainable
digital circuits.

Q-Reduce the number of states in the following state table and tabulate the
reduced state table?

Ans:
Q-

Ans:
Q-Reduce the number of states in the following state diagram and draw the
reduced state diagram?

Ans: First Draw the State table from the state diagram:
Q- Design a Synchronous Sequential Circuit for the following State diagram using JK Flip-
flops?
Q-Design a Synchronous Sequential Circuit for the following State diagram using RS Flip-
flops?

Ans: Let us assume that a-001, b-010, c-011, d- 100, e-101

Q-

Ans:

Q- Write Short notes on Sequence Detector?

Ans: A sequence detector is a sequential state machine that takes an input string of bits and
generates an output 1 whenever the target sequence has been detected.
A sequence detector is the digital circuit that detects some input signal sequences from a set of
the binary data. One can determine whether incoming bits are equal to a pre-stored sequence.
Sequence detectors have applications in digital electronics and telecommunications. This
technology can be applied in the area of bioinformatics, by detecting specific nucleotide
sequences in DNA or RNA, thus showing its applicability across various fields.
Sequence detector is of two types:
1. Overlapping
2. Non-Overlapping
In an overlapping sequence detector, the last bit of one sequence becomes the first bit of the
next sequence. However, in a non-overlapping sequence detector, the last bit of one sequence
does not become the first bit of the next sequence.
Examples
For non overlapping case
Input : 0110101011001
Output:0000100010000
For overlapping case
Input :0110101011001
Output:0000101010000
Q-Design and implement circuit using D flip flop to detect the following binary sequence
110 using Moore FSM.

Ans: State Diagram for sequence detector to detect the sequence 110 using Moore FSM is
given below:

Let us assume that S0=00, S1=01, S2=10 & S3=11

State Table for the above state diagram is:

Present State Next State O/P FF-I/Ps

Q1 Q2 x Q1 Q2 Z D1 D2
0 0 0 0 0 0 0 0
0 0 1 0 1 0 0 1
0 1 0 0 0 0 0 0
0 1 1 1 0 0 1 0
1 0 0 1 1 1 1 1
1 0 1 1 0 0 1 0
1 1 0 0 0 0 0 0
1 1 1 0 1 0 0 1

K-Map for D1:

Q2 x 00 01 11 10
Q1 0
1

1 1 1
D1= Q1Q2’ + Q1’Q2x

K-Map for D2:

Q2 x 00 01 11 10
Q1 0
1

1 1 1

D2= Q1’Q2’x + Q1Q2’x’ + Q1Q2x

= (Q1’Q2’ + Q1Q2)x + Q1Q2’x’
= (Q1ΘQ2) + Q1Q2’x’

K-Map for Z:

Q2 x 00 01 11 10
Q1 0

1 1

Z = Q1Q2’x’

Circuit Diagram:
Q-Design and implement circuit using D flip flop to detect the following binary sequence
110 using Mealy FSM.

Ans: State Diagram for sequence detector to detect the sequence 110 using Mealy FSM is
given below:

Let us assume that S0=00, S1=01, S2=10

State Table for the above state diagram is:

Present State Next State O/P FF-I/Ps

Q1 Q2 x Q1 Q2 Z D1 D2
0 0 0 0 0 0 0 0
0 0 1 0 1 0 0 1
0 1 0 0 0 0 0 0
0 1 1 1 0 0 1 0
1 0 0 0 0 1 0 0
1 0 1 1 0 0 1 0

K-Map for D1:

Q2 x 00 01 11 10
Q1 0
1

1 1 X X

D1= Q1x + Q2x

K-Map for D2:
Q2 x 00 01 11 10
Q1 0
1

1 X X

D2= Q1’Q2’x

K-Map for Z:

Q2 x 00 01 11 10
Q1 0

1 1 X X

Z = Q1x’

Circuit Diagram:
Q- Design a sequence detector to detect a sequence 1101 using D FF (Use Mealy machine).

Ans: : State Diagram for sequence detector to detect the sequence 1101 using Mealy FSM is
given below:

Let us assume that A=00, B=01, C=10, D=11

State Table for the above State diagram with state assignment are:

Present State Next State O/P FF-I/Ps

Q1 Q2 x Q1 Q2 Z D1 D2
0 0 0 0 0 0 0 0
0 0 1 0 1 0 0 1
0 1 0 0 0 0 0 0
0 1 1 1 0 0 1 0
1 0 0 1 1 0 1 1
1 0 1 1 0 0 1 0
1 1 0 0 0 0 0 0
1 1 1 0 1 1 0 1

K-Map for D1:

Q2 x 00 01 11 10
Q1 0
1

1 1 1

D1= Q1Q2’ + Q1’Q2x

K-Map for D2:
Q2 x 00 01 11 10
Q1 0
1

1 1 1

D2= Q1’Q2’x + Q1Q2’x’ + Q1Q2x

= (Q1’Q2’ + Q1Q2)x + Q1Q2’x’
= (Q1ΘQ2) + Q1Q2’x’

K-Map for Z:

Q2 x 00 01 11 10
Q1 0

1 1

Z = Q1Q2x

Circuit Diagram:

Q- Design a sequence detector to detect a sequence 1001 using T-FF (Use Moore machine).
Ans: Do it yourself…..

Q- Write short notes on ASM Chart?

ASM Chart :
An Algorithmic State Machine (ASM) chart is a specialized flowchart used in digital logic
design to represent the sequential operations of a digital system, particularly finite state
machines (FSMs). It provides a structured and clear way to define the control flow and
operations within a sequential circuit.

The ASM chart is composed of three basic elements, which are

 State box
 Decision box
 Conditional Output box
State box :

State box
 A state in the control sequence is described by State box.
 The shape of the state box is rectangular in which register operations or output signal
names can be specified.
 The state name is given a symbolic name which is written in the upper left corner of the
box.
 After the state assignment, the binary code is placed at upper right corner of the box.

Decision box :

Decision box

 It describes the effect of the input on the control subsystem.

 It is a diamond-shaped box with two or more exit paths. The input condition which
needs to be checked is written inside the box.
 One exit path is taken when the condition is true, otherwise other is taken when the
condition is false.
 When the input condition is assigned to a binary value, then the two paths are
indicated by 1 and 0.

Conditional Output box:

Condition Output box

 It has an oval shape. The input path of the conditional box must come from the exit
path of the decision box.
 The register operations and output lists are written inside the conditional box which is
generated in a particular state but the input condition must be true.

Q-

Ans:
Q-Draw ASM chart for 2 bit binary counter having enable line E such that:
E=1, Count Enable and E=0, Count Disable?
Ans:
Q-

Ans: