Exp No: 3
ESTIMATION OF POWER IN ARRAY MULTIPLIER AND BOOTH MULTIPLIER
Date: 02/09/25
AIM:
To simulate array multiplier and booth multiplier, obtain the estimated the power
consumption and utilization report for analysis
SOFTWARE USED:
Xilinx Vivado
PROCEDURE:
1. Open Xilinx virtuoso Tool
2. Create a new project and Add source for writing the source code. Write the
Verilog HDL code for creating a ripple carry adder and carry look ahead adder by
following the step-by-step procedure given in manual document.
3. Perform simulation and verify the functionality of the circuit.
4. Synthesize the code and obtain the utilization and power report of the adders and
tabulate.
VERILOG CODE FOR BOOTH MULTIPLIER:
timescale 1ns / 1ps
module booth_multiplier (
input wire clk,
input wire start,
input wire signed [3:0] M, // multiplicand
input wire signed [3:0] Q, // multiplier
output reg signed [7:0] P, // product (8-bit signed)
output reg done
);
reg signed [7:0] A;
reg signed [7:0] M_ext;
reg [3:0] Q_reg;
reg Qm1;
BOOTH MULTIPLIER :
SCHEMATIC :
CONSTRAINTS:
reg [2:0] count;
reg signed [7:0] A_temp;
reg signed [7:0] A_next;
reg [3:0] Q_next;
reg Qm1_next;
reg signed [12:0] combined; // {A_temp, Q_reg, Qm1}
reg [11:0] result; // {A_next, Q_next}
always @(posedge clk) begin
if (start) begin
// initialize
A <= 8'sd0;
Q_reg <= Q;
Qm1 <= 1'b0;
M_ext <= { {4{M[3]}}, M }; // sign-extend multiplicand
count <= 3'd4;
done <= 1'b0;
P <= 8'sd0;
end
else if (count != 0) begin
// step 1: compute add/sub
case ({Q_reg[0], Qm1})
2'b01: A_temp = A + M_ext;
2'b10: A_temp = A - M_ext;
default: A_temp = A;
endcase
combined = {A_temp, Q_reg, Qm1};
combined = combined >>> 1; // arithmetic right shift
// step 3: update next values
UTILIZATION REPORT:
POWER:
= combined[12:5];
Q_next = combined[4:1];
Qm1_next = combined[0];
;
initial begin
$display(" A B | Product ");
for (i = 0; i < 4; i = i + 1) begin
for (j = 0; j < 4; j = j + 1) begin
A = i;
B = j;
#10;
Endmodule
Testbench for booth multiplier:
`timescale 1ns / 1ps
module tb_booth_multiplier;
reg clk;
reg start;
reg signed [3:0] M;
reg signed [3:0] Q;
wire signed [7:0] P;
wire done;
// DUT instantiation
booth_multiplier dut (
.clk(clk),
.start(start),
.M(M),
.Q(Q),
.P(P),
.done(done)
);
SIMULATION:
PATH DELAY:
initial clk = 0;
always #5 clk = ~clk;
integer i, j;
reg signed [7:0] expected;
task run_case;
input signed [3:0] m_in;
input signed [3:0] q_in;
begin
@(negedge clk);
M = m_in;
Q = q_in;
start = 1;
@(negedge clk);
start = 0;
wait(done == 1);
@(posedge clk);
expected = m_in * q_in;
initial begin
start = 0; M = 0; Q = 0;
for (i = -8; i < 8; i = i + 1) begin
for (j = -8; j < 8; j = j + 1) begin
run_case(i, j);
end
end
$display("All testcases finished.");
$stop;
end
endmodule
PATH DELAY:
ARRAY MULTIPLIER:
SIMULATION:
VERILOG CODE FOR ARRAY MULTIPLIER:
`timescale 1ns / 1ps
module array_multiplier_2x2(
input [1:0] A, // 2-bit input A
input [1:0] B, // 2-bit input B
output [3:0] P // 4-bit product
);
wire p0, p1, p2, p3; // partial products
wire s1, c1, s2, c2; // sums and carries
// Step 1: Generate partial products
assign p0 = A[0] & B[0];
assign p1 = A[1] & B[0];
assign p2 = A[0] & B[1];
assign p3 = A[1] & B[1];
// First stage addition
assign s1 = p1 ^ p2; // sum of p1 and p2
assign c1 = p1 & p2; // carry of p1 and p2
assign s2 = p3 ^ c1; // sum of p3 and c1
assign c2 = p3 & c1; // carry of p3 and c1
// Step 3: Form the final product
assign P[0] = p0;
assign P[1] = s1;
assign P[2] = s2;
assign P[3] = c2;
endmodule
SCHEMATIC:
UTILIZATION REPORT:
TEST BENCH CODE FRO ARRAY MULTIPLIER:
`timescale 1ns / 1ps
module tb_array_multiplier_2x2;
// Testbench signals
reg [1:0] A;
reg [1:0] B;
wire [3:0] P;
// Instantiate the DUT (Device Under Test)
array_multiplier_2x2 dut (
.A(A),
.B(B),
.P(P)
);
integer i, j;
initial begin
// Display header
$display(" A B | Product ");
$display("----------------");
// Apply all input combinations
for (i = 0; i < 4; i = i + 1) begin
for (j = 0; j < 4; j = j + 1) begin
A = i;
B = j;
PATH DELAY:
#10; // wait for output to settle
$display(" %b %b | %b (%d)", A, B, P, P);
end
end
$stop; // stop simulation
end
endmodule
PATH DELAY:
POWER REPORT:
CONSTRAINT FILE:
SYNTHESIS SCHEMATIC:
COMPARISON:
LUT Static power Dynamic power Time Logic levels
BOOTH MULTIPLIER
ARRAY MULTIPLIER
RESULT:
Thus array multiplier and booth multiplier has been simulated successfully in vivado and the
power consumption and utilization report is noted and the output is verified successfully
