NOTE : (yellow shaded) is the saved filename in the program .
saved filename and yellow
shaded should be same.
Code reference from GRT Engineering college and [Link] Engineering college
1. LOGIC GATES:
module gatand(a, b, c_and, d_or, e_nand, f_nor, g_xor, h_xnor);
input a;
input b;
output c_and;
output d_or;
output e_nand;
output f_nor;
output g_xor;
output h_xnor;
and (c_and,a,b);
or (d_or,a,b);
nand (e_nand,a,b);
nor (f_nor,a,b);
xor (g_xor,a,b);
xnor (h_xnor,a,b);
endmodule
2. SHIFT REGISTERS:
module shiftreg(a,s,clk,p);
input [3:0]a;
input [1:0]s;
input clk;
output reg [3:0]p;
initial
p<=4'b0110;
always@(posedge clk)
begin
case (s)
2'b00:
begin
p[3]<=p[3];
p[2]<=p[2];
p[1]<=p[1];
p[0]<=p[0];
end
2'b01:
begin
p[3]<=p[0];
p[2]<=p[3];
p[1]<=p[2];
p[0]<=p[1];
end
2'b10:
begin
p[0]<=p[3];
p[1]<=p[0];
p[2]<=p[1];
p[3]<=p[2];
end
2'b11:
begin
p[0]<=a[0];
p[1]<=a[1];
p[2]<=a[2];
p[3]<=a[3];
end
endcase
end
endmodule
3. HALF ADDER:
module halfadd(a,b,sum,carry);
input a,b;
output sum,carry;
xor (sum,a,b);
and (carry,a,b);
endmodule
4. FULL ADDER:
module fulladd (sum, carry, a, b, c);
input a, b, c;
output sum, carry;
wire w1, w2, w3;
xor (sum,a,b,c);
and (w1,a,b);
and(w2,b,c);
and(w3,c,a);
or(carry,w1,w2,w3);
endmodule
5. HALF SUBTRACTOR:
module halfsub(a, b, diff, borr);
input a, b;
output diff, borr;
wire s;
not (s, a);
xor (diff, a, b);
and (borr, s, b);
endmodule
6. FULL SUBTRACTOR:
module fullsub (a, b, cin, diff, borr);
input a, b, cin;
output diff, borr;
wire w1, w2, w3, w4, w5;
not n1(w1, a);
not n2(w4, w3);
xor x1(w3, a, b);
xor x2(diff, w3, cin);
and a1(w2, w1, b);
and a2(w5,w4,cin);
or g1(borr, w5, w2);
endmodule
7. 8 BIT ADDER:
module bitaddeight(a,b,sum);
input [7:0]a,b;
output [7:0]sum;
assign sum=a+b;
endmodule
8. 8 BIT MULTIPLIER USING HALF ADDER:
module bitmultieight(sout,cout,a,b);
input a,b;
output sout,cout;
assign sout=(a^b);
assign cout=(a&b);
endmodule
9. 8 BIT MULTIPLIER USING FULL ADDER:
module HA (sout,cout,a,b);
input a,b;
output sout,cout;
assign sout=(a^b);
assign cout=(a&b);
endmodule
module FA (sout,cout,a,b,cin);
input a,b,cin;
output sout,cout;
assign sout=(a^b^cin);
assign cout=((a&b)|(b&cin)|(cin&a));
endmodule
module bitmul (m,x,y);
output [7:0]m;
input [3:0]x;
input [3:0]y;
assign m[0]=(x[0]&y[0]);
wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17;
HA HA1 (m[1],x1,(x[1]&y[0]),(x[0]&y[1]));
FA FA1 (x2,x3,(x[1]&y[1]),(x[0]&y[2]),x1);
FA FA2 (x4,x5,(x[1]&y[2]),(x[0]&y[3]),x3);
HA HA2 (x6,x7,(x[1]&y[3]),x5);
HA HA3 (m[2],x15,x2,(x[2]&y[0]));
FA FA5 (x14,x16,x4,(x[2]&y[1]),x15);
FA FA4 (x13,x17,x6,(x[2]&y[2]),x16);
FA FA3 (x9,x8,x7,(x[2]&y[3]),x17);
HA HA4 (m[3],x12,x14,(x[3]&y[0]));
FA FA8 (m[4],x11,x13,(x[3]&y[1]),x12);
FA FA7 (m[5],x10,x9,(x[3]&y[2]),x11);
FA FA6 (m[6],m[7],x8,(x[3]&y[3]),x10);
Endmodule
10. UPCOUNTER:
module upccounterr(clk,clr,q);
input clk, clr;
output [3:0]q;
reg [3:0]tmp;
always@(posedge clk or posedge clr)
begin
if (clr)
tmp <= 4'b0000;
else
tmp <= tmp + 1'b1;
end
assign q = tmp;
endmodule
11. DOWNCOUNTER:
module downccount(clk,clr,q);
input clk, clr;
output [3:0]q;
reg [3:0]tmp;
always@(posedge clk or posedge clr)
begin
if (clr)
tmp <= 4'b1111;
else
tmp <= tmp - 1'b1;
end
assign q = tmp;
endmodule
12. COUNTER (WITH 3 INPUTS
module counter(clk,rst,sel,count);
input clk,rst,sel;
output reg[3:0] count;
always @(posedge clk)
begin
if(rst==1 && sel==0)
count=0;
else if(rst==1 && sel==1)
count=4'd15;
else if(rst==0 && sel==0)
count=count+1;
else if(rst==0 && sel==1)
count=count-1;
end
endmodule
13. FINITE STATE MACHINE(MOORE)
module fsm( clk, rst, inp, outp);
input clk, rst, inp;
output outp;
reg [1:0] state;
reg outp;
always @( posedge clk, posedge rst )
begin
if( rst )
state <= 2'b00;
else
begin
case( state )
2'b00:
begin
if( inp ) state <= 2'b01;
else state <= 2'b10;
end
2'b01:
begin
if( inp ) state <= 2'b11;
else state <= 2'b10;
end
2'b10:
begin
if( inp ) state <= 2'b01;
else state <= 2'b11;
end
2'b11:
begin
if( inp ) state <= 2'b01;
else state <= 2'b10;
end
endcase
end
end
always @(posedge clk, posedge rst)
begin
if( rst )
outp <= 0;
else if( state == 2'b11 )
outp <= 1;
else outp <= 0;
end
endmodule
14. FINITE STATE MACHINE(MEELAY)
module fsmmeelay( clk, rst, inp, outp);
input clk, rst, inp;
output outp;
reg [1:0] state;
reg outp;
always @( posedge clk, posedge rst ) begin
if( rst ) begin
state <= 2'b00;
outp <= 0;
end
else begin
case( state )
2'b00: begin
if( inp ) begin
state <= 2'b01;
outp <= 0;
end
else begin
state <= 2'b10;
outp <= 0;
end
end
2'b01: begin
if( inp ) begin
state <= 2'b00;
outp <= 1;
end
else begin
state <= 2'b10;
outp <= 0;
end
end
2'b10: begin
if( inp ) begin
state <= 2'b01;
outp <= 0;
end
else begin
state <= 2'b00;
outp <= 1;
end
end
default: begin
state <= 2'b00;
outp <= 0;
end
endcase
end
end
endmodule
15. MEMORIES:
module mmemories(op,ip,rd_wr,clk,address);
output reg [3:0] op;
input [3:0] ip;
input [3:0] address;
input rd_wr,clk;
reg [3:0] memory[0:15];
always @(posedge clk)
begin
if (rd_wr)
op=memory[address];
else
begin
memory[address]=ip;
end
end
endmodule // memory_16x4
