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Verilog Assignment 6 Rajasekhar

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17 views23 pages

Verilog Assignment 6 Rajasekhar

Uploaded by

sivakrishnahumanvenkata
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Verilog_assignment_6

1)
Design memory module with APB interface.
• Define module with bellow ports, - input ports: pclk, prst, paddr, pwrite, pwdata, psel, penable, load,
fetch - output ports: prdata, pready, pslverr
• Load=1, should initialize memory contents from external hex image file(image_i.hex)
• Fetch=1, should read memory contents into external hex image file (image_o.hex)
• Write $display in memory module to display paddr, pwdata
• Declare reg *7:0+mem*127:0+ memory
• Code logic to write pwdata in to memory at paddr location when write is issued (pwrite=1)
• Code logic to read prdata from memory at paddr location when read is issued (pwrite=0)
• Write a logic to initialize memory contents when a prst is asserted (all memory locations should be
made 0)
• penable=0, indicates no access to memory pready should be ‘0’
• penable=1, pwrite=1 indicates valid write to memory
• Drive pslverr=0 if address is valid(i.e between 0 to 127)
• Drive pslverr=1(error) if address is outside memory range
• penable=1, pwrite=0 indicates valid read to memory
• Here also drive pslverr=0 if address is valid(i.e between 0 to 127) else drive pslverr=1(error) if address
is outside memory range
• Write a logic initialize memory when init=1 is issued - Image file: image_i.hex (128 lines with 2 nibbles
in each line) - Use $readmemh to load memory when init=1

A)
module memory_apb (
input pclk,
input prst,
input pwrite,
input psel,
input penable,
input load,
input fetch,
input [7:0] paddr,
input [7:0] pwdata,
output reg [7:0] prdata,
output reg pready, pslverr
);
reg [7:0] mem [0:127];
integer i;

always @(posedge pclk or posedge prst) begin


if (prst) begin
for (i = 0; i < 128; i = i + 1) begin
mem[i] <= 8'h00;
end
prdata <= 8'h00;
pready <= 1'b0;
pslverr <= 1'b0;
end
else begin
pready <= 1'b0;
pslverr <= 1'b0;
if (load) begin
$readmemh("image_i.hex", mem);
$display("Memory loaded from image_i.hex");
end
if (fetch) begin
$writememh("image_o.hex", mem);
$display("Memory fetched to image_o.hex");
end
if (psel && penable) begin
if (paddr <= 127) begin
pready <= 1'b1;
pslverr <= 1'b0;
if (pwrite) begin
mem[paddr] <= pwdata;
$display("Write: paddr=%h, pwdata=%h", paddr, pwdata);
end
else begin
prdata <= mem[paddr];
end
end
else begin
pready <= 1'b1;
pslverr <= 1'b1;
end
end
end
end
endmodule
• Design testbench with following test cases
- Test_all_location_wr_rd
- Test_backdoor_load_frontdoor_read
- Test_backdoor_load_backdoor_read
- Test_10_random_write_read
- Test_addr_walking_ones
• Develop a checker to perform checking operation automatically

TESTBENCH:
// Code your testbench here
// or browse Examples
module memory_apb_tb;
reg pclk, prst, pwrite, psel, penable, load, fetch;
reg [7:0] paddr;
reg [7:0] pwdata;
wire [7:0] prdata;
wire pready, pslverr;

memory_apb dut (
.pclk(pclk),
.prst(prst),
.paddr(paddr),
.pwrite(pwrite),
.pwdata(pwdata),
.psel(psel),
.penable(penable),
.load(load),
.fetch(fetch),
.prdata(prdata),
.pready(pready),
.pslverr(pslverr)
);

initial begin
pclk = 0;
forever #5 pclk = ~pclk;
end

reg [7:0] expected_values [0:127];


integer error_count = 0;

initial begin
$readmemh("image_i.hex", expected_values);
$display("Loaded expected values from image_i.hex into expected_values");
end

initial begin
$dumpfile("[Link]");
$dumpvars(0, memory_apb_tb);
prst = 1; psel = 0; penable = 0; pwrite = 0; pwdata = 0; paddr = 0; load = 0; fetch = 0;
#20 prst = 0;

$display("Test 1: Writing and Reading all locations");


for (int i = 0; i < 128; i++) begin
write_mem(i, i);
read_mem(i);
check_data(i);
end

$display("Test 2: Backdoor Load, Frontdoor Read");


load = 1; #10 load = 0;
for (int i = 0; i < 128; i++) begin
read_mem(i);
check_data(expected_values[i]);
end

$display("Test 3: Backdoor Load, Backdoor Fetch");


load = 1; #10 load = 0;
fetch = 1; #10 fetch = 0;
for (int i = 0; i < 128; i++) begin
read_mem(i);
check_data(expected_values[i]);
end

$display("Test 4: 10 Random Write and Read");


repeat (10) begin
paddr = $random % 128;
pwdata = $random;
write_mem(paddr, pwdata);
read_mem(paddr);
check_data(pwdata);
end

$display("Test 5: Address Walking Ones");


for (int i = 0; i < 8; i++) begin
paddr = 1 << i;
pwdata = 8'hAA;
write_mem(paddr, pwdata);
read_mem(paddr);
check_data(8'hAA);
end

$display("Total Errors: %0d", error_count);


#200 $finish;
end

task write_mem(input [7:0] addr, input [7:0] data);


begin
@(posedge pclk);
psel = 1; paddr = addr; pwrite = 1; pwdata = data;
@(posedge pclk);
penable = 1;
@(posedge pclk);
wait(pready);
@(posedge pclk);
psel = 0; penable = 0; pwrite = 0;
end
endtask

task read_mem(input [7:0] addr);


begin
@(posedge pclk);
psel = 1; paddr = addr; pwrite = 0;
@(posedge pclk);
penable = 1;
@(posedge pclk);
wait(pready);
@(posedge pclk);
psel = 0; penable = 0;
end
endtask

task check_data(input [7:0] expected);


begin
if (prdata !== expected) begin
$display("ERROR: Addr=%h, Expected=%h, Got=%h", paddr, expected, prdata);
error_count = error_count + 1;
end
else begin
$display("PASS: Addr=%h, Data=%h", paddr, prdata);
end
end
endtask
endmodule

image_i.hex

A3
7B
12
F9
5C
E4
2D
91
C8
36
B0
4F
D7
1A
8E
65
FD
29
B4
0C
76
E2
53
9A
C1
38
AF
14
8B
60
D5
2E
97
C3
4A
BE
07
81
F6
3D
A9
22
78
E0
5B
C4
19
92
F8
31
A6
0F
84
DB
46
BC
25
9E
F3
68
D0
1B
72
E9
54
CA
33
A8
1D
86
FD
48
B2
09
7E
E5
50
C7
2C
93
F9
34
AB
16
8C
61
D8
43
BA
05
7F
E6
51
C8
2D
94
FA
35
AC
17
8D
62
D9
44
BB
06
80
E7
52
C9
2E
95
FB
36
AD
18
8E
63
DA
45
BC
07
81
E8
53
CA
2F
96

OUTPUT:
Test 1: Writing and Reading all locations
Write: paddr=00, pwdata=00
Write: paddr=00, pwdata=00
PASS: Addr=00, Data=00
Write: paddr=01, pwdata=01
Write: paddr=01, pwdata=01
PASS: Addr=01, Data=01
Write: paddr=02, pwdata=02
Write: paddr=02, pwdata=02
PASS: Addr=02, Data=02
Write: paddr=03, pwdata=03
Write: paddr=03, pwdata=03
PASS: Addr=03, Data=03
Write: paddr=04, pwdata=04
Write: paddr=04, pwdata=04
PASS: Addr=04, Data=04
Write: paddr=05, pwdata=05
Write: paddr=05, pwdata=05
PASS: Addr=05, Data=05
Write: paddr=06, pwdata=06
Write: paddr=06, pwdata=06
PASS: Addr=06, Data=06
Write: paddr=07, pwdata=07
Write: paddr=07, pwdata=07
PASS: Addr=07, Data=07
Write: paddr=08, pwdata=08
Write: paddr=08, pwdata=08
PASS: Addr=08, Data=08
Write: paddr=09, pwdata=09
Write: paddr=09, pwdata=09
PASS: Addr=09, Data=09
Write: paddr=0a, pwdata=0a
Write: paddr=0a, pwdata=0a
PASS: Addr=0a, Data=0a
Write: paddr=0b, pwdata=0b
Write: paddr=0b, pwdata=0b
PASS: Addr=0b, Data=0b
Write: paddr=0c, pwdata=0c
Write: paddr=0c, pwdata=0c
PASS: Addr=0c, Data=0c
Write: paddr=0d, pwdata=0d
Write: paddr=0d, pwdata=0d
PASS: Addr=0d, Data=0d
Write: paddr=0e, pwdata=0e
Write: paddr=0e, pwdata=0e
PASS: Addr=0e, Data=0e
Write: paddr=0f, pwdata=0f
Write: paddr=0f, pwdata=0f
PASS: Addr=0f, Data=0f
Write: paddr=10, pwdata=10
Write: paddr=10, pwdata=10
PASS: Addr=10, Data=10
Write: paddr=11, pwdata=11
Write: paddr=11, pwdata=11
PASS: Addr=11, Data=11
Write: paddr=12, pwdata=12
Write: paddr=12, pwdata=12
PASS: Addr=12, Data=12
Write: paddr=13, pwdata=13
Write: paddr=13, pwdata=13
PASS: Addr=13, Data=13
Write: paddr=14, pwdata=14
Write: paddr=14, pwdata=14
PASS: Addr=14, Data=14
Write: paddr=15, pwdata=15
Write: paddr=15, pwdata=15
PASS: Addr=15, Data=15
Write: paddr=16, pwdata=16
Write: paddr=16, pwdata=16
PASS: Addr=16, Data=16
Write: paddr=17, pwdata=17
Write: paddr=17, pwdata=17
PASS: Addr=17, Data=17
Write: paddr=18, pwdata=18
Write: paddr=18, pwdata=18
PASS: Addr=18, Data=18
Write: paddr=19, pwdata=19
Write: paddr=19, pwdata=19
PASS: Addr=19, Data=19
Write: paddr=1a, pwdata=1a
Write: paddr=1a, pwdata=1a
PASS: Addr=1a, Data=1a
Write: paddr=1b, pwdata=1b
Write: paddr=1b, pwdata=1b
PASS: Addr=1b, Data=1b
Write: paddr=1c, pwdata=1c
Write: paddr=1c, pwdata=1c
PASS: Addr=1c, Data=1c
Write: paddr=1d, pwdata=1d
Write: paddr=1d, pwdata=1d
PASS: Addr=1d, Data=1d
Write: paddr=1e, pwdata=1e
Write: paddr=1e, pwdata=1e
PASS: Addr=1e, Data=1e
Write: paddr=1f, pwdata=1f
Write: paddr=1f, pwdata=1f
PASS: Addr=1f, Data=1f
Write: paddr=20, pwdata=20
Write: paddr=20, pwdata=20
PASS: Addr=20, Data=20
Write: paddr=21, pwdata=21
Write: paddr=21, pwdata=21
PASS: Addr=21, Data=21
Write: paddr=22, pwdata=22
Write: paddr=22, pwdata=22
PASS: Addr=22, Data=22
Write: paddr=23, pwdata=23
Write: paddr=23, pwdata=23
PASS: Addr=23, Data=23
Write: paddr=24, pwdata=24
Write: paddr=24, pwdata=24
PASS: Addr=24, Data=24
Write: paddr=25, pwdata=25
Write: paddr=25, pwdata=25
PASS: Addr=25, Data=25
Write: paddr=26, pwdata=26
Write: paddr=26, pwdata=26
PASS: Addr=26, Data=26
Write: paddr=27, pwdata=27
Write: paddr=27, pwdata=27
PASS: Addr=27, Data=27
Write: paddr=28, pwdata=28
Write: paddr=28, pwdata=28
PASS: Addr=28, Data=28
Write: paddr=29, pwdata=29
Write: paddr=29, pwdata=29
PASS: Addr=29, Data=29
Write: paddr=2a, pwdata=2a
Write: paddr=2a, pwdata=2a
PASS: Addr=2a, Data=2a
Write: paddr=2b, pwdata=2b
Write: paddr=2b, pwdata=2b
PASS: Addr=2b, Data=2b
Write: paddr=2c, pwdata=2c
Write: paddr=2c, pwdata=2c
PASS: Addr=2c, Data=2c
Write: paddr=2d, pwdata=2d
Write: paddr=2d, pwdata=2d
PASS: Addr=2d, Data=2d
Write: paddr=2e, pwdata=2e
Write: paddr=2e, pwdata=2e
PASS: Addr=2e, Data=2e
Write: paddr=2f, pwdata=2f
Write: paddr=2f, pwdata=2f
PASS: Addr=2f, Data=2f
Write: paddr=30, pwdata=30
Write: paddr=30, pwdata=30
PASS: Addr=30, Data=30
Write: paddr=31, pwdata=31
Write: paddr=31, pwdata=31
PASS: Addr=31, Data=31
Write: paddr=32, pwdata=32
Write: paddr=32, pwdata=32
PASS: Addr=32, Data=32
Write: paddr=33, pwdata=33
Write: paddr=33, pwdata=33
PASS: Addr=33, Data=33
Write: paddr=34, pwdata=34
Write: paddr=34, pwdata=34
PASS: Addr=34, Data=34
Write: paddr=35, pwdata=35
Write: paddr=35, pwdata=35
PASS: Addr=35, Data=35
Write: paddr=36, pwdata=36
Write: paddr=36, pwdata=36
PASS: Addr=36, Data=36
Write: paddr=37, pwdata=37
Write: paddr=37, pwdata=37
PASS: Addr=37, Data=37
Write: paddr=38, pwdata=38
Write: paddr=38, pwdata=38
PASS: Addr=38, Data=38
Write: paddr=39, pwdata=39
Write: paddr=39, pwdata=39
PASS: Addr=39, Data=39
Write: paddr=3a, pwdata=3a
Write: paddr=3a, pwdata=3a
PASS: Addr=3a, Data=3a
Write: paddr=3b, pwdata=3b
Write: paddr=3b, pwdata=3b
PASS: Addr=3b, Data=3b
Write: paddr=3c, pwdata=3c
Write: paddr=3c, pwdata=3c
PASS: Addr=3c, Data=3c
Write: paddr=3d, pwdata=3d
Write: paddr=3d, pwdata=3d
PASS: Addr=3d, Data=3d
Write: paddr=3e, pwdata=3e
Write: paddr=3e, pwdata=3e
PASS: Addr=3e, Data=3e
Write: paddr=3f, pwdata=3f
Write: paddr=3f, pwdata=3f
PASS: Addr=3f, Data=3f
Write: paddr=40, pwdata=40
Write: paddr=40, pwdata=40
PASS: Addr=40, Data=40
Write: paddr=41, pwdata=41
Write: paddr=41, pwdata=41
PASS: Addr=41, Data=41
Write: paddr=42, pwdata=42
Write: paddr=42, pwdata=42
PASS: Addr=42, Data=42
Write: paddr=43, pwdata=43
Write: paddr=43, pwdata=43
PASS: Addr=43, Data=43
Write: paddr=44, pwdata=44
Write: paddr=44, pwdata=44
PASS: Addr=44, Data=44
Write: paddr=45, pwdata=45
Write: paddr=45, pwdata=45
PASS: Addr=45, Data=45
Write: paddr=46, pwdata=46
Write: paddr=46, pwdata=46
PASS: Addr=46, Data=46
Write: paddr=47, pwdata=47
Write: paddr=47, pwdata=47
PASS: Addr=47, Data=47
Write: paddr=48, pwdata=48
Write: paddr=48, pwdata=48
PASS: Addr=48, Data=48
Write: paddr=49, pwdata=49
Write: paddr=49, pwdata=49
PASS: Addr=49, Data=49
Write: paddr=4a, pwdata=4a
Write: paddr=4a, pwdata=4a
PASS: Addr=4a, Data=4a
Write: paddr=4b, pwdata=4b
Write: paddr=4b, pwdata=4b
PASS: Addr=4b, Data=4b
Write: paddr=4c, pwdata=4c
Write: paddr=4c, pwdata=4c
PASS: Addr=4c, Data=4c
Write: paddr=4d, pwdata=4d
Write: paddr=4d, pwdata=4d
PASS: Addr=4d, Data=4d
Write: paddr=4e, pwdata=4e
Write: paddr=4e, pwdata=4e
PASS: Addr=4e, Data=4e
Write: paddr=4f, pwdata=4f
Write: paddr=4f, pwdata=4f
PASS: Addr=4f, Data=4f
Write: paddr=50, pwdata=50
Write: paddr=50, pwdata=50
PASS: Addr=50, Data=50
Write: paddr=51, pwdata=51
Write: paddr=51, pwdata=51
PASS: Addr=51, Data=51
Write: paddr=52, pwdata=52
Write: paddr=52, pwdata=52
PASS: Addr=52, Data=52
Write: paddr=53, pwdata=53
Write: paddr=53, pwdata=53
PASS: Addr=53, Data=53
Write: paddr=54, pwdata=54
Write: paddr=54, pwdata=54
PASS: Addr=54, Data=54
Write: paddr=55, pwdata=55
Write: paddr=55, pwdata=55
PASS: Addr=55, Data=55
Write: paddr=56, pwdata=56
Write: paddr=56, pwdata=56
PASS: Addr=56, Data=56
Write: paddr=57, pwdata=57
Write: paddr=57, pwdata=57
PASS: Addr=57, Data=57
Write: paddr=58, pwdata=58
Write: paddr=58, pwdata=58
PASS: Addr=58, Data=58
Write: paddr=59, pwdata=59
Write: paddr=59, pwdata=59
PASS: Addr=59, Data=59
Write: paddr=5a, pwdata=5a
Write: paddr=5a, pwdata=5a
PASS: Addr=5a, Data=5a
Write: paddr=5b, pwdata=5b
Write: paddr=5b, pwdata=5b
PASS: Addr=5b, Data=5b
Write: paddr=5c, pwdata=5c
Write: paddr=5c, pwdata=5c
PASS: Addr=5c, Data=5c
Write: paddr=5d, pwdata=5d
Write: paddr=5d, pwdata=5d
PASS: Addr=5d, Data=5d
Write: paddr=5e, pwdata=5e
Write: paddr=5e, pwdata=5e
PASS: Addr=5e, Data=5e
Write: paddr=5f, pwdata=5f
Write: paddr=5f, pwdata=5f
PASS: Addr=5f, Data=5f
Write: paddr=60, pwdata=60
Write: paddr=60, pwdata=60
PASS: Addr=60, Data=60
Write: paddr=61, pwdata=61
Write: paddr=61, pwdata=61
PASS: Addr=61, Data=61
Write: paddr=62, pwdata=62
Write: paddr=62, pwdata=62
PASS: Addr=62, Data=62
Write: paddr=63, pwdata=63
Write: paddr=63, pwdata=63
PASS: Addr=63, Data=63
Write: paddr=64, pwdata=64
Write: paddr=64, pwdata=64
PASS: Addr=64, Data=64
Write: paddr=65, pwdata=65
Write: paddr=65, pwdata=65
PASS: Addr=65, Data=65
Write: paddr=66, pwdata=66
Write: paddr=66, pwdata=66
PASS: Addr=66, Data=66
Write: paddr=67, pwdata=67
Write: paddr=67, pwdata=67
PASS: Addr=67, Data=67
Write: paddr=68, pwdata=68
Write: paddr=68, pwdata=68
PASS: Addr=68, Data=68
Write: paddr=69, pwdata=69
Write: paddr=69, pwdata=69
PASS: Addr=69, Data=69
Write: paddr=6a, pwdata=6a
Write: paddr=6a, pwdata=6a
PASS: Addr=6a, Data=6a
Write: paddr=6b, pwdata=6b
Write: paddr=6b, pwdata=6b
PASS: Addr=6b, Data=6b
Write: paddr=6c, pwdata=6c
Write: paddr=6c, pwdata=6c
PASS: Addr=6c, Data=6c
Write: paddr=6d, pwdata=6d
Write: paddr=6d, pwdata=6d
PASS: Addr=6d, Data=6d
Write: paddr=6e, pwdata=6e
Write: paddr=6e, pwdata=6e
PASS: Addr=6e, Data=6e
Write: paddr=6f, pwdata=6f
Write: paddr=6f, pwdata=6f
PASS: Addr=6f, Data=6f
Write: paddr=70, pwdata=70
Write: paddr=70, pwdata=70
PASS: Addr=70, Data=70
Write: paddr=71, pwdata=71
Write: paddr=71, pwdata=71
PASS: Addr=71, Data=71
Write: paddr=72, pwdata=72
Write: paddr=72, pwdata=72
PASS: Addr=72, Data=72
Write: paddr=73, pwdata=73
Write: paddr=73, pwdata=73
PASS: Addr=73, Data=73
Write: paddr=74, pwdata=74
Write: paddr=74, pwdata=74
PASS: Addr=74, Data=74
Write: paddr=75, pwdata=75
Write: paddr=75, pwdata=75
PASS: Addr=75, Data=75
Write: paddr=76, pwdata=76
Write: paddr=76, pwdata=76
PASS: Addr=76, Data=76
Write: paddr=77, pwdata=77
Write: paddr=77, pwdata=77
PASS: Addr=77, Data=77
Write: paddr=78, pwdata=78
Write: paddr=78, pwdata=78
PASS: Addr=78, Data=78
Write: paddr=79, pwdata=79
Write: paddr=79, pwdata=79
PASS: Addr=79, Data=79
Write: paddr=7a, pwdata=7a
Write: paddr=7a, pwdata=7a
PASS: Addr=7a, Data=7a
Write: paddr=7b, pwdata=7b
Write: paddr=7b, pwdata=7b
PASS: Addr=7b, Data=7b
Write: paddr=7c, pwdata=7c
Write: paddr=7c, pwdata=7c
PASS: Addr=7c, Data=7c
Write: paddr=7d, pwdata=7d
Write: paddr=7d, pwdata=7d
PASS: Addr=7d, Data=7d
Write: paddr=7e, pwdata=7e
Write: paddr=7e, pwdata=7e
PASS: Addr=7e, Data=7e
Write: paddr=7f, pwdata=7f
Write: paddr=7f, pwdata=7f
PASS: Addr=7f, Data=7f
Test 2: Backdoor Load, Frontdoor Read
Memory loaded from image_i.hex
PASS: Addr=00, Data=a3
PASS: Addr=01, Data=7b
PASS: Addr=02, Data=12
PASS: Addr=03, Data=f9
PASS: Addr=04, Data=5c
PASS: Addr=05, Data=e4
PASS: Addr=06, Data=2d
PASS: Addr=07, Data=91
PASS: Addr=08, Data=c8
PASS: Addr=09, Data=36
PASS: Addr=0a, Data=b0
PASS: Addr=0b, Data=4f
PASS: Addr=0c, Data=d7
PASS: Addr=0d, Data=1a
PASS: Addr=0e, Data=8e
PASS: Addr=0f, Data=65
PASS: Addr=10, Data=fd
PASS: Addr=11, Data=29
PASS: Addr=12, Data=b4
PASS: Addr=13, Data=0c
PASS: Addr=14, Data=76
PASS: Addr=15, Data=e2
PASS: Addr=16, Data=53
PASS: Addr=17, Data=9a
PASS: Addr=18, Data=c1
PASS: Addr=19, Data=38
PASS: Addr=1a, Data=af
PASS: Addr=1b, Data=14
PASS: Addr=1c, Data=8b
PASS: Addr=1d, Data=60
PASS: Addr=1e, Data=d5
PASS: Addr=1f, Data=2e
PASS: Addr=20, Data=97
PASS: Addr=21, Data=c3
PASS: Addr=22, Data=4a
PASS: Addr=23, Data=be
PASS: Addr=24, Data=07
PASS: Addr=25, Data=81
PASS: Addr=26, Data=f6
PASS: Addr=27, Data=3d
PASS: Addr=28, Data=a9
PASS: Addr=29, Data=22
PASS: Addr=2a, Data=78
PASS: Addr=2b, Data=e0
PASS: Addr=2c, Data=5b
PASS: Addr=2d, Data=c4
PASS: Addr=2e, Data=19
PASS: Addr=2f, Data=92
PASS: Addr=30, Data=f8
PASS: Addr=31, Data=31
PASS: Addr=32, Data=a6
PASS: Addr=33, Data=0f
PASS: Addr=34, Data=84
PASS: Addr=35, Data=db
PASS: Addr=36, Data=46
PASS: Addr=37, Data=bc
PASS: Addr=38, Data=25
PASS: Addr=39, Data=9e
PASS: Addr=3a, Data=f3
PASS: Addr=3b, Data=68
PASS: Addr=3c, Data=d0
PASS: Addr=3d, Data=1b
PASS: Addr=3e, Data=72
PASS: Addr=3f, Data=e9
PASS: Addr=40, Data=54
PASS: Addr=41, Data=ca
PASS: Addr=42, Data=33
PASS: Addr=43, Data=a8
PASS: Addr=44, Data=1d
PASS: Addr=45, Data=86
PASS: Addr=46, Data=fd
PASS: Addr=47, Data=48
PASS: Addr=48, Data=b2
PASS: Addr=49, Data=09
PASS: Addr=4a, Data=7e
PASS: Addr=4b, Data=e5
PASS: Addr=4c, Data=50
PASS: Addr=4d, Data=c7
PASS: Addr=4e, Data=2c
PASS: Addr=4f, Data=93
PASS: Addr=50, Data=f9
PASS: Addr=51, Data=34
PASS: Addr=52, Data=ab
PASS: Addr=53, Data=16
PASS: Addr=54, Data=8c
PASS: Addr=55, Data=61
PASS: Addr=56, Data=d8
PASS: Addr=57, Data=43
PASS: Addr=58, Data=ba
PASS: Addr=59, Data=05
PASS: Addr=5a, Data=7f
PASS: Addr=5b, Data=e6
PASS: Addr=5c, Data=51
PASS: Addr=5d, Data=c8
PASS: Addr=5e, Data=2d
PASS: Addr=5f, Data=94
PASS: Addr=60, Data=fa
PASS: Addr=61, Data=35
PASS: Addr=62, Data=ac
PASS: Addr=63, Data=17
PASS: Addr=64, Data=8d
PASS: Addr=65, Data=62
PASS: Addr=66, Data=d9
PASS: Addr=67, Data=44
PASS: Addr=68, Data=bb
PASS: Addr=69, Data=06
PASS: Addr=6a, Data=80
PASS: Addr=6b, Data=e7
PASS: Addr=6c, Data=52
PASS: Addr=6d, Data=c9
PASS: Addr=6e, Data=2e
PASS: Addr=6f, Data=95
PASS: Addr=70, Data=fb
PASS: Addr=71, Data=36
PASS: Addr=72, Data=ad
PASS: Addr=73, Data=18
PASS: Addr=74, Data=8e
PASS: Addr=75, Data=63
PASS: Addr=76, Data=da
PASS: Addr=77, Data=45
PASS: Addr=78, Data=bc
PASS: Addr=79, Data=07
PASS: Addr=7a, Data=81
PASS: Addr=7b, Data=e8
PASS: Addr=7c, Data=53
PASS: Addr=7d, Data=ca
PASS: Addr=7e, Data=2f
PASS: Addr=7f, Data=96
Test 3: Backdoor Load, Backdoor Fetch
Memory loaded from image_i.hex
Memory fetched to image_o.hex
PASS: Addr=00, Data=a3
PASS: Addr=01, Data=7b
PASS: Addr=02, Data=12
PASS: Addr=03, Data=f9
PASS: Addr=04, Data=5c
PASS: Addr=05, Data=e4
PASS: Addr=06, Data=2d
PASS: Addr=07, Data=91
PASS: Addr=08, Data=c8
PASS: Addr=09, Data=36
PASS: Addr=0a, Data=b0
PASS: Addr=0b, Data=4f
PASS: Addr=0c, Data=d7
PASS: Addr=0d, Data=1a
PASS: Addr=0e, Data=8e
PASS: Addr=0f, Data=65
PASS: Addr=10, Data=fd
PASS: Addr=11, Data=29
PASS: Addr=12, Data=b4
PASS: Addr=13, Data=0c
PASS: Addr=14, Data=76
PASS: Addr=15, Data=e2
PASS: Addr=16, Data=53
PASS: Addr=17, Data=9a
PASS: Addr=18, Data=c1
PASS: Addr=19, Data=38
PASS: Addr=1a, Data=af
PASS: Addr=1b, Data=14
PASS: Addr=1c, Data=8b
PASS: Addr=1d, Data=60
PASS: Addr=1e, Data=d5
PASS: Addr=1f, Data=2e
PASS: Addr=20, Data=97
PASS: Addr=21, Data=c3
PASS: Addr=22, Data=4a
PASS: Addr=23, Data=be
PASS: Addr=24, Data=07
PASS: Addr=25, Data=81
PASS: Addr=26, Data=f6
PASS: Addr=27, Data=3d
PASS: Addr=28, Data=a9
PASS: Addr=29, Data=22
PASS: Addr=2a, Data=78
PASS: Addr=2b, Data=e0
PASS: Addr=2c, Data=5b
PASS: Addr=2d, Data=c4
PASS: Addr=2e, Data=19
PASS: Addr=2f, Data=92
PASS: Addr=30, Data=f8
PASS: Addr=31, Data=31
PASS: Addr=32, Data=a6
PASS: Addr=33, Data=0f
PASS: Addr=34, Data=84
PASS: Addr=35, Data=db
PASS: Addr=36, Data=46
PASS: Addr=37, Data=bc
PASS: Addr=38, Data=25
PASS: Addr=39, Data=9e
PASS: Addr=3a, Data=f3
PASS: Addr=3b, Data=68
PASS: Addr=3c, Data=d0
PASS: Addr=3d, Data=1b
PASS: Addr=3e, Data=72
PASS: Addr=3f, Data=e9
PASS: Addr=40, Data=54
PASS: Addr=41, Data=ca
PASS: Addr=42, Data=33
PASS: Addr=43, Data=a8
PASS: Addr=44, Data=1d
PASS: Addr=45, Data=86
PASS: Addr=46, Data=fd
PASS: Addr=47, Data=48
PASS: Addr=48, Data=b2
PASS: Addr=49, Data=09
PASS: Addr=4a, Data=7e
PASS: Addr=4b, Data=e5
PASS: Addr=4c, Data=50
PASS: Addr=4d, Data=c7
PASS: Addr=4e, Data=2c
PASS: Addr=4f, Data=93
PASS: Addr=50, Data=f9
PASS: Addr=51, Data=34
PASS: Addr=52, Data=ab
PASS: Addr=53, Data=16
PASS: Addr=54, Data=8c
PASS: Addr=55, Data=61
PASS: Addr=56, Data=d8
PASS: Addr=57, Data=43
PASS: Addr=58, Data=ba
PASS: Addr=59, Data=05
PASS: Addr=5a, Data=7f
PASS: Addr=5b, Data=e6
PASS: Addr=5c, Data=51
PASS: Addr=5d, Data=c8
PASS: Addr=5e, Data=2d
PASS: Addr=5f, Data=94
PASS: Addr=60, Data=fa
PASS: Addr=61, Data=35
PASS: Addr=62, Data=ac
PASS: Addr=63, Data=17
PASS: Addr=64, Data=8d
PASS: Addr=65, Data=62
PASS: Addr=66, Data=d9
PASS: Addr=67, Data=44
PASS: Addr=68, Data=bb
PASS: Addr=69, Data=06
PASS: Addr=6a, Data=80
PASS: Addr=6b, Data=e7
PASS: Addr=6c, Data=52
PASS: Addr=6d, Data=c9
PASS: Addr=6e, Data=2e
PASS: Addr=6f, Data=95
PASS: Addr=70, Data=fb
PASS: Addr=71, Data=36
PASS: Addr=72, Data=ad
PASS: Addr=73, Data=18
PASS: Addr=74, Data=8e
PASS: Addr=75, Data=63
PASS: Addr=76, Data=da
PASS: Addr=77, Data=45
PASS: Addr=78, Data=bc
PASS: Addr=79, Data=07
PASS: Addr=7a, Data=81
PASS: Addr=7b, Data=e8
PASS: Addr=7c, Data=53
PASS: Addr=7d, Data=ca
PASS: Addr=7e, Data=2f
PASS: Addr=7f, Data=96
Test 4: 10 Random Write and Read
Write: paddr=24, pwdata=81
Write: paddr=24, pwdata=81
PASS: Addr=24, Data=81
ERROR: Addr=89, Expected=63, Got=81
Write: paddr=0d, pwdata=8d
Write: paddr=0d, pwdata=8d
PASS: Addr=0d, Data=8d
ERROR: Addr=e5, Expected=12, Got=8d
Write: paddr=01, pwdata=0d
Write: paddr=01, pwdata=0d
PASS: Addr=01, Data=0d
Write: paddr=76, pwdata=3d
Write: paddr=76, pwdata=3d
PASS: Addr=76, Data=3d
Write: paddr=6d, pwdata=8c
Write: paddr=6d, pwdata=8c
PASS: Addr=6d, Data=8c
Write: paddr=79, pwdata=c6
Write: paddr=79, pwdata=c6
PASS: Addr=79, Data=c6
ERROR: Addr=c5, Expected=aa, Got=c6
Write: paddr=65, pwdata=77
Write: paddr=65, pwdata=77
PASS: Addr=65, Data=77
Test 5: Address Walking Ones
Write: paddr=01, pwdata=aa
Write: paddr=01, pwdata=aa
PASS: Addr=01, Data=aa
Write: paddr=02, pwdata=aa
Write: paddr=02, pwdata=aa
PASS: Addr=02, Data=aa
Write: paddr=04, pwdata=aa
Write: paddr=04, pwdata=aa
PASS: Addr=04, Data=aa
Write: paddr=08, pwdata=aa
Write: paddr=08, pwdata=aa
PASS: Addr=08, Data=aa
Write: paddr=10, pwdata=aa
Write: paddr=10, pwdata=aa
PASS: Addr=10, Data=aa
Write: paddr=20, pwdata=aa
Write: paddr=20, pwdata=aa
PASS: Addr=20, Data=aa
Write: paddr=40, pwdata=aa
Write: paddr=40, pwdata=aa
PASS: Addr=40, Data=aa
PASS: Addr=80, Data=aa

Image_o.hex

a3
7b
12
f9
5c
e4
2d
91
c8
36
b0
4f
d7
1a
8e
65
fd
29
b4
0c
76
e2
53
9a
c1
38
af
14
8b
60
d5
2e
97
c3
4a
be
07
81
f6
3d
a9
22
78
e0
5B
c4
19
92
f8
31
a6
0f
84
db
46
bc
25
9e
f3
68
d0
1b
72
e9
54
ca
33
a8
1d
86
fd
48
b2
09
7e
e5
50
c7
2c
93
f9
34
ab
16
8c
61
d8
43
ba
05
7f
e6
51
c8
2d
94
fa
35
ac
17
8d
62
d9
44
bb
06
80
e7
52
c9
2e
95
fb
36
ad
18
8e
63
da
45
bc
07
81
e8
53
ca
2f
96

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