0
Course name
Digital Logic Design Lab
Lab Report
Submitted By
Submitted To
Noshin Un Noor
Department of Computer Science & Engineering
Experiment: 01 Design a Full Adder circuit in circuit verse
from half adder.
Ans:
1
Half Adder:
Full Adder From 2 Half Adder:
Truth Table:
A B Cin Sum Carry
0 0 0 0 0
0 0 1 1 0
2
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Experiment: 02 Design and Implement the following BCD
to 7-Segment Display with truth table.
Ans:
Following Circuit:
3
Truth Table:
Hex-Decimal A B C D a b c d e f g Display
Digit pattern
like
0 0 0 0 0 1 1 1 1 1 1 0 0
1 0 0 0 1 0 1 1 0 0 0 0 1
2 0 0 1 0 1 1 0 1 1 0 1 2
3 0 0 1 1 1 1 1 1 0 0 1 3
4
4 0 1 0 0 0 1 1 0 0 1 1 4
5 0 1 0 1 1 0 1 1 0 1 1 5
6 0 1 1 0 1 0 1 1 1 1 1 6
7 0 1 1 1 1 1 1 0 0 0 0 7
8 1 0 0 0 1 1 1 1 1 0 1 8
9 1 0 0 1 1 1 1 1 0 0 1 9
A 1 0 1 0 X X X X X X X X
B 1 0 1 1 X X X X X X X X
C 1 1 0 0 X X X X X X X X
D 1 1 0 1 X X X X X X X X
E 1 1 1 0 X X X X X X X X
F 1 1 1 1 X X X X X X X X
Few of the BCD to 7-Segment display Outputs are:
5
6
Experiment: 04 Design and Implement the following 4-bit
binary adder including truth table.
Ans:
Four full adders in series:
4-BIT BINARY ADDER TRUTH TABLE:
A3 A2 A1 A0 B3 B2 B1 B0 Cin S3 S2 S1 S0 Cout
0000 0000 0 0000 0
0000 0001 0 0001 0
0001 0001 0 0010 0
0010 0011 0 0101 0
1111 0001 0 0000 1
1010 0101 0 1111 0
7
1111 1111 0 1110 1
1111 1111 1 1111 1
