FINFET TECHNOLOGY

Chapter 1

INTRODUCTION
As devices shrink further and further, the problems with conventional (planar) MOSFETs are increasing. Industry is currently at the 90nm node (i.e. DRAM half metal pitch, which corresponds to gate lengths of about 70nm). As we go down to the 65nm, 45nm, etc nodes, there seem to be no viable options of continuing forth with the conventional MOSFET. Severe short channel effects (SCE) such as VT rolloff and drain induced barrier lowering (DIBL), increasing leakage currents such as subthreshold S/D leakage, D/B (GIDL), gate direct tunneling leakage, and hot carrier effects that result in device degradation is plaguing the industry (at the device level; there are other BEOL (back-end of the line) problems such as interconnect RC delays which we wont discuss here). Reducing the power supply Vdd helps reduce power and hot carrier effects, but worsens performance. Performance can be improved back by lowering VT but at the cost of worsening S/D leakage. To reduce DIBL and increase adequate channel control by the gate, the oxide thickness can be reduced, but that increases gate leakage. Solving one problem leads to another. Efforts are on to find a suitable high-k gate dielectric so that a thicker physical oxide can be used to help reduce gate leakage and yet have adequate channel control, but this search has not been successful to the point of being usable. There are problems with band alignment (w.r.t Si) and/or thermal instability problems and/or interface states problems (with Si). The thermal instability problem has led researchers to search for metal gate electrodes instead of polysilicon (because insufficient activation leads to poly depletion effects). But metal gates with suitable work functions havent been found to the point of being usable. In the absence of this, polysilicon continues to be used, whose work function demands that VT be set by high channel doping. High channel doping in turn leads to random dopant fluctuations (at small gate lengths) as well as increased impurity scattering and therefore reduced mobility. Indeed, it is felt that instead of planar MOSFETs, a double gate device will be needed at gate lengths below 50nm in order to be able to continue forth on the shrinking path. 1.1 SCALING OF BULK CMOS Scaling planar CMOS to 10nm and below would be exceptionally difficult but not completely impossible, due to electrostatics, excessive leakages, mobility degradation, and many realistic fabrication issues. Particularly, control of leakage in a nano scale transistor would be critical

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FINFET TECHNOLOGY to high performance chips such as microprocessors. Non-planar MOSFETs provide potential advantages in packing density, carrier transport, and device scalability.

Fig 1.1: Comparison between Bulk CMOS and SOI CMOS 1.2 DG-MOSFET Double gate MOSFETs (DG-FET) is a MOSFET that has two gates to control the channel. Its schematic is shown in Fig. 1.2.

Fig. 1.2: Cross section of a generic planar DGFET Its main advantage is that of improved gate-channel control. In conjunction with ultra thin bodies in an SOI implementation (FDSOI DG-FET), it additionally offers reduced SCE, Dept. of E&C 2 CEC

FINFET TECHNOLOGY because all of the drain field lines are not able to reach the source. This is because the gate oxide has a lower dielectric constant than Si (assuming the oxide is SiO2), and also because the body is ultra thin. Because of its greater resilience to SCE and greater gate-channel control, the physical gate thickness can be increased (compared to planar MOSFET). Thus it also brings along reduced leakage currents (gate leakage as well as S/D leakage). There are 2 kinds of DG-FETs: Symmetric Asymmetric

Symmetric DG-FETs have identical gate electrode materials for the front and back gates (i.e. top and bottom gates). When symmetrically driven, the channel is formed at both the surfaces. In an asymmetric DG-FET, the top and bottom gate electrode materials can differ (eg. n+ poly and p+ poly). When symmetrically driven this would end up forming a channel on only one of the surfaces. Both have their advantages and disadvantages. Recent work regarding them will be described in a later section in this report. Energy band diagrams for symmetrical and asymmetrical DG-FETs are shown in Figures 1.3 and 1.4

Fig.1. 3: Symmetrical DGFET energy band diagram

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FINFET TECHNOLOGY

Fig. 1.4: Asymmetrical DGFET energy band diagram The biggest and perhaps the only stumbling block with DG-FETs is its fabrication. One can conceive of 3 ways to fabricate a DG-FET, labeled Types 1, 2 and 3 in Fig.1.5.

Fig1.5: Three possible realizations of DGFETs

Types 1 and 2 suffer most from fabrication problems, viz. it is hard to fabricate both gates of the same size and that too exactly aligned to each other. Also, it is hard to align the source/drain regions exactly to the gate edges. Further, in Type 1 DG-FETs, it is hard to provide a low-resistance, area-efficient contact the bottom gate, since it is buried.

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FINFET TECHNOLOGY

1.3 FinFET
Type 3 DG-FETs are called FinFETs. Even though current conduction is in the plane of the wafer, it is not strictly a planar device. Rather, it is referred to as a quasi-planar device, because its geometry in the vertical direction (viz. the fin height) also affects device behavior. Amongst the DG-FET types, the FinFET is the easiest one to fabricate. Its schematic is shown in Fig. 1.6.

Fig. 1.6: FinFET structure, with dimensions marked Because of the vertically thin channel structure, it is referred to as a fin because it resembles a fishs fin; hence the name FinFET. A gate can also be fabricated at the top of the fin, in which case it is a triple gate FET. Or optionally, the oxide above the fin can be made thick enough so that the gate above the fin is as good as not being present. (This helps in reducing corner effects, discussed later in this report).

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FINFET TECHNOLOGY It should be noted that while the gate length L of a FinFET is in the same sense as that in a conventional planar FET, the device width W is quite different. W is defined as:
W 2 H fin T fin

where Hfin and Tfin are the fin height and thickness respectively (see Fig.1.6 above. Some literature refers to the fin thickness as the fin width). The reason for this is quite clear when one notices that W as defined above is indeed the width of the gate region that is in touch with (ie. in control of) the channel in the fin (albeit with a dielectric in between). This fact can especially be seen if one unfolds the gate (i.e. unwraps it). The above definition of device width is for a triple gate FinFET. If the gate above the fin is absent/ineffective, then the Tfin term in the above definition is taken out. On the surface, this freedom in the vertical direction (of increasing Hfin) is a much desired capability since it lets one increase the device width W without increasing the planar layout area! (Increasing W increases the Ion, a desirable feature). However, it will be seen in subsequent sections in this report, that there is a definite range (in relation to Tfin) beyond which Hfin should not be increased, else one encounters SCE.

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FINFET TECHNOLOGY

Chapter 2

BACKGROUND
The term FinFET was coined by University of California, Berkeley researchers to describe a non-planar, double-gate transistor built on an SOI substrate, based on the earlier DELTA (single-gate) transistor design. The distinguishing characteristic of the FinFET is that the conducting channel is wrapped around a thin silicon "fin," which forms the body of the device. The dimensions of the fin determine the effective channel length of the device. It has been demonstrated that digital logic circuits using FinFETs can be significantly more power-efficient than their counterparts implemented in bulk CMOS at the same gate length. Thus, directly translating bulk CMOS interconnects to FinFETs may also be expected to provide corresponding power savings. In the technical literature, FinFET is used somewhat generically to describe any fin-based, multi-gate transistor architecture regardless of number of gates. A 25-nm transistor operating on just 0.7 V was demonstrated in December 2002 by Taiwan Semiconductor Manufacturing Company. The "Omega FinFET" design, named after the similarity between the Greek letter "Omega" and the shape in which the gate wraps around the source/drain structure, has a gate delay of just 0.39 picosecond (ps) for the N-type transistor and 0.88ps for the P-type transistor (Figure 6).

Fig. 6: A double-gate FinFET

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Chapter 3

FinFET FABRICATION
The key challenges in FinFET fabrication are the thin, uniform fin and also in reducing the source-drain series resistance. FinFETs have broadly been reported to have been fabricated in 2 ways: Gate-first process: Here the gate stack is patterned/formed first, and then the source and drain regions are formed Gate-last process (also called replacement gate process): Here source and drain regions are formed first and then the gate is formed Fig.2.1 shows the FinFET fabrication process flow. As the starting material SOI wafer is used with a 400-nm thick buried oxide layer and 50-nm thick silicon film. The measured standard deviation of the silicon film thickness is around 20 A. Although the silicon film thickness determines the channel width, the variation is acceptable for the device uniformity. The larger source of process variation is the variation in gate length. As the gate length will vary process variation also vary. The CVD SI3N4 and SiO2 stack layer is deposited on top of the silicon film to make a hard mask or cover layer. The fine Si-fin is patterned by electron beam (EB) lithography with 100 keV acceleration energy. The resist pattern is slightly ashed at 5 W and 30 sec for the reduction of the Si-fin width. Then, using top SiO2 layer as a hard etching mask, the SOI layer is etched. CVD SiO2 is deposited to make spacers around the S/D pads.. Making use of the difference in the heights, the SiO2 spacer on the sides of the Si-fin is completely removed by sufficient over etching of SiO2 while the cover layer protects the Si-fin. Then, boron-doped SI0.4Ge0.6 is deposited as the gate material. Because the source and drain extension is already formed and covered by thick SiO2 layer, no high temperature steps are required after gate deposition. Therefore, the structure is suitable to use with new high gate dielectric and metal gates that are not compatible with each other under high temperature.

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FINFET TECHNOLOGY

Fig.2.1: High level FinFET fabrication steps; (a-b): Gate-first process, (c-f): Gate last process

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FINFET TECHNOLOGY FinFETs are usually fabricated on an SOI substrate. It starts by patterning and etching thin fins on the SOI wafer using a hard mask. The hard mask is retained throughout the process to protect the fin. The fin thickness is typically half or one third the gate length, so it is a very small dimension. It is made by either e-beam lithography or by optical lithography using extensive line width trimming. In the gate-first process, fabrication steps after the fin formation are similar to that in a conventional bulk MOSFET process. In the gate-last process, the source/drain is formed immediately after fin patterning. To protect the fin while forming the other regions, doped poly or poly SiGe or even doped amorphous Silicon is deposited on the fin. Then the S/D fanout pads are patterned, leaving a thin slot between the source and the drain. This distance determines the gate length, which can be further reduced using a dielectric sidewall spacer. Finally the gate oxide is grown and the gate material is deposited and patterned. To create thin fins very close to each other, the sidewall image transfer (SIT) technique can be used. This technique can help obtain a fin pitch that is half the lithography pitch, which is desirable because: It improves device layout density (done by creating very close fins and using a trim level to break the gate continuity, thus separating devices), and It enables having the fin pitch smaller than the fin height, which is desirable because it make the FinFET have a greater effective device width than a planar conventional FET.

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FINFET TECHNOLOGY

Chapter 4

RECENT WORK ON FinFET

4.1 Fabrication efforts
Ultra thin fins result in better SCE, but increased series resistance. So a fine balance has to be achieved between the two goals. Also, the fabrication process has to be easily integrate-able into conventional CMOS process to the extent possible. Keeping such considerations in mind and others, there have been many efforts to fabricate and characterize FinFETs. Some of them are listed below. Hisamoto et al reported a gate-last process where they made FinFETs with10nm thick and 50nm tall fins, and 30nm gate length. The fins were patterned using e-beam lithography. The gate material was boron-doped Si0.4Ge0.6, which has the advantage that it is compatible with poly-Si process and its work function is continuously controllable by the mole fraction of Ge. Boron-doped Si0.4Ge0.6 results in a mid-gap work function. The gate was self-aligned to S/D, which was a raised source drain (RSD) structure to reduce series resistance. As was reported, a S/D first, gate-last process can be advantageous when used with a high-k gate dielectric, which mostly have thermal stability issues. Using a gate-first process, Collaert, et al fabricated FinFETs having (poly, not metal) gate lengths (Lpoly) of 25nm for nFETs and 35nm for pFETs, with 60-80nm tall fins, each being 10nm thick with a 1.6nm gate oxide EOT. The fins were patterned using e-beam lithography. The wafers underwent a H2 anneal to smoothen the fin surface and a 15nm oxidation to round the corners (more on corner effects later in this report). Selective epitaxy to create RSD was not used just to simplify the fabrication process, even though they would have lowered the series resistance. More recently, Kedzierski, et al fabricated a high performance FinFET using a gate-first process, with a 30nm gate length. Epitaxial RSD, highly angled S/D implants, and CoSi 2 silicidation were used to reduce series resistance. High performance nFETs and pFETs with ION of 1460uA/um and 850uA/um were reported. The fin thickness and height was 20nm and 65nm respectively, with a 1.6nm oxide. Many devices were fabricated to specifically study the effect of fin thickness and height on the series resistance. Devices were fabricated in the <100> as well as <110> direction. Fig. 8 shows a cross section.

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Fig.4.1: Electron micrographs of a <110> FinFET perpendicular to current flow

Effect of non-vertical fin sidewall

The fabrication of the uniform, ultra thin fin is one of the key challenges in FinFET fabrication. Due to non ideal anisotropic over etch, the fins can end up having a slightly triangular or trapezoidal shape. Concave and convex surfaces can also end up during the reactive ion etching (RIE) process. In [5], Wu et al assumed a trapezoidal shape and studied the effect of the various parameters of the trapezoid (slope of the sidewall, fin height, etc) on the subthreshold slope S and VT rolloff, using 3D device simulations. Assuming a constant top thickness (of the fin), S and VT rolloff worsens as the fin height is increased. This is because the thickness at the bottom increases, resulting in worsened SCE. It was reported that more than 50% profit from suppression of SCE can be gained, if the sidewall angle (w.r.t. horizontal) is controlled between 75 to 85.

Corner effects
In ultra thin triple gate (TG) FinFETs with a doped fin, the corners of the fin get inverted before the sidewalls of the fin get inverted. This is because the corners are under the influence of 2 gates (the top gate and one of the sidewall gates). This also makes the corners turn off later, as the gate voltage is ramped down. As a result, there is increased subthreshold leakage at the corners. There have been many efforts to study these corner effects and see

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FINFET TECHNOLOGY how they can be minimized. The unanimous conclusion in all these efforts has been that to minimize these corner effects, we need FinFETs with: Undoped fins Metal gates with appropriate work function for VT control Corners of fins should be rounded as much as possible (i.e. not sharp) FinFET circuits, layouts Along with efforts at the device level, there have been efforts to use FinFETs in circuits in an economic way (i.e. resulting in a quick TTM (time-to-market) as well as high yield). To this end, there have been efforts to build tools to convert existing planar CMOS layouts into FinFET layouts. A FinFET with multiple fins (N) has an effective device width given by:
Weff N 2 H fin T fin

When the fins are created using the SIT process, the number of fins created N is always an even number. It may be necessary to have an odd number of fins, in order to achieve the desired ratios (ratio of ON resistance), or to break fins to isolate devices. To create the fins using SIT, and to break fin loops, it is necessary to add 2 more levels in the fabrication process module. These are called the fin and the trim levels. A tool called FinGEN has been developed for converting existing planar designs into FinFET designs, to add the fin and trim levels. The tool is designed to be automatic, but needs manual intervention in some cases, eg. in cases where the transistors are severely sensitive for their functioning, such as SRAM cells. Device width quantization Because Weff varies in integral multiples of 2HFin + TFin, FinFET circuits inherently have a device width quantization problem. To illustrate this, suppose HFin and TFin are 30nm and 10nm respectively. Thus, Weff can be 70nm, 140nm, 210nm, etc. This renders it hard to get W/L ratios of say, 2.5 between 2 devices (eg. pFET and nFET in an inverter are usually sized such, to account for the mobility differences, in order to get equal rise/fall times). It is not clear how this is tackled in the literature. To cater to the cases where the fractional W/L ratio requirements are simply due to mobility differences as in the above example, there have been unpublished proposals to lighten this requirement by enhancing the mobility of pFETs in an alternate way, such as fabricating them in a <110> direction. Dept. of E&C 13 CEC

FINFET TECHNOLOGY Another way to solve the problem is to increase the gate length, which is lithographically controlled and hence doable. However this potentially reverses the benefits of shrinking. Layout density optimization Anil et al have come up [6] with ground rules that relate various layout dimensions, such as fin height and thickness, fin pitch, effective device width, and design rule margins. Equations giving minimum/maximum values have been derived, for both direct lithography patterning as well as SIT technique (spacer lithography). It was concluded that direct lithography puts more stringent demand on the required fin height, in order to be competitive with planar CMOS. This is not surprising because it is a known fact that the SIT technique can help create more fins in the same active area, compared to direct lithography.

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Chapter 5

CONCLUSION
FinFETs appear to be the device of choice in sub-50nm designs, because of their reduced short channel effects (SCE) and relative ease of integration into existing fabrication processes. They seem well suited to help us stay on track with Moores law, for a little while longer. A gate-first method of fabricating FinFETs is advantageous in that it is more akin to the conventional CMOS process. This is probably the reason why there is more literature on this method. On the other hand, a gate-last method of fabricating FinFETs is advantageous from a thermal stability point of view when introducing metal gates and high-k gate dielectrics. Tall, thin fins help minimize SCE, but tend to increase series resistance. For best SCE, keeping manufacturability in mind, the ideal dimensions reported are a fin thickness of one third the channel length. Tall fin heights are desirable because they yield higher ON currents (increased Weff), but it gets more difficult to manufacture them with uniformly steep sidewalls. So a fine balance needs to be struck. FinFETs need to be used with metal gates with appropriate work function, for yielding desired VT. Also, undoped fins need to be used to minimize corner effects. It was shown that Molybdenum with controlled Nitrogen doping is suitable for this. Fabrication techniques need to be improved to create thin fins with uniform thickness (uniformity across devices) as well as smooth, vertical sidewalls. These are necessary for consistent and high ON currents. Also, the parasitic series resistance needs to be brought down to acceptable levels. People have shown lowered series resistance with raised source-drain (RSD) using selective epitaxy, and also with high angle S/D implants. On the modeling front, compact models for FinFETs need to evolve more. Lastly, self heating problems, which are inherent in SOI devices and not limited to FinFETs, need to be handled before FinFETs can be adopted on a large scale.

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REFERENCES
1. A. Burenkov and J. Lorenz , Corner Effect in Double and Triple Gate FinFETs, ESSDERC 2003, pp. 135-138 2. P.M. Solomon et al, Two Gates are better than one, IEEE Circuits and Devices Magazine, Jan 2003, pp. 48-62 3. Yuan Taur, Analytic Solutions of Charge and Capacitance in Symmetric and Asymmetric Double-Gate MOSFETs, IEEE Trans. Electron Devices, vol. 48, pp. 28612869, Dec 2001 4. Digh Hisamoto et al, FinFETA Self-Aligned Double-Gate MOSFET Scalable to 20 nm, IEEE Trans. Electron Devices, vol. 47, pp. 2320-2325, Dec 2000 5. Xusheng Wu et al, Impact of Non-Vertical Sidewall on Sub-50nm FinFET, SOIC 2003, pp. 151-152 6. K. G. Anil et al, Layout Density Analysis of FinFETs, ESSDERC 2003, pp. 139-142

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