ANALOG & MIXED MODE VLSI DESIGN

DATA CONVERTERS – DAC Architectures

DR. B. H. V. S. Narayana Murthy

DAC Architectures
■ There are a wide varieties of DAC architectures that exist with their own merits and
demerits.
■ The DAC architectures that we would be studying are:
– Resistor string DAC
– R-2R DAC
– Current Steering DAC
– Charge Scaling DAC
– Cyclic DAC
– Pipeline DAC
■ The choice depends on particular application. In addition, the digital signal provided
as input in an application may not be always in binary.
■ We can have them in BCD, Gray Code, Thermometer Code, Sign Magnitude, 2’s
Complement mode and so on.
Comparison of Digital Input Codes

Point to Note
1. For converting Binary to Gray: 𝐺2 = 𝐵2 , 𝐺1 = 𝐵2 ⊕ 𝐵1 , 𝐺1 = 𝐵1 ⊕ 𝐵0
2. For 2’s complement, move from right side to left and leave the bits as they are until a ‘1’ is
encountered. Complement the remaining bits at LHS.
Diagram from Baker: fig. 29.1
 Resistor String DAC
■ Most basic DAC. Utilizes Resistor Divider Networks.
■ For, N bit DAC 2𝑁 number of resistors are used, and 𝑉𝑅𝐸𝐹 𝑖𝑠 𝑑𝑖𝑣𝑖𝑑𝑒𝑑 𝑖𝑛𝑡𝑜 (2𝑁 −
1) values.
■ The respective output voltage is selected by means of switch network.
■ A 𝑵 ∶ 𝟐𝑵 decoder is used to close respective switch in binary input.
■ For a 3 input DAC, if input is “000” then 𝑆0 gets closed and all switches remain
open.
■ For a 3 input DAC, if input is “001” then 𝑆0 gets opened and 𝑆1 gets closed.
■ This way, only one switch remains closed for a particular input word and all other
remain open.
■ The analog output is simply the DC voltage at the selected tap.
■ Therefore,
– 𝑉𝑜𝑢𝑡(min) = 0 𝑣𝑜𝑙𝑡𝑠 & 𝑉𝑜𝑢𝑡(max) = 𝑉𝐹𝑆
Advantages: Output is always monotonic.
Disadvantages: Only one out of 2𝑁 switches are ON at a time and others are OFF. The switches are constructed usually
with MOSFETS and switches that are off come in parallel, resulting parasitic capacitances which is prominent in higher
resolutions resulting in slower conversion speed.
Diagram from Baker: fig. 29.2
Resistor String DAC - Binary Switch Array for Capacitance Issue

■ The parasitic capacitances are reduced by slightly altering

resistor string arrangement as in figure.
■ Here, the total number of switches are:
1
2𝑁 2𝑁 2𝑁 1−( )𝑁
– 2𝑁 + + + ⋯+ = 2𝑁 2
1 = 2 × (2𝑁 − 1)
21 22 2𝑁−1 1−2

■ Even though the number of switches are increased, there is

no necessity of decoder in this case.
■ Due to the binary tree arrangement of the switch array, the
binary input itself is the input to switch array.
■ Here, Half the switches will always be ON in each column and
hence this results in reduction in parasitic capacitance and
resulting in the conversion speed increase.

Diagram from Baker: fig. 29.2

 Resistor String DAC - Disadvantage
■ An inherent disadvantage with the Resistor String DAC is power dissipation as the current keeps
flowing through the resistor string always.
■ For reducing power dissipation, the resistors value can be made larger, using the n-well resistors.
But, this is applicable only for lower resolutions.
■ As resolution increases, the relative accuracy of resistor becomes important, for which n-well
resistor may not be suitable. Thus, there is always a trade off in between power dissipation and
area.
 Resistor String DAC – Mismatch Errors

■ Voltage at 𝒊𝒕𝒉 resistor of the DAC is given by:

𝒊
– 𝑽𝒊(𝒊𝒅𝒆𝒂𝒍) = × 𝑽𝑹𝑬𝑭 … 𝟏 where ( i = 0, 1, 2, ………., 𝟐𝑵 − 𝟏 )
𝟐𝑵

■ But the accuracy of DAC is directly related to accuracy of value of R. Hence, the mismatch
results in larger INL and DNL.
■ Let the 𝑖 𝑡ℎ resistor in the string has mismatch error, such that
– 𝑹𝒊 = 𝑹 + ∆𝑹𝒊
■ Let us also assume that the mismatches are symmetrical about the string, so that:
𝑵
– σ𝟐𝒊=𝟏 ∆𝑹𝒊 = 0
■ This means that the total mismatch in the string is zero. It is also assumed that if one resistor
has increase in value, then the other one decreases such that the collective resistance remains
ideal which is 𝟐𝑵 × 𝑹.
 Resistor String DAC – Mismatch Errors

■ Therefore, the voltage at 𝒊𝒕𝒉 resistor is given by:

σ𝒊𝒌=𝟏 𝑹𝒌 σ𝒊𝒌=𝟏(𝑹+∆𝑹𝒌 ) 𝑽𝑹𝑬𝑭
– 𝑽𝒊 = 𝑵 × 𝑽𝑹𝑬𝑭 = × 𝑽𝑹𝑬𝑭 = ( 𝒊𝑹 + σ𝒊𝒌=𝟏 ∆𝑹𝒌 )
σ𝟐𝒌=𝟏 𝑹𝒌 𝟐𝑵 ×𝑹 𝟐𝑵 ×𝑹
𝒊.𝑽𝑹𝑬𝑭 𝑽𝑹𝑬𝑭
– Solving further: 𝑽𝒊 = + σ𝒊𝒌=𝟏 ∆𝑹𝒌 … 𝟐
𝟐𝑵 𝟐𝑵 ×𝑹
𝑽𝑹𝑬𝑭
– From (1) it can be written as: 𝑽𝒊 = 𝑽𝒊(𝒊𝒅𝒆𝒂𝒍) + σ𝒊𝒌=𝟏 ∆𝑹𝒌 … (3)
𝟐𝑵 ×𝑹
 Resistor String DAC – INL

■ INL is difference between actual and ideal switching points.

– 𝑰𝑵𝑳 = 𝑽𝒊 − 𝑽𝒊(𝒊𝒅𝒆𝒂𝒍)
■ Using equation (3), INL can be written as:
𝑽𝑹𝑬𝑭 ∆𝑹𝒌
– 𝑰𝑵𝑳 = σ𝒊𝒌=𝟏 … (4)
𝟐𝑵 𝑹

■ As it is assumed that the mismatches gets summed down to zero in complete string, it is
appropriate to assume maximum INL occurs at mid point of the string. This means: 𝐼𝑁𝐿𝑚𝑎𝑥
occurs at 𝑖 = 2𝑁−1 .
𝑽𝑹𝑬𝑭 𝑵−𝟏 ∆𝑹𝒌
■ Therefore, ȁ𝑰𝑵𝑳ȁ𝒎𝒂𝒙 = σ𝟐𝒌=𝟏 … (5)
𝟐𝑵 𝑹
 Resistor String DAC – DNL
■ DNL is difference between actual and ideal step heights.
𝒊.𝑽𝑹𝑬𝑭 𝑽𝑹𝑬𝑭 (𝒊−𝟏).𝑽𝑹𝑬𝑭 𝑽𝑹𝑬𝑭
– 𝑽𝒊 − 𝑽𝒊−𝟏 = + σ𝒊𝒌=𝟏 ∆𝑹𝒌 - + σ𝒊−𝟏
𝒌=𝟏 ∆𝑹𝒌
𝟐𝑵 𝟐𝑵 ×𝑹 𝟐𝑵 𝟐𝑵 ×𝑹
■ Solving further,
𝑽𝑹𝑬𝑭 𝟏 𝟏
– 𝐕𝐢 − 𝐕𝐢−𝟏 = 𝒊+ σ𝐢𝐤=𝟏 ∆𝐑 𝐤 − 𝐢 − 𝟏 − σ𝐢−𝟏
𝐤=𝟏 ∆𝐑 𝐤
𝟐𝑵 𝐑 𝑹
𝑽𝑹𝑬𝑭 ∆𝑹𝒊
– i.e., 𝑽𝒊 − 𝑽𝐢−𝟏 = 𝟏+ … (6)
𝟐𝑵 𝑹
■ DNL Therefore can be obtained as:
𝑽𝑹𝑬𝑭 ∆𝑹𝒊 𝑽𝑹𝑬𝑭
– 𝑫𝑵𝑳𝒊 = 𝟏+ −
𝟐𝑵 𝑹 𝟐𝑵
𝑽𝑹𝑬𝑭 ∆𝑹𝒊
– 𝑫𝑵𝑳𝒊 = × … (7)
𝟐𝑵 𝑹
■ The maximum value of DNL will occur at value of “i” where ∆𝑅 is maximum.
 R-2R DAC

■ R-2R ladder network is at the input as shown.

■ Advantage:
– It contains less number of resistors when compared to Resistor String DAC.
– Here, the number of resistors equals 2𝑁 + 1 where it was 2𝑁 in the earlier one.

Diagram from Baker: fig. 29.5

 R-2R DAC

■ Working principle of DAC is as below:

– When the bit input is ‘0’, the switch gets connected to ground.
– When the bit input is ‘1’, the switch gets connected to inverting input of OPAMP.
𝑅𝐹
– The output voltage is given by: 𝑉𝑜𝑢𝑡 = − 𝑅𝑖
× 𝑉𝑅𝐸𝐹

■ However, for finding "𝑅𝑖 “ for input bit combination, Thevenin’s theorem has to be applied for each
binary input. Thus output voltage is given by:
– 𝑣𝑂𝑈𝑇 = −𝑖 𝑇𝑂𝑇 × 𝑅𝐹
𝑉 1
– Where, 𝑖 𝑇𝑂𝑇 = σ𝑁−1
𝑘=0 𝐷𝑘
𝑅𝐸𝐹
2𝑁−𝑘 2𝑅
Diagram from Baker: fig. 29.5
 R-2R DAC

■ When all the input bits are ‘0’ all the 2R resistors are connected to ground.
■ Hence, 𝑖 𝑇𝑂𝑇 = 0, due to the virtual ground and thus 𝑣𝑜𝑢𝑡 = 0.
■ When all the input bits are ‘1’,
– 𝑣𝑜𝑢𝑡 = −𝑉𝐹𝑆
– 𝑣𝑜𝑢𝑡(𝐹𝑆) = − 2𝑁 −1ൗ × 𝑉𝑅𝐸𝐹 iff 𝑅𝐹 = 2𝑅
2𝑁

■ The OPAMP is used here as a buffer and hence the value of the output voltage can be scaled to
any desired value, by appropriate choice of 𝑅𝐹 .
Diagram from Baker: fig. 29.5
 R-2R DAC

■ Just like the resistor string architecture, R-2R DAC also requires good matching.
■ In addition, the architecture contains switches with finite resistance.
■ The switch resistance comes in series with 2R and hence results in an error.
■ To eliminate the same, dummy switches have to be included in the network as shown.
■ Here, the switch resistance is designated as ∆𝑅 and hence the resistance of dummy switch must be
always ∆𝑅Τ2 and must be always ON.
∆𝑅
■ Hence, the total resistance 𝑅′ = 𝑅 + 2
𝑎𝑛𝑑 2𝑅 ′ = 2𝑅 + ∆𝑅 . Thus, 𝑅 ′ − 2𝑅 ′ relationship is
maintained.
Diagram from Baker: fig. 29.6
 Current steering DAC

■ This DAC uses current instead of voltage for conversion process and hence the term current steering.
■ Current sources are used along with the switches as shown.
■ The circuit is in current sinking mode, in which, 𝟐𝑵 − 𝟏 current sources are present.
■ As there is no current being steered when all input bits are 0, we require one current source less
than 𝟐𝑵 .
■ When each source has a unit value ‘I’, the output current will have a range of: 𝟎 ≤ 𝒊𝒐𝒖𝒕 ≤ 𝟐𝑵 − 𝟏 𝑰

Diagram from Baker: fig. 29.9

 Current steering DAC
■ Now, as all the current sources in parallel, the binary code cannot be used in this case.
■ Instead, this converter utilizes thermometer code, in which current source gets switched in
parallel with previous one.
■ Hence, current keeps increasing from 0 till 𝟐𝑵 − 𝟏 𝑰.
■ Therefore, the converter requires a thermometer encoder, in addition to current sources.
■ The scheme of conversion for 3 bit DAC is as illustrated.

Diagram from Baker: fig. 29.11

 Current steering DAC
■ To avoid thermometer encoder and reduce number of current sources, the architecture is
altered such that binary weighted current sources are used.

■ In this case, only ‘N’ current sources are used,

in which current source’s rating is twice the
previous configuration.
■ Hence output current is:𝟎 ≤ 𝒊𝒐𝒖𝒕 ≤ 𝟐𝑵 − 𝟏 𝑰

■ The limitation with this architecture is size of current source at MSB.

■ For a 16 bit generic current steering DAC, number of current source required is 216 − 1 = 65535. Due to
this enormous area in die is occupied.
■ In contrast, the binary weighted current steering DAC requires only 16 current sources. But, the MSB
current is 216−1 . 𝐼 = 32768. I
■ For I = 5 µA, then MSB current would be 32768 x 5 µA = 163.84 mA, which is quite large within the chip.
Diagram from Baker: fig. 29.10
 Current steering DAC
■ As the current steering DACs have the high-current drive, the output buffers are not necessary.
■ Hence, these DACs are used in high-speed applications.

■ Limitation:
– There is a possibility of occurrence of glitches due to switching ON and OFF of current
sources.
 Current steering DAC – Mismatch Errors
■ Generic Current-Steering DAC:
– The analysis is similar to that of Resistor String DAC. I
– Assumption: 𝑰𝒌 = 𝑰 + ∆𝑰𝒌 for (𝑘 = 1, 2, 3, … … … , 2𝑁 − 1) where I is the ideal value and
∆𝑰𝒌 is the error due to mismatch,
𝟐 𝑵−𝟏
■ It can be again assumed: σ𝒌=𝟏 ∆𝑰𝒌 = 𝟎
■ Here, one half of the current sources will have maximum positive mismatch and other half will
have maximum negative mismatch. Thus, the worst case condition is at mid-scale, where
current is given by:
𝑁−1
– 𝐼𝑜𝑢𝑡 = σ2𝑘=1 𝐼 + ∆𝐼𝑘 = 2𝑁−1 . 𝐼 + 2𝑁−1 . ȁ∆𝐼ȁ𝑚𝑎𝑥 (or) 𝑰𝒐𝒖𝒕 = 𝑰𝒐𝒖𝒕 𝒊𝒅𝒆𝒂𝒍 + 𝟐𝑵−𝟏 . ȁ∆𝑰ȁ𝒎𝒂𝒙
■ Therefore, ȁ𝐼𝑁𝐿ȁ𝑚𝑎𝑥 is given by
– ȁ𝐼𝑁𝐿ȁ𝑚𝑎𝑥 = 𝐼𝑜𝑢𝑡(𝑖𝑑𝑒𝑎𝑙) + 2𝑁−1 . ȁ∆𝐼ȁ𝑚𝑎𝑥 − 𝐼𝑜𝑢𝑡 𝑖𝑑𝑒𝑎𝑙 = 𝟐𝐍−𝟏 . ∆𝐈 𝐦𝐚𝐱,𝑰𝑵𝑳
1
■ The maximum tolerable INL is 𝐿𝑆𝐵 and each current source represents 1 LSB.
2
𝑰 𝑰
■ Therefore, ȁ𝐈𝐍𝐋ȁ𝒎𝒂𝒙 = = 𝟐𝑵−𝟏 . ∆𝑰 𝒎𝒂𝒙,𝑰𝑵𝑳 => ∆𝑰 𝒎𝒂𝒙,𝑰𝑵𝑳 =
𝟐 𝟐𝑵
 Current steering DAC – Mismatch Errors
5 µA
■ If N=12 and I = 5 µA, then ∆𝑰 𝒎𝒂𝒙,𝑰𝑵𝑳 = = 𝟏. 𝟐𝟐𝟏 𝒏𝑨.
𝟐𝟏𝟐

■ This means that each current source must lie in between 𝟒. 𝟗𝟗𝟖𝟕𝟕𝟗 µA ≤ 𝑰𝒌 ≤ 𝟓. 𝟎𝟎𝟏𝟐𝟐𝟏 µA.
■ Thus, the current sources have to be highly precise.
■ DNL is given by the actual step height minus the ideal step height.
– Therefore, ȁ𝑫𝑵𝑳ȁ𝒎𝒂𝒙 = 𝑰𝒌 + ȁ∆𝑰ȁ𝒎𝒂𝒙 − 𝑰𝒌
– Or, ȁ𝑫𝑵𝑳ȁ𝒎𝒂𝒙 = ȁ∆𝐈ȁ𝐦𝐚𝐱
𝟏
■ As this is tolerable to LSB,
𝟐
𝑰
– ȁ𝑫𝑵𝑳ȁ𝒎𝒂𝒙 = ȁ∆𝐈ȁ𝒎𝒂𝒙 =
𝟐
𝑰
– ȁ∆𝐈ȁ𝐦𝐚𝐱,𝑫𝑵𝑳 =
𝟐

■ Thus, it can be seen that the DNL requirement is much less stringent than that of INL, for
generic DAC.
 Current steering DAC – Mismatch Errors
■ Binary Weighted Current-Steering DAC:
– σ𝑵 𝒌=𝟏 ∆𝑰𝒌 = 𝟎, then the current source corresponding to MSB must have maximum
positive mismatch error and the remainder of the bits contain the maximum negative
mismatch error.
■ Therefore, INL is given by:
– ȁ𝐈𝐍𝐋ȁ𝒎𝒂𝒙= (𝟐𝐍 −𝟏). 𝑰 + ∆𝑰 𝒎𝒂𝒙,𝑰𝑵𝑳 − 𝟐𝑵−𝟏 . 𝑰
– Or, ȁ𝐈𝐍𝐋ȁ𝒎𝒂𝒙 = 𝟐𝐍−𝟏 ∆𝑰 𝒎𝒂𝒙,𝑰𝑵𝑳

■ This is same as that of generic current steering DAC.

■ The DNL here is different because of binary weighting and the incremental change is non
uniform,
■ However, the worst case condition occurs at mid scale where the transition is from 01111…111
to 10000…000.
 Current steering DAC – Mismatch Errors
■ The worst case DNL is given by:
– 𝑫𝐍𝐋𝒎𝒂𝒙 = 𝟐𝐍−𝟏 . 𝑰 + ∆𝑰 𝒎𝒂𝒙,𝑰𝑵𝑳 − σ𝑵−𝟐
𝒌=𝟎 𝟐
𝒌 𝑰 + ∆𝑰
𝒎𝒂𝒙,𝑰𝑵𝑳 −𝑰

■ Solving, we get:
– 𝑫𝑵𝑳= (𝟐𝐍 −𝟏) ∆𝑰 𝒎𝒂𝒙
1
■ Equating this to 𝐿𝑆𝐵,
2
𝑰
– ∆𝑰 𝒎𝒂𝒙,𝑫𝑵𝑳 =
𝟐(𝟐𝑵 −𝟏)
𝑰
– Or, ∆𝑰 𝒎𝒂𝒙,𝑫𝑵𝑳 =
(𝟐𝑵+𝟏 −𝟐)

■ It can be inferred that DNL requirement for the binary weighted DAC is more stringent than INL.
 Charge Scaling DAC

■ The architecture is similar to that of binary weighted current steering DAC except that capacitors are
used instead of current sources.
■ When all input bits are ‘0’ all capacitors are connected to ground & output voltage is zero.
■ For each input bits are ‘1’ the corresponding capacitor gets connected to 𝑉𝑅𝐸𝐹 .
■ The other capacitors connected to ground become parallel and effective capacitance becomes in
series with one connected to 𝑉𝑅𝐸𝐹 .
Diagram from Baker: fig. 29.12
 Charge Scaling DAC
■ When MSB is high and all other bits are low, the output voltage is produced by voltage divider
network and it is given by:
2𝑁−1 .𝐶 2𝑁−1 2𝑁−1
– 𝑣𝑜𝑢𝑡 = 𝑉𝑅𝐸𝐹 × = 𝑉𝑅𝐸𝐹 × 2𝑁 −1
= 𝑉𝑅𝐸𝐹 ×
(2𝑁−1 +2𝑁−2 +⋯+2+1+1).𝐶 1+1( 2−1 ) 2𝑁
𝑉𝑅𝐸𝐹
– 𝑣𝑜𝑢𝑡 =
2
■ The equivalent circuit is as shown:

■ Output voltage for the 𝑘𝑡ℎ ‘1’ bit is given by:

2𝑘 .𝐶
– 𝑣𝑜𝑢𝑡 = × 𝑉𝑅𝐸𝐹 = 2𝑘−𝑁 × 𝑉𝑅𝐸𝐹
2𝑁.𝐶

■ 𝒗𝒐𝒖𝒕 = σ𝑵−𝟏
𝒌=𝟎 𝑫𝒌 × 𝟐
𝐤−𝑵 × 𝑽
𝑹𝑬𝑭

Diagram from Baker: fig. 29.12

 Charge Scaling DAC - Limitations
■ The limitation of the architecture is value of MSB Capacitor is quite large.
■ For a 16-bit DAC , if unit capacitor is chosen as 0.5 pF, then 𝐶𝑀𝑆𝐵 = 216−1 × 0.5𝑝𝐹 = 16.384 𝑛𝐹.
■ In 2 µ𝑚 process, the capacitance between poly-1 and poly-2 is nominally 500 aF/µ𝑚2 .
■ Therefore, the area occupied by this capacitor is 16.384 n/500 a = 32.768 × 106 µ𝑚2 ≈ 30 𝑚𝑖𝑙𝑙𝑖𝑜𝑛 µ𝑚2 .
■ Therefore, there is a need to reduce the area occupied by the capacitor. This is done by modifying the
architecture using split array.
 Split Array Charge Scaling DAC

■ Unlike previous one where 6-bit DAC should have had capacitor as 32C whereas here we will have
only 4C reducing the capacitor value gets reduced by 8 times.
■ The reduction in value of MSB Capacitor is achieved by splitting capacitor array in two parts, by
inserting an “attenuation capacitor” in between.
■ Value of capacitor is chosen such that, when all input bits are ‘0’, the series combination of this
value and LSB array’s value is equal to C. For 6 Bit Array,
𝑆𝑢𝑚 𝑜𝑓 𝐿𝑆𝐵 𝑎𝑟𝑟𝑎𝑦 8
■ 𝐶𝑎𝑡𝑡𝑒𝑛 = ×𝐶 𝐶𝑎𝑡𝑡𝑒𝑛 =
7
×𝐶
𝑆𝑢𝑚 𝑜𝑓 𝑀𝑆𝐵 𝑎𝑟𝑟𝑎𝑦

Diagram from Baker: fig. 29.14

Layout Considerations for Charge Scaling DAC
■ Due to the reason that Charge Scaling DAC
requires ratioed capacitors, the ratio must
be precisely maintained in the layout. But
during fabrication, the “undercutting” of
mask causes an error in the value of
capacitor as shown.

■ The problem can be solved by constructing

the capacitors out of unit capacitance.
Thus, undercutting affects all capacitors in
same way.

■ If there is a process gradient errors in oxide

growth, then even this layout is affected
which can be solved by employing the
common centroid scheme.
Diagram from Baker: fig. 29.14
Cyclic DAC
■ A summer adds either "𝑉𝑅𝐸𝐹 " or "GND“ to
the feedback signal, based on input bit.
■ The feedback signal is derived by means of
an amplifier with a gain of 0.5. The
feedback signal itself is taken as analog
input.
■ The advantage with this DAC is that its
resolution can be configured for any value
of N.

𝟏 𝒗𝑨 𝒏−𝟏
■ The output voltage expression can be generalized as: 𝑽𝒐𝒖𝒕(𝒂𝒄𝒕𝒖𝒂𝒍) = 𝟐 𝑫𝒏−𝟏 . 𝑽𝑹𝑬𝑭 +
𝟐
■ The quick way to find actual output voltage is: 𝑽𝒐𝒖𝒕(𝒂𝒄𝒕𝒖𝒂𝒍) = 𝑽𝑹𝑬𝑭 σ𝑵−𝟏
𝒌=𝟎 𝑨
𝑵−𝒌
. 𝑫𝒌 where A = gain
■ Limitations:
– Takes “N” Cycles for N bit conversion and hence slower compared to parallel input DACs.
– Accuracy is dependent upon the gain of the amplifier and has to be highly precise at 50%.
Diagram from Baker: fig. 29.17
Pipeline DAC

■ The limitation of taking “N” clock cycles can be overcome by means of pipeline DAC which ‘N’ is
number of cyclic DAC stages are cascaded.
■ The initial N-clock cycle delay is present for the first input word. But, then onwards, a
conversion takes place for every clock cycle and hence DAC works much faster than the cyclic
DAC and its speed is almost comparable to parallel input DACs.
■ The DAC has limitation of using N-times more circuitry than that of cyclic DAC. Hence, there is a
trade off between speed and area. The output voltage of 𝑛𝑡ℎ stage is given by:
1
𝑣𝑜𝑢𝑡(𝑛) = 𝑉𝑅𝐸𝐹 . 𝐷𝑛−1 + 𝑣𝑜𝑢𝑡 𝑛−1
2
Diagram from Baker: fig. 29.19
CASE STUDY – Analog Devices AD5541/AD5542 16-Bit DACs

■ Single-channel, 16-bit, voltage-output DACs with serial input.

■ Supply voltage: 2.7 V to 5.5 V.
■ AD5541: Unipolar output
■ AD5542: Unipolar or bipolar output
■ Low power consumption: 0.625 mW at 5 V.
■ Fast settling time: 1 µs to ±0.0015% of full scale.
Diagram from AD Datatasheet
Analog Devices AD5541/AD5542 16-Bit DACs – Key Features

■ 16-bit resolution for high-precision output.

■ Unbuffered output, drives 60 kΩ loads.
■ SPI-compatible serial interface (3-wire for AD5541, 4-wire for AD5542).
■ Power-on reset to 0 V (unipolar mode).
■ Low glitch energy: 1.1 nV-sec.

Diagram from AD Datatasheet

Analog Devices AD5541/AD5542 16-Bit DACs – Key Features

■ INL: ±1 LSB max (linearity error).

■ DNL: ±1 LSB max (ensures monotonicity).
■ Gain Error: ±2 LSB at 25°C (output scaling accuracy).
■ Zero Code Error: ±0.7 LSB at 25°C (offset at 0 input).
■ Output Noise: 11.8 nV/√Hz at 1 kHz (low noise performance).

Diagram from AD Datatasheet

Analog Devices AD5541/AD5542 16-Bit DACs – Serial Interfaces

■ AD5541: 3-wire (CS, SCLK, DIN).

■ AD5542: 4-wire (adds LDAC for synchronous updates).
■ 16-bit data word, MSB first.
■ Data clocked on SCLK rising edge.

Diagram from AD Datatasheet

Analog Devices AD5541/AD5542 16-Bit DACs – Unipolar Output Configuration

■ Output range: 0 V to 𝑉𝑅𝐸𝐹 – 1 LSB.

■ Example: 𝑉𝑅𝐸𝐹 = 2.5 V → Full-scale output ≈ 2.5 V.
■ Used in applications like digital gain control.

Diagram from AD Datatasheet

Analog Devices AD5541/AD5542 16-Bit DACs – Unipolar Output Configuration

■ Output range: 0 V to 𝑉𝑅𝐸𝐹 – 1 LSB.

■ Example: 𝑉𝑅𝐸𝐹 = 2.5 V → Full-scale output ≈ 2.5 V.
■ Used in applications like digital gain control.

Diagram from AD Datatasheet

Analog Devices - Bipolar Output Operation (AD5542)

■ Output range: - 𝑉𝑅𝐸𝐹 to + 𝑉𝑅𝐸𝐹 – 1 LSB.

■ Requires external op-amp and resistors (𝑹𝑭𝑩 , 𝑹𝑰𝑵𝑽 )
■ Ideal for applications needing positive/negative signals.

Diagram from AD Datatasheet

 Case Study: Applications of AD5541/AD5542 and Interface with MPs

■ Automatic Test Equipment (ATE): Precise test signal generation.

■ Data Acquisition Systems: Sensor data to analog conversion.
■ Industrial Process Control: Control signals for automation.
■ Digital Gain/Offset Adjustment: Signal tuning.
■ Supports SPI, QSPI, MICROWIRE, and DSP interfaces.
■ Example: Interface with ADSP-21xx or [Link] precise timing and data formatting.

Diagram from AD Datatasheet

Case Study: Advanced Features and Considerations

■ Power-On Reset: Resets output to 0 V on startup.

■ Optocoupler Interface: Adds isolation for noisy environments.
■ Multiple DACs: Use CS to decode multiple AD5541/AD5542 units
Diagram from AD Datatasheet
CASE STUDY – Analog Devices AD5541/AD5542 16-Bit DACs
■ High-precision, low-power DACs with versatile interfacing.
■ Critical specs: INL, DNL, settling time.
Tutorial:

1. Design a 3-bit resistor-string ladder using a binary switch array. Assume that VREF = 5 V
and that the maximum power dissipation of the converter is to be 5 mW. Indicate the switch
positions for input code of 100.
2. Determine the resolution for a resistor string DAC, which is assumed to be limited by the
INL. The poly resistors have relative matching of 1% and Vref = 5 volts.
3. A 3 bit resistor string DAC was designed with a desired resistor of 500 ohms. After
fabrication, mismatch caused the actual value of resistors to be: 500 ohm, 480 ohm, 470
ohm, 520 ohm, 510 ohm, 490 ohm, 530 ohm and 500 ohm. These values are given from
the lower most resistor onwards. Determine the maximum INL and DNL for the DAC
assuming Vref = 5 volts.
4. An 8-bit resistor string DAC was fabricated with the resistor value of 1 kilo ohm. If the
process was able to provide the matching of within 1%, find the effective resolution of the
converter assuming Vref = 5 volts.
5. Design a 3 bit DAC using R-2R architecture with R=1 kilo ohm, Rf = 2 kilo ohm and Vref = 5
volts. Determine value of 𝑖 𝑇𝑂𝑇 for each digital input and corresponding 𝑣𝑜𝑢𝑡 . Indicate the
input code 001 in the circuit diagram.
Tutorial:

6. Obtain the transfer characteristics of a 3-bit R-2R DAC if all R=1.1 kilo ohm and 2R = 2 kilo
ohm. Assume Vref = 5 volts. What is the maximum INL and DNL of the converter?
7. Design a 3-bit current steering DAC with thermometer code. Assume that each current
source is 5 mA, and find the total output current for each input code. Repeat the same for
the binary weighted current steering DAC.
8. If a 10-bit binary weighted current source array has a unit source of 1 uA, determine the
tolerance of MSB current source, assuming a worst case DNL of ½ LSB.
9. A certain process is able to fabricate matched current sources to within 0.05%. Determine
the maximum resolution that a generic current steering DAC can attain using this process.
Repeat same for binary weighted current steering DAC.
10. Design an 8 bit current steering DAC using binary weighted current sources, with smallest
current sources having 1 uA. What is the range of values that the MSB current source can
have while maintaining INL of ½ LSB? Repeat same for DNL of ½ LSB.
Tutorial:

11. Design a 3-bit charge scaling DAC with Vref = 5 volts and C = 0.5 pF. Find the output voltage
for all input bit combinations. Show the equivalent networks for inputs 010 and 101.
12. Write the equivalent network to determine the output of the 6-bit charge scaling DAC for
following inputs: 101101, 010110. Assume Vref = 5 volts and C = 0.5 pF.
13. For the split array charge scaling 6 bit DAC deduce output voltage for following inputs:
10000, 000001.
14. Design a 4 bit charge scaling DAC using a split array. Assume that Vref = 5 volts and C = 0.5
pF. Draw equivalent network for each of the following input words and determine the output
voltage. D = 0001, 0010, 0100, 1000.
15. Show the value of output at the end of each cycle for 6 bit cyclic DAC, with input value of
110101 assuming Vref = 5 volts.
16. For a cyclic DAC, determine the gain error for a 3 bit conversion, if the feedback amplifier
has a gain of 0.45. Assume Vref = 5 volts. Find maximum INL and DNL.
17. Repeat Problem 16 for an offset voltage of 0.2 and gain 0.5.
18. Repeat the problem above with offset voltage 0.2 and gain 0.45
Practical Assignment

1. Use LTSpice to design DACS provided.

Reference:

1. CMOS Circuit Design, Layout, and Simulation, Jacob Baker, 4th edition.
2. Analog Devices Data Sheet for AD5541/AD5542 16-Bit DACs
Thank you