ECEG 1551 INDIVIDUAL ASSIGNMENT 5
1. Answer the following questions.
a. Explain why a half-adder is not suitable for all addition operation
and why a full-adder is needed instead.
b. With the aid of a diagram, show how a full adder can be
implemented from two half-adders.
2. Three 2-input multiplexers are connected as shown in the figure below;
a. Determine the truth table that describes the output, Z, for all
combinations of S1 and S0
b. What function is this circuit implementing?
3. Given a multiplexer circuit using lC 741LS51 as shown in the figure below,
determine the output value for the circuit, F, with respect to the given inputs
shown in the table shown below.
ECEG 1551 1
Inputs Output
A B C D F
0 1 1 0
1 0 1 0
0 0 1 1
1 1 1 1
0 0 0 1
1 1 1 0
4. You are required to design a decoder logic circuit that is used to drive a
seven-segment display, as shown in the figure below. The display is used to
display six alphabets: H, E, L, P, S, O. The table given below shows the
active segments for each alphabet.
Alphabet Segments Activated
H B,C,E,F,G
E A,D,E,F,G
L D,E,F
P A,B,E,F,G
S A,C,D,F,G
O A,B,C,D,E,F
The decoder circuit has 3 inputs: A0, A1 and A2 and seven outputs (A to G), one
for each segment of the seven-segment display. The below figure shows the
block diagram of the alphabet decoding logic. The relation between the input
combinations and the alphabet to be displayed is given in table shown below.
There are only six input combinations that will display the alphabets. The other
two input combinations can be ignored (don't care).
ECEG 1551 2
Inputs Alphabet to
be displayed
A2 A1 A0
0 0 0 H
0 0 1 E
0 1 0 L
0 1 0 P
1 0 0 S
1 0 1 O
a. Construct the truth table for the logic circuit showing all possible
input combinations and the corresponding values for the outputs A,
B, C, D, E, F, G.
b. Using Karnaugh maps, determine the minimized Boolean
expression for each output.
c. Draw the circuit diagram based on the minimized Boolean
expressions.
ECEG 1551 3
