TLV888, TLV2888

SBOSAG5A – DECEMBER 2024 – REVISED SEPTEMBER 2025

TLVx888 Low-Noise, Zero-Drift, Wide-Bandwidth, MUX-Friendly

Operational Amplifiers
1 Features The TLVx888 feature very fast settling time due
in part to the wide gain bandwidth and very high
• High dc precision:
slew rate. The settling time is further enhanced in
– Zero drift: 0.01μV/°C
multichannel systems by the proprietary MUX-friendly
– Low offset voltage: 3μV
input architecture.
– High PSRR: 150dB
– High CMRR: 150dB The combination of high precision, fast settling, and
• Excellent ac performance: low noise make the TLVx888 an excellent choice
– Gain bandwidth: 14MHz for a wide range of applications, including signal
– Slew rate: 40V/µs measurement, precision instrumentation, and data
– Low noise: 7.5nV/√Hz acquisition.
• Input to the negative rail, rail-to-rail output The TLVx888 are available in industry standard
• Low quiescent current: 1.5mA packages as well as micro-size packages to fit in the
• RFI/EMI filtered inputs most space-constrained applications. The devices are
• Supply range: 4.5V to 36V specified for operation from –40°C to +125°C.
• Temperature: –40°C to +125°C
Device Information
2 Applications PART NUMBER CHANNEL COUNT PACKAGE(1)

• PC PSU and game console unit D (SOIC, 8)

• Merchant DC/DC TLV888 Single DBV (SOT-23, 5)(2)
• Flow transmitter DRL (SOT, 5)(2)
• Pressure transmitter D (SOIC, 8)
• Merchant battery charger
DDF (SOT-23, 8)(2)
• Electricity meter TLV2888 Dual
DGK (VSSOP-8)
3 Description DSG (WSON-8)(2)

The TLV888, TLV2888, and TLV4888 (TLVx888) D (SOIC, 14)

TLV4888(2) Quad
are wide-bandwidth, low noise, zero-drift operational PW (TSSOP-14)
amplifiers (op amps). These op amps feature only
(1) For more information, see Section 10.
15µV of offset voltage (max) and 0.05µV/°C of offset (2) Preview information (not Production Data).
voltage drift (max) over a wide temperature range.

V+

+
TLVx888 VOUT

–
RSENSE
ISOURCE
RES11A −V

1k 1k

RL
1k
1k

REF

High-Side Current Shunt Monitor Application

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
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Table of Contents
1 Features............................................................................1 7 Application and Implementation.................................. 19
2 Applications..................................................................... 1 7.1 Application Information............................................. 19
3 Description.......................................................................1 7.2 Typical Applications.................................................. 22
4 Pin Configuration and Functions...................................2 7.3 Power Supply Recommendations.............................26
5 Specifications.................................................................. 4 7.4 Layout....................................................................... 26
5.1 Absolute Maximum Ratings........................................ 4 8 Device and Documentation Support............................28
5.2 ESD Ratings............................................................... 4 8.1 Device Support......................................................... 28
5.3 Recommended Operating Conditions.........................4 8.2 Documentation Support............................................ 28
5.4 Thermal Information: TLV888..................................... 5 8.3 Receiving Notification of Documentation Updates....28
5.5 Thermal Information: TLV2888................................... 5 8.4 Support Resources................................................... 28
5.6 Electrical Characteristics.............................................6 8.5 Trademarks............................................................... 29
5.7 Typical Characteristics................................................ 8 8.6 Electrostatic Discharge Caution................................29
6 Detailed Description......................................................15 8.7 Glossary....................................................................29
6.1 Overview................................................................... 15 9 Revision History............................................................ 29
6.2 Functional Block Diagram......................................... 15 10 Mechanical, Packaging, and Orderable
6.3 Feature Description...................................................15 Information.................................................................... 29
6.4 Device Functional Modes..........................................18

4 Pin Configuration and Functions

NC 1 8 NC

±IN 2 ± 7 V+

+IN 3 + 6 OUT

V± 4 5 NC

Not to scale

Figure 4-1. TLV888: D Package, 8-Pin SOIC (Top View)

Table 4-1. Pin Functions: TLV888

PIN
TYPE DESCRIPTION
NAME NO.
–IN 2 Input Inverting input
+IN 3 Input Noninverting input
NC 1, 8, 5 — No connection (can be left floating)
OUT 6 Output Output
V– 4 Power Negative (lowest) power supply
V+ 7 Power Positive (highest) power supply

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OUT A 1 8 V+

±IN A 2 7 OUT B

+IN A 3 6 ±IN B

V± 4 5 +IN B

Not to scale

Figure 4-2. TLV2888: D Package, 8-Pin SOIC and DGK Package, 8-pin VSSOP (Top View)

Table 4-2. Pin Functions: TLV2888

PIN
TYPE DESCRIPTION
NAME NO.
–IN A 2 Input Inverting input channel A
–IN B 6 Input Inverting input channel B
+IN A 3 Input Noninverting input channel A
+IN B 5 Input Noninverting input channel B
OUT A 1 Output Output channel A
OUT B 7 Output Output channel B
V– 4 Power Negative supply
V+ 8 Power Positive supply

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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VS Supply voltage 40 V
Common-mode (V–) – 0.5 (V+) + 0.5
Signal input voltage V
Differential (V+) – (V–)
Current ±10 mA
Output short circuit(2) Continuous
TA Operating temperature –55 150 °C
TJ Junction temperature 150 °C
Tstg Storage temperature –65 150 °C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) Short-circuit to ground, one amplifier per package.

5.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±250

(1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Single supply 4.5 36
VS Supply voltage, (V+) – (V–) V
Dual supply ±2.25 ±18
TA Operating temperature –40 125 °C

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5.4 Thermal Information: TLV888

TLV888
THERMAL METRIC(1) D (SOIC) UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance 144.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 81.9 °C/W
RθJB Junction-to-board thermal resistance 88.9 °C/W
ΨJT Junction-to-top characterization parameter 26.2 °C/W
ΨJB Junction-to-board characterization parameter 88.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

5.5 Thermal Information: TLV2888

TLV2888
THERMAL METRIC(1) D (SOIC) DGK (VSSOP) UNIT
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 132.3 158.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 72.2 53.0 °C/W
RθJB Junction-to-board thermal resistance 81.7 93.2 °C/W
ΨJT Junction-to-top characterization parameter 19.6 2.4 °C/W
ΨJB Junction-to-board characterization parameter 80.6 91.6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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5.6 Electrical Characteristics

at TA = 25°C, VS = 4.5V to 36V, VCM = VOUT = VS / 2, and RLOAD = 10kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
±3 ±15
VOS Input offset voltage(1) µV
TA = –40°C to +125°C ±20
dVOS/ Input offset voltage
TA = –40°C to +125°C ±0.01 ±0.05 µV/°C
dT drift(1)
Power-supply rejection
PSRR TA = –40°C to +125°C ±0.03 ±0.5 µV/V
ratio(1)
INPUT BIAS CURRENT
±50 ±350 pA
IB Input bias current(1)
TA = –40°C to +125°C ±7 nA
±100 ±600 pA
IOS Input offset current(1)
TA = –40°C to +125°C ±3 nA
NOISE
En Input voltage noise f = 0.1Hz to 10Hz 0.180 µVPP
f = 10Hz 7.6
Input voltage noise
en f = 100Hz 7.6 nV/√Hz
density
f = 1kHz 7.5
Input current noise
in f = 1kHz 175 fA/√Hz
density
INPUT VOLTAGE
VCM Common-mode voltage (V–) – 0.1 (V+) – 1.7 V
VS = ±2.25V 118 135
(V–) – 0.1V ≤ VCM ≤ (V+) – 1.7V
Common-mode VS = ±18V 140 150
CMRR dB
rejection ratio
(V–) – 0.1V ≤ VCM ≤ (V+) – 1.7V, VS = ±2.25V 118 130
TA = –40°C to +125°C(1) VS = ±18V 140 150
INPUT IMPEDANCE
Differential input
zid 100 || 1.6 MΩ || pF
impedance
Common-mode input
zic 1 || 1.9 TΩ || pF
impedance
OPEN-LOOP GAIN
VS = ±15V, 130 148
(V–) + 0.6V < VO < (V+) – 0.6V,
RLOAD = 10kΩ TA = –40°C to +125°C(1) 130
AOL Open-loop voltage gain dB
VS = ±15V, 130 144
(V–) + 1.7V < VO < (V+) – 1.7V,
RLOAD = 2kΩ TA = –40°C to +125°C(1) 130

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5.6 Electrical Characteristics (continued)

at TA = 25°C, VS = 4.5V to 36V, VCM = VOUT = VS / 2, and RLOAD = 10kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FREQUENCY RESPONSE
GBW Gain-bandwidth product 14 MHz
SR Slew rate Gain = 1, 10V step 40 V/µs
THD+ Total harmonic distortion
Gain = 1, f = 1kHz, VOUT = 4VRMS 0.00012%
N + noise
Crosstalk f = 100kHz 110 dB

VS = ±18V, gain = 1, To 0.1% 1

tS Settling time µs
10V step To 0.01% 15
tOR Overload recovery time VIN × gain = VS = ±18V 460 ns
OUTPUT
No load(1) 26 40
Positive rail,
RLOAD = 10kΩ 122 150
VS = 30V
RLOAD = 2kΩ 500 575
Voltage output swing
VO No load(1) 26 40 mV
from rail
Negative rail,
RLOAD = 10kΩ 120 135
VS = 30V
RLOAD = 2kΩ 515 575
RLOAD = 10kΩ, TA = –40°C to +125°C, both rails(1) 250
ISC Short-circuit current ±42 mA
CLOAD Capacitive load drive See Typical Characteristics pF
Open-loop output
ZO f = 1MHz 220 Ω
impedance
POWER SUPPLY
1.5 1.8
VS = ±2.25V (VS = 4.5V), IO = 0A
Quiescent current per TA = –40°C to +125°C(1) 1.5 1.9
IQ mA
amplifier 1.5 1.8
VS = ±18V (VS = 36V), IO = 0A
TA = –40°C to +125°C(1) 1.5 1.9

(1) Specification established from device population bench system measurements across multiple lots.

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5.7 Typical Characteristics

at TA = 25°C, VS = ±18V, VCM = VS / 2, and RL = 10kΩ (unless otherwise noted)

20

15

Amplifiers (%)
10

0
-15 -12 -9 -6 -3 0 3 6 9 12 15
Input Offset Voltage ( V)
70 units TA = 125°C, 70 units

Figure 5-1. Offset Voltage Distribution Figure 5-2. Offset Voltage Distribution
20 22.5

20
16 17.5

15
Amplifiers (%)

Amplifiers (%)

12
12.5

10
8
7.5

4 5

2.5

0 0
-0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 0.05 -350 -250 -150 -50 0 50 150 250 350
Input Offset Voltage Drift ( V/ C) Input Bias Current (pA)
TA = –40°C to +125°C, 70 units 70 units

Figure 5-3. Offset Voltage Drift Figure 5-4. Input Bias Current Distribution, IBN
20 20

17.5 17.5

15 15
Amplifiers (%)

Amplifiers (%)

12.5 12.5

10 10

7.5 7.5

5 5

2.5 2.5

0 0
-350 -250 -150 -50 50 150 250 350 -600 -400 -200 0 200 400 600
Input Bias Current (pA) Input Offset Current (pA)
70 units 70 units

Figure 5-5. Input Bias Current Distribution, IBP Figure 5-6. Input Offset Current Distribution

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5.7 Typical Characteristics (continued)

at TA = 25°C, VS = ±18V, VCM = VS / 2, and RL = 10kΩ (unless otherwise noted)

5 5
4 4
3 3
Input Offset Voltage ( V)

Input Offset Voltage ( V)

2 2
1 1
0 0
-1 -1
-2 VCM = −18.1V VCM = 16.3V -2 VCM = −18.1V VCM = 16.3V
-3 -3
-4 -4
-5 -5
-20 -15 -10 -5 0 5 10 15 20 -20 -15 -10 -5 0 5 10 15 20
Common-Mode Voltage (V) Common-Mode Voltage (V)
TA = 125°C

Figure 5-7. Offset Voltage vs Common-Mode Voltage Figure 5-8. Offset Voltage vs Common-Mode Voltage
5 5
4 4
3 3
Input Offset Voltage ( V)
Input Offset Voltage ( V)

2 2
1 1
0 0
-1 -1
-2 -2
-3 -3
-4 -4
-5 -5
-50 -25 0 25 50 75 100 125 150 0 4 8 12 16 20 24 28 32 36
Temperature ( C) Supply Voltage (V)
5 typical units 5 typical units

Figure 5-9. Offset Voltage vs Temperature Figure 5-10. Offset Voltage vs Supply Voltage
350 180 300
300 IBN Gain
IBP 160 Phase 240
250
IOS 140 180
200
Input Bias Current (pA)

150 120 120

100
100 60
Gain (dB)

Phase ( )

50
0 80 0
-50
60 -60
-100
-150 40 -120
-200 20 -180
-250
VCM = −18.1V VCM = 16.3V 0 -240
-300
-350 -20 -300
-20 -15 -10 -5 0 5 10 15 20 10m 100m 1 10 100 1k 10k 100k 1M 10M
Common-Mode Voltage (V) Frequency (Hz)

Figure 5-11. Input Bias Current vs Common-Mode Voltage Figure 5-12. Open-Loop Gain and Phase vs Frequency

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5.7 Typical Characteristics (continued)

at TA = 25°C, VS = ±18V, VCM = VS / 2, and RL = 10kΩ (unless otherwise noted)

60 700
650 IBN
600 IBP
40 IOS
550

Input Bias Current (pA)

500
20 450
Gain (dB)

400
0 350
300
-20 250
200
G = −1 150
-40 G= 1
100
G = 10
G = 100 50
-60 0
100 1k 10k 100k 1M 10M -50 -25 0 25 50 75 100 125
Frequency (Hz) Temperature ( C)

Figure 5-13. Closed-Loop Gain vs Frequency Figure 5-14. Input Bias Current and Offset Current vs
Temperature
18 -6
TA = −40 C
16.5 -7.5 TA = 25 C
TA = 85 C
15 -9 TA = 125 C
Output Voltage (V)
Output Voltage (V)

13.5 -10.5

12 -12

10.5 -13.5

9 TA = −40 C -15
TA = 25 C
7.5 TA = 85 C -16.5
TA = 125 C
6 -18
0 5 10 15 20 25 30 35 40 45 50 55 60 0 5 10 15 20 25 30 35 40 45 50 55 60
Output Current (mA) Output Current (mA)

Figure 5-15. Output Voltage Swing vs Figure 5-16. Output Voltage Swing vs
Output Current (Sourcing) Output Current (Sinking)
160 200
CMRR
Common-Mode Rejection Ratio (dB)

140 PSRR−
PSRR
120 180
Rejection Ratio (dB)

100

80 160

60

40 140

20

0 120
10m 100m 1 10 100 1k 10k 100k 1M 10M -50 -25 0 25 50 75 100 125 150
Frequency (Hz) Temperature ( C)
5 typical units

Figure 5-17. CMRR and PSRR vs Frequency Figure 5-18. CMRR vs Temperature

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5.7 Typical Characteristics (continued)

at TA = 25°C, VS = ±18V, VCM = VS / 2, and RL = 10kΩ (unless otherwise noted)

200
Power Supply Rejection Ratio (dB)

Input Voltage Noise (50nV/div)

180

160

140

120
-50 -25 0 25 50 75 100 125 150 10
Temperature ( C) Time (2s/div)
5 typical units

Figure 5-19. PSRR vs Temperature Figure 5-20. 0.1Hz to 10Hz Voltage Noise
100 1000
Voltage Noise Spectral Density (nV Hz)

70 Current Noise Spectral Density (fA Hz) 700

50 500

30 300
20 200

10 100
7 70
5 50

3 30
2 20

1 10
100m 1 10 100 1k 10k 100k 1 10 100 1k 10k 100k
Frequency (Hz) Frequency (Hz)

Figure 5-21. Input Voltage Noise Spectral Density vs Frequency Figure 5-22. Input Current Noise Spectral Density vs Frequency
0.1 -60 0.1 -60
Noise (dB)

G = −1, 10k Load 0.05

Total Harmonic Distortion + Noise (dB)

Noise (%)
Noise ( )

G = −1, 2k Load
G = −1, 600 Load 0.02
0.01 G = 1, 10k Load -80 0.01 -80
G = 1, 2k Load
0.005
G = 1, 600 Load
Total Harmonic Distortion
Total Harmonic Distortion

Total Harmonic Distortion

0.002
0.001 -100 0.001 -100
0.0005
G = −1, 10k Load
0.0002
G = −1, 2k Load
0.0001 -120 0.0001 G = −1, 600 Load -120
5E-5 G = 1, 10k Load
G = 1, 2k Load
2E-5 G = 1, 600 Load
1E-5 -140 1E-5 -140
20 200 2k 20k 10m 100m 1 10
Frequency (Hz) Output Amplitude (VRMS)
VOUT = 4VRMS f = 1kHz

Figure 5-23. THD+N vs Frequency Figure 5-24. THD+N vs Output Amplitude

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5.7 Typical Characteristics (continued)

at TA = 25°C, VS = ±18V, VCM = VS / 2, and RL = 10kΩ (unless otherwise noted)

2 1.75

1.75 1.7
1.65
Quiescent Current (mA)

Quiescent Current (mA)

1.5
1.6
1.25 1.55
1 1.5

0.75 1.45
1.4
0.5
1.35
0.25 1.3
0 1.25
0 4 8 12 16 20 24 28 32 36 -50 -25 0 25 50 75 100 125 150
Supply Voltage (V) Temperature ( C)
5 typical units 5 typical units

Figure 5-25. Quiescent Current vs Supply Voltage Figure 5-26. Quiescent Current vs Temperature
500 80
Riso = 0
Riso = 25
Riso = 50
Open Loop Output Impedance, Z

60
100
Overshoot (%)

40

20
10

5 0
1 10 100 1k 10k 100k 1M 10M 100M 10 100 1k
Frequency (Hz) Capacitance (pF)
Gain = –1, 10mV step

Figure 5-27. Open-Loop Output Impedance vs Frequency Figure 5-28. Small-Signal Overshoot vs
Capacitive Load
100
Riso = 0 VIN
Riso = 25 VOUT
Riso = 50
75
Voltage (5V/div)
Overshoot (%)

50

25

0
10 100 1k
Capacitance (pF) Time (100 s/div)
Gain = 1, 10mV step

Figure 5-29. Small-Signal Overshoot vs Figure 5-30. No Phase Reversal

Capacitive Load

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5.7 Typical Characteristics (continued)

at TA = 25°C, VS = ±18V, VCM = VS / 2, and RL = 10kΩ (unless otherwise noted)

VIN VIN
VOUT VOUT
Voltage (5V/div)

Voltage (5V/div)
Time (400ns/div) Time (400ns/div)

Figure 5-31. Positive Overload Recovery Figure 5-32. Negative Overload Recovery

VIN
VOUT (CL = 28pF)
VOUT (CL = 97pF)
Output Voltage (5mV/div)

Output Voltage (5mV/div)

VOUT (CL = 157pF)

VIN
VOUT (CL = 28pF)
VOUT (CL = 97pF)
VOUT (CL = 157pF)

Time (150ns/div) Time (150ns/div)

Gain = 1, 10mV step Gain = –1, 10mV step

Figure 5-33. Small-Signal Step Response Figure 5-34. Small-Signal Step Response

VIN VIN
VOUT VOUT
Output Voltage (2V/div)

Output Voltage (2V/div)

Time (1µs/div) Time (500ns/div)

Gain = 1, 10V step Gain = –1, 10V step

Figure 5-35. Large-Signal Step Response Figure 5-36. Large-Signal Step Response

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5.7 Typical Characteristics (continued)

at TA = 25°C, VS = ±18V, VCM = VS / 2, and RL = 10kΩ (unless otherwise noted)

60
Falling
Rising

45

Voltage (1mV/div)
Phase Margin ( )

30

15

0
10 100 1k
Capacitance (pF) Time (4 s/div)
10V step, 0.01% settling

Figure 5-37. Phase Margin vs Capacitive Load Figure 5-38. Settling Time
65 24
22.5 VS = 18V
60 21 VS = 2.25V
19.5
Short-Circuit Current (mA)

55 18
Output Voltage (VPP)

16.5
50 15
13.5
45 12
10.5
40 9
7.5
35 6
4.5
30 Sinking 3
Sourcing 1.5
25 0
-50 -25 0 25 50 75 100 125 150 1 10 100 1k 10k 100k 1M 10M
Temperature ( C) Frequency (Hz)

Figure 5-39. Short Circuit Current vs Temperature Figure 5-40. Maximum Output Voltage vs Frequency
180 -60
165 -70
150
-80
Channel Seperation (dB)

135
-90
120
EMIRR (dB)

105 -100
90 -110
75 -120
60
-130
45
-140
30
15 -150
0 -160
10M 100M 1G 100 1k 10k 100k 1M 10M
Frequency (Hz) Frequency (Hz)

Figure 5-41. EMIRR vs Frequency Figure 5-42. Channel Separation

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6 Detailed Description
6.1 Overview
The TLVx888 operational amplifiers combine precision offset and drift with excellent overall performance, making
the device a great choice for a wide variety of precision applications. The precision offset drift of only 0.01µV/°C
provides stability over the entire operating temperature range of –40°C to +125°C. In addition, this device offers
excellent linear performance with high CMRR, PSRR, and AOL. As with all amplifiers, applications with noisy or
high-impedance power supplies require decoupling capacitors close to the device pins. In most cases, 0.1µF
capacitors are adequate. For details and a layout example, see Section 7.4.
The TLVx888 is part of a family of zero-drift, MUX-friendly operational amplifiers. This device operates from 4.5V
to 36V, is unity-gain stable, and is designed for a wide range of general-purpose and precision applications.
The zero-drift architecture provides ultra-low input offset voltage and near-zero input offset voltage drift over
temperature and time. This choice of architecture also offers outstanding ac performance, such as ultra-low
broadband noise, zero flicker noise, and outstanding distortion performance when operating at less than the
chopper frequency.
The following section shows a representation of the proprietary TLVx888 architecture.
6.2 Functional Block Diagram
C2

Notch
CHOP1 GM1 CHOP2 Filter GM2 GM3

+IN 36V
Differential OUT
–IN Front End

GM_FF C1

6.3 Feature Description

The TLVx888 operational amplifiers use a proprietary, periodic autocalibration technique to provide extremely
low input offset voltage and input offset voltage drift over time and temperature. The devices have several
integrated features to help maintain a high level of precision through a variety of applications. These include a
phase-reversal protection, EMI rejection, electrical overstress protection, and MUX-friendly inputs.
Several design techniques and considerations to maintain the specified performance of the TLVx888 are
detailed in the Optimizing Chopper Amplifier Accuracy and Op Amp Offset Voltage and Bias Current Limitations
application notes.
6.3.1 Input Common-Mode Range
The TLVx888 are specified for operation from 4.5V to 36V (±2.25V to ±18V). The TLVx888 provide a wide input
common-mode voltage (VCM) range that includes the negative rail making them an excellent choice for single
supply operation. The input common-mode voltage to the positive rail is limited to (V+) − 1.7V. Limit the input
common mode voltage to (V–) – 0.1V ≤ VCM ≤ (V+) – 1.7V to maintain specified performance.

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6.3.2 Phase-Reversal Protection

The TLVx888 have internal phase-reversal protection. Some op amps exhibit a phase reversal when the input is
driven beyond the linear common-mode range. This condition is most often encountered in noninverting circuits
when the input is driven beyond the specified common-mode voltage range, causing the output to reverse into
the opposite rail. The TLVx888 input prevents phase reversal with excessive common-mode voltage. Instead,
the output limits into the appropriate rail. Figure 6-1 shows this performance.

VIN
VOUT

Voltage (5V/div)

Time (100 s/div)

Figure 6-1. No Phase Reversal

6.3.3 Chopping Transients

Zero-drift amplifiers such as the TLVx888 use a switching architecture on the inputs to correct for the intrinsic
offset and drift of the amplifier. Charge injection from the integrated switches on the inputs can introduce short
transients in the input bias current of the amplifier. The extremely short duration of these pulses prevents the
pulses from amplifying; however, the pulses can be coupled to the output of the amplifier through the feedback
network. Use low value resistors to minimize the input transient effects at the output of the amplifier. Use
a low-pass filter, such as an RC network, to minimize any additional noise attributed to the transients. The
chopping frequency of the TLVx888 is typically 200kHz.
6.3.4 EMI Rejection
The TLVx888 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI
interference from sources such as wireless communications and densely-populated boards with a mix of analog
signal chain and digital components. EMI immunity can be improved with circuit design techniques; the TLVx888
benefits from these design improvements.
High-frequency signals conducted or radiated to any pin of the operational amplifier can result in adverse effects,
as there is insufficient amplifier loop gain to correct for signals with spectral content outside the bandwidth.
Conducted or radiated EMI on inputs, power supply, or output can result in unexpected dc offsets, transient
voltages, or other unknown behavior. Take care to properly shield and isolate sensitive analog nodes from noisy
radio signals and digital clocks and interfaces.

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6.3.5 Electrical Overstress

Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but can involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect from accidental
ESD events both before and during product assembly.
A good understanding of this basic ESD circuitry and the relevance to an electrical overstress event is helpful.
Figure 6-2 shows an illustration of the ESD circuits contained in the TLVx888 (shows as the dashed line area).
The ESD protection circuitry involves several current-steering diodes connected from the input and output pins
and routed back to the internal power-supply lines, where the diodes meet at an absorption device internal to the
op amp. This protection circuitry is intended to remain inactive during normal circuit operation.
An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, high-
current pulse while discharging through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the
protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more amplifier device pins, current flows through one or
more steering diodes. Depending on the path that the current takes, the absorption device can activate. The
absorption device has a trigger or threshold voltage that is greater than the normal operating voltage of the
TLVx888, but less than the device breakdown voltage level. When this threshold is exceeded, the absorption
device quickly activates and clamps the voltage across the supply rails to a safe level.
Figure 6-2 shows that when the operational amplifier connects into a circuit, the ESD protection components
are intended to remain inactive, and do not become involved in the application circuit operation. However,
circumstances can arise where an applied voltage exceeds the operating voltage range of a given pin. If this
condition occurs, there is a risk that some internal ESD protection circuits are biased on and conduct current.
Any such current flow occurs through steering-diode paths and rarely involves the absorption device.
TVS
+
–

RF
V+


ESD Current-
RI IN + Steering Diodes
–
Op Amp VOUT
RS IN+ Core
+
Edge-Triggered ESD RL
+
VIN ID Absorption Circuit
–

V

+
–

TVS

Notes: VIN = (V+) + 500mV.

Notes: TVS: V+ < VTVSBR (min) < 40V, where VTVSBR (min) is the minimum specified value for the TVS breakdown voltage.
Notes: Suggested value for RS is approximately 5kΩ in an overvoltage condition.

Figure 6-2. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
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Figure 6-2 shows a specific example where the input voltage (VIN) exceeds the positive supply voltage (V+)
by 500mV or more. Much of what happens in the circuit depends on the supply characteristics. If V+ can
sink the current, one of the upper input steering diodes conducts and directs current to +VS. Excessively high
current levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that
applications limit the input current to 10mA.
If the supply is not capable of sinking the current, VIN can begin sourcing current to the operational amplifier, and
then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to
levels that exceed the operational amplifier absolute maximum ratings.
Another common question involves what happens to the amplifier if an input signal is applied to the input while
the power supplies V+ or V– are at 0V. Again, this question depends on the supply characteristic while at 0V,
or at a level below the input signal amplitude. If the supplies appear as high impedance, then the operational
amplifier supply current can be supplied by the input source through the current-steering diodes. This state is
not a normal biasing condition for the amplifier and can result in specification degradation or abnormal operation.
If the supplies are low impedance, then the current through the steering diodes can become quite high. The
current level depends on the ability of the input source to deliver current, and any resistance in the input path.
If there is any uncertainty about the ability of the supply to absorb this current, add external transient voltage
suppressor (TVS) diodes to the supply pins; see also Figure 6-2. The breakdown voltage must be selected such
that the diode does not turn on during normal operation. However, the breakdown voltage must be low enough
so that the TVS diode conducts if the supply pin begins to rise above the safe operating supply voltage level.
6.3.6 MUX-Friendly Inputs
The TLVx888 features a proprietary input stage design that allows an input differential voltage to be applied
while maintaining high input impedance. Typically, high-voltage CMOS or bipolar-junction input amplifiers feature
antiparallel diodes that protect input transistors from large VGS voltages that can exceed the semiconductor
process maximum and permanently damage the device. Large VGS voltages can be forced when applying a
large input step, switching between channels, or attempting to use the amplifier as a comparator.
The TLVx888 solves these problems with a switched-input technique that prevents large input bias currents
when large differential voltages are applied. This input architecture addresses many issues seen in switched or
multiplexed applications, where large disruptions to RC filtering networks are caused by fast switching between
large [Link] 6-3 shows a typical application where MUX-Friendly inputs can improve settling time
performance. The TLVx888 offers outstanding settling performance as a result of these design innovations and
built-in slew-rate boost and wide bandwidth. The TLVx888 can also be used as a comparator. Differential and
common-mode input ranges still apply.

+10V
15V
2x1 +
MUX
20V TLVx888 ADC

10V
–

15V

Figure 6-3. Multiplexed Application

6.4 Device Functional Modes

The TLVx888 has a single functional mode, and is operational when the power-supply voltage is greater than
4.5V (±2.25V). The recommended power supply voltage for the TLVx888 is 36V (±18V).

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7 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

7.1 Application Information

The TLVx888 operational amplifier combines precision offset and drift with excellent overall performance, making
the device an excellent choice for many precision applications. The precision offset drift of only 0.01µV/°C
provides stability over the entire temperature range. In addition, the device pairs excellent CMRR, PSRR, and
AOL dc performance with outstanding low-noise operation. As with all amplifiers, applications with noisy or
high-impedance power supplies require decoupling capacitors close to the device pins. In most cases, 0.1µF
capacitors are adequate.
7.1.1 Basic Noise Calculations
Low-noise circuit design requires careful analysis of all noise sources. In many cases, external noise sources
can dominate; consider the effect of source resistance on overall op-amp noise performance. Total noise of the
circuit is the root-sum-square combination of all noise components.
The resistive portion of the source impedance produces thermal noise proportional to the square root of the
resistance. The source impedance is typically fixed; consequently, select op amp and the feedback resistors that
minimize the respective contributions to the total noise.
Figure 7-1 shows the noninverting op-amp circuit configurations with gain. Figure 7-2 shows the inverting
op-amp circuit configurations with gain. In circuit configurations with gain, the feedback network resistors also
contribute noise. In general, the current noise of the op amp reacts with the feedback resistors to create
additional noise components. However, the low current noise of the TLVx888 means that the current noise
contribution can be ignored.
The feedback resistor values can generally be chosen to make these noise sources negligible. Low impedance
feedback resistors load the output of the amplifier. The equations for total noise are shown for both
configurations.
For additional resources on noise calculations, visit TI Precision Labs.

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R1 R2

GND –
eo
+

RS

Source
+
VS
–

GND

Figure 7-1. Noise Calculation in Noninverting Gain Configurations

Eo = eo BWN VRMS (1)

R 2 2 R R 2
eo = 1 + R 2 eS2 + eN2 + eR1 R2 + iNRS + iN R 1+ R
2 V
(2)
1 1 2 Hz

V
eS = 4kBT K RS (3)
Hz

R1R2 V
eR1 R2 = 4kBT K R1 + R2 (4)
Hz

J
kB = 1.38065 × 10−23 K (5)

T K = 2.37.15 + T °C K (6)

where
• en is the voltage noise spectral density of the amplifier. For the TLVx888, en = 7.5nV/√Hz at 1kHz)
• eo is the total noise density
• eS is the thermal noise of RS
• eR1 || R2 is the thermal noise of R1 || R2
• kB is the Boltzmann constant
• T(K) is the temperature in kelvins

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R1 R2

–
RS
eo
+
Source
+ GND
VS
–

GND

Figure 7-2. Noise Calculation in Inverting Gain Configurations

Eo = eo BWN VRMS (7)

R 2 R +R R 2
eo = 1 + R +2R eN2 + eR1 + RS R2 + iN R S+ R 1+ R2 V
(8)
S 1 S 1 2 Hz

RS + R1 R2 V
eR1 + RS R2 = 4kBT K RS + R1 + R2 (9)
Hz

J
kB = 1.38065 × 10−23 K (10)

T K = 2.37.15 + T °C K (11)

where
• See
• en is the voltage noise spectral density of the amplifier. For the TLVx888, en = 7.5nV/√Hz at 1kHz)
• eo is the total noise density
• eS is the thermal noise of RS
• e(R1 + RS) || R2 is the thermal noise of (R1 + RS) || R2
• kB is the Boltzmann constant
• T(K) is the temperature in kelvins

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7.2 Typical Applications

7.2.1 High-Side Current Sensing
V+

+
TLVx888 VOUT

RSENSE –
ISOURCE
Matched Resistor Pair −V

20k 20k
RL

10k
10k

REF

Figure 7-3. High-Side Current Monitor

[Link] Design Requirements

A common systems requirement is to monitor the current being delivered to a load. Monitoring confirms that
normal current levels are being maintained, and also provides an alert if an overcurrent condition occurs.
Fortunately, a relatively simple current monitor circuit can be achieved using a precision op amp, such as the
TLVx888. This device has exceptional precision and wide gain bandwidth product to accommodate for very high
gain configurations.
The TLVx888 is configured as a difference amplifier with a predetermined gain. The difference amplifier inputs
are connected across a sense resistor through which the load current flows. The sense resistor can be
connected to the high side or low side of the circuit through which the load current flows. Commonly, high-side
current sensing is applied. Figure 7-3 shows an applicable TLVx888 configuration. Low-side current sensing can
be applied as well if the sense resistor can be placed between the load and ground.
Use the following parameters for this design example:
• Dual supply: ±15V
• Linear output voltage range: 0V to 5V
• Load current, IL: 1mA to 100mA
The following design details and equations can be used to reconfigure this design for different output voltage
ranges and current loads.

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[Link] Detailed Design Procedure

Designing a high-side current monitor circuit is straightforward, provided that the amplifier electrical
characteristics are carefully considered so that linear operation is maintained. Other additional characteristics,
such as the input voltage range of the analog to digital converter (ADC) that follows the current monitor stage,
must also be considered when configuring the system.
15V
15V
+
TLVx888 +
+
TLVx888 VOUT
100m –
1mA to
100mA
< 40V
Matched Resistor Pair 15V 989
–

15V
20k 20k
RL
988k
10k
10k

330pF

Figure 7-4. High Side Current Sense With Gain Stage

For example, consider the design of a TLVx888 high-side current monitor with an output voltage range set to be
compatible with the input of an ADC with a full-scale input range of 0V to 5V. Although the TLVx888 is specified
as a rail-to-rail output amplifier, the linear output operating range (like all amplifiers) does not quite extend all the
way to the supply rails. This linear operating range must be considered.
In this design example, the TLVx888 is powered by ±15V; therefore, the device is easily capable of providing the
0V to 5V swing; or even more, if the ADC has a wider input range.
The best measure of an op-amp linear output voltage range comes from the open-loop voltage gain (AOL)
specification listed in the Electrical Characteristics table. The AOL test conditions specify a linear swing range
from 600mV from each supply rail (RL = 10kΩ).
A nominal load current (IL) of 100mA is used in this example. In most applications, however, the ability to monitor
current levels far less than 100mA is useful.
Selection of current sense resistor RS comes down to how much voltage drop can be tolerated at maximum
current and the permissible power loss or dissipation. A good compromise for a 100mA sense application is an
RS of 100mΩ. That value results in a power dissipation of 1mW, and a 10mV drop at 100mA.
Next, determine the gain of the TLVx888 difference amplifier circuit. The maximum current of 100mA flowing
through a 100mΩ sense resistor results in 100mV across the resistor. The gain of the difference amplifier is
limited by the required input common-mode voltage. A gain of 1/2, for example, provides a 1/3 attenuation of
the high side voltage seen by the circuit. The attenuation is enough to keep the input common-mode within the
range of the TLVx888, (V+) − 1.7V.
The differential voltage that is applied across the TLVx888 difference amplifier circuit inputs is attenuated by
the difference amplifier and a gain stage is needed for proper scaling. Conveniently, the second channel of
the TLV2888 can used. The ultra-low offset and wide-bandwidth enable very high gain configurations. In this
example, a gain of 1000V/V provides the necessary scaling for a 0V to 5V output.
The TLVx888 output voltage is intentionally limited to 5V. However, because of the ±15V supply, the output
voltage can be much higher to allow for a higher voltage data converter with a wider dynamic range.
The TLVx888 output, as well as other CMOS output amplifiers, often swing closer to 0V (in single supply
configurations) than the linear output parameters suggest. The voltage output swing, VO (see the Electrical
Characteristics table), is not an indication of the linear output range, but rather how close the output can move
towards the supply rail. In that region, the amplifier output approaches saturation, and the amplifier ceases to

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operate linearly. Thus, in the current-monitor application, the current-measurement capability can continue to
much less than the 600mV output level. However, keep in mind that the linearity errors are becoming large.
Lastly, some notes about maximizing the high-side current monitor performance:
1. All resistor values are critical for accurate gain results. Match resistor pairs of [R1 and R3] and [R2 and
R4] as closely as possible to minimize common-mode mismatch error. Use a 0.1% tolerance, or better.
Often, selecting two adjacent resistors on a reel provides close matching compared to random selection. The
RES21A provides an even more elegant circuit design with better performance than discrete 0.1% resistors.
2. Keep the closed-loop gain, G, of the difference amplifier set to a reasonable value to reduce gain error and
maximize bandwidth. The high bandwidth of TLVx888 enables very high gain configurations.
3. Although current monitoring is often used for monitoring dc supply currents, ac current can also be
monitored. Special attention to the −3dB cutoff frequency of the circuit is warranted.

For more information about amplifier-based, high-side current monitors, see the TI Analog Engineer’s Circuit
Cookbook: Amplifiers.
[Link] Application Curve

5
4
3
2
Output Voltage (V)

1
0
-1
-2
-3
-4
-5
-100 -80 -60 -40 -20 0 20 40 60 80 100
Current (mA)

Figure 7-5. Current Sense Measurement Results

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7.2.2 Programmable Current Source

Figure 7-6 shows the basic configuration for a precision current source using the TLVx888. The circuit provides
a configurable current source to a floating load. Figure 7-6 uses a digital-to-analog converter (DAC) to set the
current level. For example, a 5V full-scale voltage at the input of the amplifier provides a 100mA current source.
V+

RL
V+

DAC + 100
TLVx888
–

10k

100pF 49.9

GND

Figure 7-6. Programmable, Precision Current Source

7.2.3 Programmable Current Source For A Grounded Load

Figure 7-7 shows the TLVx888 configured as a programmable current source for a ground referenced load. To
achieve single supply operation, a two stage design is employed. The first stage sets a reference current, and
the second stage acts as a current mirror with gain. The TLVx888 are used to regulate the current sourced from
the transistors in both stages.
V+

100pF 32

V+
10k

320

– 100
TLVx888
V+ +
DAC + 100
V+
TLVx888
RL
–
10k

4.99k
100pF

Figure 7-7. Single Supply Programmable Current Source For A Ground Referenced Load

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7.3 Power Supply Recommendations

The TLVx888 are specified for operation from 4.5V to 36V (±2.25V to ±18V). The TLVx888 operates on both
single and dual supplies. The TLVx888 do not require symmetrical supplies; the op amps only require a
minimum voltage of 4.5V to operate.

CAUTION
Supply voltages larger than 40V can permanently damage the device (see the Absolute Maximum
Ratings table).

Place 0.1μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or
high‑impedance power supplies. For more detailed information on bypass capacitor placement, see Section 7.4.
7.4 Layout
7.4.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices:
• For the lowest offset voltage, avoid temperature gradients that create thermoelectric (Seebeck) effects in the
thermocouple junctions formed from connecting dissimilar conductors. Also:
– Use low thermoelectric-coefficient conditions (avoid dissimilar metals).
– Thermally isolate components from power supplies or other heat sources.
– Shield operational amplifier and input circuitry from air currents, such as cooling fans.
• Noise can propagate into analog circuitry through the power pins of the op amp and the circuit as a whole.
Bypass capacitors reduce the coupled noise by providing low-impedance power sources local to the analog
circuitry.
– Connect low-ESR, 0.1µF ceramic bypass capacitors between each supply pin and ground, placed as
close as possible to the device. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective
methods of noise suppression. One or more layers on multilayer PCBs are typically devoted to ground
planes. A ground plane helps distribute heat and reduces EMI noise pickup. Physically separate digital and
analog grounds paying attention to the flow of the ground current. For more detailed information, see the The
PCB is a component of op amp design analog application journal.
• To reduce parasitic coupling, run the input traces as far away as possible from the supply or output traces. If
these traces cannot be separated, cross the sensitive trace perpendicular as opposed to in parallel with the
noisy trace.
• Place the external components as close as possible to the device. As Figure 7-9 shows, keep the feedback
resistor (R3) and gain resistor (R4) close to the inverting input to minimize parasitic capacitance.
• Keep the length of input traces as short as possible. Short traces to the inverting input help to minimize
parasitic capacitance on the inverting input. Always remember that the input traces are the most sensitive
part of the circuit.
• For best performance, clean the PCB following board assembly.
• Any precision integrated circuit can experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, bake the PCB assembly to remove moisture
introduced into the device packaging during the cleaning process. A low-temperature, post-cleaning bake
at 85°C for 30 minutes is sufficient for most circumstances.

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7.4.2 Layout Example

RF_A

V+
RG_A
–
TLV2888 VOUT_A
VIN_A +

V

Replicated for channel B

Figure 7-8. Schematic Representation

VOUT_A VS+
VOUT_B
Place components Use low-ESR, ceramic
close to device and to bypass capacitor
each other to reduce
parasitic errors
RF_A
OUT A V+
RG_A
RF_B
–IN A OUT B
RG_B
VIN_A +IN A –IN B

V– +IN B VIN_B

VS–

Use low-ESR, ceramic

Ground (GND) plane on another layer
bypass capacitor

Figure 7-9. Operational Amplifier Board Layout for Noninverting Amplifier Configuration

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8 Device and Documentation Support

8.1 Device Support
8.1.1 Development Support
[Link] PSpice® for TI
PSpice® for TI is a design and simulation environment that helps evaluate performance of analog circuits. Create
subsystem designs and prototype solutions before committing to layout and fabrication, reducing development
cost and time to market.
[Link] TINA-TI™ Simulation Software (Free Download)
TINA-TI™ simulation software is a simple, powerful, and easy-to-use circuit simulation program based on a
SPICE engine. TINA-TI simulation software is a free, fully-functional version of the TINA™ software, preloaded
with a library of macromodels, in addition to a range of both passive and active models. TINA-TI simulation
software provides all the conventional dc, transient, and frequency domain analysis of SPICE, as well as
additional design capabilities.
Available as a free download from the Design and simulation tools web page, TINA-TI simulation software offers
extensive post-processing capability that allows users to format results in a variety of ways. Virtual instruments
offer the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic
quick-start tool.

Note
These files require that either the TINA software or TINA-TI software be installed. Download the free
TINA-TI simulation software from the TINA-TI™ software folder.

8.2 Documentation Support

8.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Zero-drift Amplifiers: Features and Benefits application brief
• Texas Instruments, The PCB is a component of op amp design application note
• Texas Instruments, Operational amplifier gain stability, Part 3: AC gain-error analysis
• Texas Instruments, Operational amplifier gain stability, Part 2: DC gain-error analysis
• Texas Instruments, Using infinite-gain, MFB filter topology in fully differential active filters application note
• Texas Instruments, Op Amp Performance Analysis
• Texas Instruments, Single-Supply Operation of Operational Amplifiers application note
• Texas Instruments, Shelf-Life Evaluation of Lead-Free Component Finishes application note
• Texas Instruments, Feedback Plots Define Op Amp AC Performance application note
• Texas Instruments, EMI Rejection Ratio of Operational Amplifiers application note
• Texas Instruments, Analog Linearization of Resistance Temperature Detectors application note
• Texas Instruments, TI Precision Design TIPD102 High-Side Voltage-to-Current (V-I) Converter
8.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on [Link]. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
8.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.

28 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TLV888 TLV2888

 TLV888, TLV2888
[Link] SBOSAG5A – DECEMBER 2024 – REVISED SEPTEMBER 2025

8.5 Trademarks
TINA-TI™ and TI E2E™ are trademarks of Texas Instruments.
TINA™ is a trademark of DesignSoft, Inc.
PSpice® is a registered trademark of Cadence Design Systems, Inc.
All trademarks are the property of their respective owners.
8.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

8.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

9 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (December 2024) to Revision A (September 2025) Page
• Changed TLV888 D (SOIC) and TLV2888 DGK (VSSOP) packages from preview to production data (active) 1
• Updated application circuit in Description ..........................................................................................................1
• Updated offset voltage drift value to fix typo in Description ...............................................................................1
• Updated TLV2888 (D, SOIC-8) Thermal Information ........................................................................................ 5
• Added note 1 to common-mode rejection ratio for TA = –40°C to +125°C......................................................... 6
• Updated open-loop voltage gain for RLOAD = 2kΩ test condition....................................................................... 6
• Added note 1 to open-loop voltage gain for TA = –40°C to +125°C................................................................... 6
• Added note 1 to voltage output swing from rail for no load................................................................................ 6
• Updated voltage output swing from rail for no load............................................................................................ 6

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 29

Product Folder Links: TLV888 TLV2888
 PACKAGE OPTION ADDENDUM

[Link] 2-Oct-2025

PACKAGING INFORMATION

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

TLV2888DR Active Production SOIC (D) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TL2888
TLV2888DR.A Active Production SOIC (D) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TL2888
TLV888DR Active Production SOIC (D) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TL888

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

[Link]
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

[Link]
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

[Link]
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