Scribd
Upload
22 views2 pages

Five

The document describes the implementation of a memory module in Verilog with specified terminals for clock, reset, validation, readiness, read/write control, address, input data, and output data. It also details the creation of multiple instances of the memory module using a generate construct, allowing for a parameterized number of memory instances defined by MEM_VALUE. The design includes functionality for both reading from and writing to the memory based on control signals.

Uploaded by

RITESH
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
22 views2 pages

Five

The document describes the implementation of a memory module in Verilog with specified terminals for clock, reset, validation, readiness, read/write control, address, input data, and output data. It also details the creation of multiple instances of the memory module using a generate construct, allowing for a parameterized number of memory instances defined by MEM_VALUE. The design includes functionality for both reading from and writing to the memory based on control signals.

Uploaded by

RITESH
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

1)Implement a memory module with following terminals.

Clk, reset, validv(validate transmit data), ready, wr_rd(read/write), addr, data_i, data_o.

//DESIGN
module Mem(
input wire clk,
input wire reset,
input wire validv,
input wire ready,
input wire wr_rd,
input wire [7:0] addr,
input wire [7:0] data_i,
output reg [7:0] data_o
);
reg [7:0] memory [0:255]; // 256x8 memory (256 address locations, each storing 8 bits)
always @(posedge clk or posedge reset) begin
if (reset)
data_o <= 8'b0;
else if (validv && wr_rd == 1 && ready)
data_o <= memory[addr];
end
always @(posedge clk or posedge reset) begin
if (reset)
begin
for (int i = 0; i <= 255; i = i + 1)
memory[i] <= 8'b0;
end
else if (validv && wr_rd == 0 && ready)
begin
memory[addr] <= data_i;
end
end
endmodule
2) Create a multiple instance of memory module defined above with generate construct. Define a parameter MEM_VALUE=4 with default value and use
corresponding index value to implement multiple instance and verify it.

module Mul_mem_Instances #(parameter MEM_VALUE = 4) (input


wire clk,
input wire reset,
input wire validv,
input wire ready,
input wire wr_rd,
input wire [7:0] addr,
input wire [7:0] data_i,
output wire [7:0] data_o
);
genvar i; //generate block
generate
for (i = 0; i < MEM_VALUE; i = i + 1) begin : memory_instances
Memory memory_instance (
.clk(clk),
.reset(reset),
.validv(validv),
.ready(ready),
.wr_rd(wr_rd),
.addr(addr),
.data_i(data_i),
.data_o(data_o[i])
);
end
endgenerate
endmodule

You might also like