4.

Central Processing Unit (CPU)

4.1. Instruction Set and Addressing
The operation of CPU is determined by the instruction it executes, referred to as machine instructions or
computer instructions. The collection of different instructions is referred as the instruction set of the
CPU. Where do you think the instruction come from?

Each instruction must contain the information required by the CPU for execution. The elements of an
instruction are as follows:
Operation Code:
Specifies the operation to be performed (e.g., add, move etc.). The operation is specified by a binary
code, known as the operation code or opcode.
Source operand reference:
The operation may involve one or more source operands; that is, operands that are inputs for the
operation.
Result operand reference:
The operation may produce a result.
Next instruction reference:
This tells the CPU where to fetch the next instruction after the execution of this instruction is
complete.

4.1.1. Addressing Techniques

We see what the definitions of opcode and operand are. Now we have to see how the address of an
operand is specified, and how are the bits of an instruction organized to define the operand addresses
and operation of that instruction.
The main addressing Modes/techniques are:
1) Immediate
2) Direct
3) Indirect
4) Register
5) Register Indirect
6) Displacement
7) Stack
All computer architectures provide more than one of these addressing modes. The question arises as to
how the control unit can determine which addressing mode is being used in a particular instruction.
Several approaches are used. Often, different opcodes will use different addressing modes. Also, one or
more bits in the instruction format can be used as a mode field. The value of the mode field determines
which addressing mode is to be used.
What is the interpretation of effective address? In a system without virtual memory (virtual memory will
be covered in future courses), the effective address will be either a main memory address or a register.
In a virtual memory system, the effective address is a virtual address or a register. The actual mapping to
a physical address is a function of the paging mechanism and is invisible to the programmer.
To explain the addressing modes, we use the following notation:
A = Contents of an address field in the instruction that refers to a memory.
R =
Contents of an address field in the instruction that refers to a register.
Actual (effective) address of the location containing the referenced
EA =
operand.
(X) = Contents of location X.
1) Immediate Addressing

1
The simplest form of addressing is immediate addressing, in which the operand is actually present inthe
instruction:
OPERAND = A

This mode can be used to define and use constants or set initial values of variables. The advantage of
immediate addressing is that no memory reference other than the instruction fetch is required to
obtain the operand. The disadvantage is that the size of the number is restricted to the size of the
address field, which, in most instruction sets, is small compared with the world length.

Figure: Immediate Addressing Mode

The instruction format for Immediate Addressing Mode is shown in the above figure.

2) Direct Addressing:

A very simple form of addressing is direct addressing, in which the address field contains the effective
address of the operand:

EA = A

It requires only one memory reference and no special calculation.

Figure: Direct Addressing Mode

The fetching of data from the memory location in case of direct addressing mode is shown in the above
figure. Here, 'A' indicates the memory address field for the operand.

3) Indirect Addressing:

2
With direct addressing, the length of the address field is usually less than the word length, thus limiting
the address range. One solution is to have the address field refer to the address of a word in memory,
which in turn contains a full-length address of the operand. This is known as indirect addressing:

EA = (A)

Figure: Indirect Addressing Mode

The exact memory location of the operand in case of indirect addressing mode is shown in the above
figure. Here 'A' indicates the memory address field of the required operands.

4) Register Addressing:

Register addressing is similar to direct addressing. The only difference is that the address field refers to
a register rather than a main memory address:

EA = R

The advantages of register addressing are that only a small address field is needed in the instruction
and no memory reference is required. The disadvantage of register addressing is that the address space
is very limited.

3
 Figure: Register Addressing Mode.

The exact register location of the operand in case of Register Addressing Mode is shown in the above
figure. Here, 'R' indicates a register where the operand is present.

5) Register Indirect Addressing

Register indirect addressing is similar to indirect addressing, except that the address field refers to a
register instead of a memory location.
It requires only one memory reference and no special calculation.

EA = (R)

Register indirect addressing uses one less memory reference than indirect addressing. Because, the
first information is available in a register which is nothing but a memory address, from that memory
location, we use to get the data or information. In general, register access is much faster than the
memory access.

6) Displacement Addressing

A very powerful mode of addressing combines the capabilities of direct addressing and register indirect
addressing, which is broadly categorized as displacement addressing:

EA = A + (R)

Displacement addressing requires that the instruction have two address fields, at least one of which is
explicit. The value contained in one address field (value = A) is used directly. The other address field, or
an implicit reference based on opcode, refers to a register whose contents are added to A to produce
the effective address. The advantage of displacement addressing is that CPU can make implicit or
explicit access (for example increment/decrement) to the nearby register instead of the far memory.
The general format of displacement Addressing is shown in the next figure.

4
 Figure: Displacement Addressing

Three most common use of displacement addressing is:

 Relative addressing
 Base-register addressing
 Indexing

Relative Addressing:

For relative addressing, the implicitly referenced register is the program counter (PC). That is,
the current instruction address is added to the address field to produce the EA. Thus, the
effective address is a displacement relative to the address of the instruction.

Base-Register Addressing:

The reference register contains a memory address, and the address field contains a
displacement from that address. The register reference may be explicit or implicit.
In some implementation, a single segment/base register is employed and is used implicitly. In
others, the programmer may choose a register to hold the base address of a segment, and the
instruction must reference it explicitly. In this addressing mode, the base registers vary implicitly
or explicitly while the memory address field contains the offset from the base register.

Explicit and implicit are common terms in computer science. Can you guess the meaning of
implicit and explicit? If an address is explicit its value must be specified in the instruction clearly,
if it is implicit, the control unit knows its value automatically and no need to specify its value in
the instruction.

Indexing:

The address field references a main memory address, and the reference register contains a
positive displacement from that address. In this case also the register reference is sometimes
explicit and sometimes implicit.

5
 Generally index register are used for iterative tasks, it is typical that there is a need to
increment or decrement the index register after each reference to it. Because this is such a
common operation, some system will automatically do this as part of the same instruction cycle.

This is known as auto-indexing. We may get two types of auto-indexing:

-- one is auto-incrementing and the other one is
-- auto-decrementing.

If certain registers are devoted exclusively to indexing, then auto-indexing can be invoked
implicitly and automatically. If general purpose register are used, the auto index operation may
need to be signaled by a bit in the instruction.

Auto-indexing using increment can be depicted as follows:

EA = A + (R)
R = (R) + 1

Auto-indexing using decrement can be depicted as follows:

EA = A + (R)
R = (R) - 1

7) Stack Addressing

A stack is a linear array or list of locations. It is sometimes referred to as a last-in-first-out queue. A stack
is a reserved block of locations. Items are appended to the top of the stack so that, at any given time,
the block is partially filled. Associated with the stack is a pointer whose value is the address of the top
of the stack. The stack pointer is maintained in a register. Thus, references to stack locations in
memory are in fact register indirect addresses.

The stack mode of addressing is a form of implied addressing. The machine instructions need not include
a memory reference but implicitly operate on the top of the stack.

Note: Try to compare the above addressing modes in terms of size of bits available for addressing
(address space), number of memory references required, amount of calculations required and how
easy to handle the calculations. Do you see any trade off between these parameters? Yes. Increasing
the address space allows you to have more number of addresses to refer, however this forces you to use
more number of bits for address than those available in registers. This force you to use main memory to
store address (indirect addressing) which in turn involve slower main memory address access.

4.1.2. Machine Instruction

In the previous section, the operands are discussed. Now it is time to discuss the whole instruction
including the opcodes. The next instruction to be fetched is located in main memory (but don’t forget
the use of cache discussed in chapter three). But in case of virtual memory system, it may be either in
main memory or secondary memory (disk). In most cases, the next instruction to be fetched
immediately follows the current instruction (remember the locality of reference concept in chapter
three - memory). In those cases, there is no explicit reference to the next instruction. When an explicit
reference is needed, then the main memory or virtual memory address must be given. Virtual memory
will be covered in future courses.

6
Source and result operands can be in one of the three areas:

 main or virtual memory,

 CPU register or
 I/O device.

The steps involved in instruction execution are shown in the next Figure.

Figure: Steps involved in instruction execution

Instruction Representation
Within the computer, each instruction is represented by a sequence of bits (remember that computer
understand only 0 and 1). The instruction is divided into fields, corresponding to the constituent
elements of the instruction. The instruction format is highly machine specific and it mainly depends on
the machine architecture. A simple example of an instruction format is shown in the next figure. It is
assume that it is a 16-bit CPU (this means you have 16-bit word length which is also the size of MBR, also
the words are instructions). 4 bits are used to provide the operation code. So, we may have 16 (24 = 16)
different set of instructions. With each instruction, there are two operands. To specify each operand, 6
bits are used. It is possible to provide 64 (26 = 64) different operands for each operand reference.

It is difficult to deal with binary representation of machine instructions. Thus, it has become common
practice to use a symbolic representation of machine instructions. Opcodes are represented by
abbreviations, called mnemonics that indicate the operations. Visualize you are writing computer code
using binary digits instead of using high level programming languages like C++. What do you think is
the purpose of compilers in programming?
Common examples include:

ADD Add
SUB Subtract
MULT Multiply
DIV Division
LOAD Load data from memory to
CPU
Figure: A simple instruction format.

7
 STORE Store data to memory from
CPU.

Operands are also represented symbolically. For example, the instruction

MULT R, X ; R R * X

May mean multiply the value contained in the data location X by the contents of register R and put the
result in register R

In this example, X refers to the address of a location in memory and R refers to a particular register.

Thus, it is possible to write a machine language program in symbolic form. Each symbolic opcode has a
fixed binary representation, and the programmer specifies the location of each symbolic operand.

Instruction Types
The instruction set of a CPU can be categorized as follows:
Data Processing:
These are arithmetic and Logic instructions. Arithmetic instructions provide computational
capabilities for processing numeric data. Logic (Boolean) instructions operate on the bits of a
word as bits rather than as numbers. Logic instructions thus provide capabilities for processing
any other type of data. These operations are performed primarily on data in CPU registers.

Data Storage:
Memory instructions are used for moving data between memory and CPU registers.

Data Movement:
I/O instructions are needed to transfer program and data into memory from storage device or
input device and the results of computation back to the user (output devices like screen). What
will happen when you double click an application icon from in desktop?

Control:
Test and branch instructions
Test instructions are used to test the value of a data word or the status of a computation.
Branch instructions are then used to branch to a different set of instructions depending on the
decision made.

All this instructions are covered in your future courses (Assembly Programming). Hence, detail
discussions are not provided here.

4.1.3. Instruction Format

An instruction format defines the layout of the bits of an instruction, in terms of its constituent parts.
An instruction format must include an opcode and, implicitly or explicitly, zero or more operands. Each
explicit operand is referenced using one of the addressing modes that are available for that machine.
The format must, implicitly or explicitly, indicate the addressing mode of each operand. For most
instruction sets, more than one instruction format is used. Four common instruction formats are shown
in the next figure.

8
 Figure: Four common Instruction formats

Instruction Length
On some machines, all instructions have the same length; on others there may be many different
lengths. Instructions may be shorter than, the same length as, or more than the word length. Having all
the instructions be the same length is simpler and make decoding easier but often wastes space, since
all instructions then have to be as long as the longest one. Here you should see trade off between
simplicity in decoding (control circuit) and efficient use of bits in the instructions. Possible relationship
between instruction length and word length is shown in the next figure.

Figure: Some Possible relationship between instructions and word length

9
Generally there is a correlation between memory transfer length and the instruction length. Either the
instruction length should be equal to the memory transfer length or one should be a multiple of the
other. Also in most of the case there is a correlation between memory transfer length and word length
of the machine. Word length <--> memory transfer length <--> instruction length

Allocation of Bits:

For a given instruction length, there is clearly a trade-off between the number of opcodes and the power
of the addressing capabilities. More opcodes obviously mean more bits in the opcode field. For an
instruction format of a given length, this reduces the number of bits available for addressing.
The following interrelated factors go into determining the use of the addressing bits:

Number of Addressing modes:

Sometimes as addressing mode can be indicated implicitly. In other cases, the addressing mode must be
explicit, and one or more bits will be needed.

Number of Operands:

Typical instructions on today's machines provide for two operands (not three, guess why? To use the
instruction bits efficiently). Each operand address in the instruction might require its own mode
indicator, or the use of a mode indicator could be limited to just one of the address field.

Register versus memory:

A machine must have registers so that data can be brought into the CPU for processing. With a single
user-visible register (usually called the accumulator), one operand address is implicit and consumes no
instruction bits. Even with multiple registers, only a few bits are needed to specify the register. The
more that registers can be used for operand references, the fewer bits are needed.

Number of register sets:

A number of machines have one set of general purpose registers, with typically 8 or 16 registers in the
set. These registers can be used to store data and can be used to store addresses for displacement
addressing. The trend recently has been away from one bank of general purpose registers and toward a
collection of two or more specialized sets (such as data and displacement).

Address range:

For addresses that reference memory, the range of addresses that can be referenced is related to the
number of address bits. With displacement addressing, the range is opened up to the length of the
address register.

Address granularity:

10
In a system with 16- or 32-bit words, an address can reference a word or a byte at the designer's choice.
Byte addressing is convenient for character manipulation but requires, for a fixed size memory, more
address bits.

Variable-Length Instructions:

Instead of looking for fixed length instruction format, designer may choose to provide a variety of
instructions formats of different lengths. This tactic makes it easy to provide a large range of opcodes,
with different opcode lengths. Addressing can be more flexible, with various combinations of register
and memory references plus addressing modes. With variable length instructions, many variations can
be provided efficiently and compactly. The principal price to pay for variable length instructions is an
increase in the complexity of the CPU (especially the control unit – to handle the variations). Do you see
the trade off between flexibility and circuit complexity? This is also related to RISC and CISC concepts to
be covered in the last chapter of this course.

Number of addresses:

The processor architecture is described in terms of the number of addresses contained in each
instruction. Most of the arithmetic and logic instructions will require more operands. All arithmetic and
logic operations are either unary
(one source operand, e.g. NOT) or binary (two source operands, e.g. ADD).

Thus, we need a maximum of two addresses to reference source operands. The result of an operation
must be stored, suggesting a third reference.

Three address instruction formats are not common because they require a relatively long instruction
format to hold the three address reference.

With two address instructions, and for binary operations, one address must do double duty as both an
operand and a result.

In one address instruction format, a second address must be implicit for a binary operation. For implicit
reference, a processor register is used and it is termed as accumulator (AC). The accumulator contains
one of the operands and is used to store the result. Can you guess the purpose of AC?

Consider a simple arithmetic expression to evaluate:

Y= (A + B) / (C * D)

The evaluation of this expression in three address instruction format, two address instruction formats
and one address instruction format is shown in the next figures, Figure a, Figure b and Figure c
respectively.

11
Figure a: Three address instructions Figure b: Two address instructions

Figure c: One address instructions

Again do you see any trade off here, yes. There is a trade off between the number of instructions and
the number of operands (size of instructions). As you try to decrease the instruction size (by reducing
the number of operands) the number of instructions to accomplish the same task will be increased.

Section 4.2.2 and 4.2.3 will be discussed in detail in future courses.

12
4.2. Introduction to CPU Design
4.2.1. Introduction to CPU

The operation or task that must be performed by CPU is:

 Fetch Instruction: The CPU reads an instruction from memory.

 Decode Instruction: The instruction is decoded to determine what action is required.
 Fetch Data: The execution of an instruction may require reading data from memory or
I/O module. This is part of execution step.
 Process data: The execution of an instruction may require performing some arithmetic
or logical operation on data. This is also part of execution step.
 Write data: The result of an execution may require writing data to memory or an I/O
module.

To do these tasks, it should be clear that the CPU needs to store some data temporarily. It must
remember the location of the last instruction so that it can know where to get the next instruction. It
needs to store instructions and data temporarily while an instruction is being executed. In other words,
the CPU needs a small internal memory. These storage locations are generally referred as registers.

The major components of the CPU are an arithmetic and logic unit (ALU) and a control unit (CU). The
ALU does the actual computation or processing of data. The CU controls the movement of data and
instruction into and out of the CPU and controls the operation of the ALU.

The CPU is connected to the rest of the system through system bus. Through system bus, data or
information gets transferred between the CPU and the other component of the system. The system bus
may have three components:

Data Bus:
Data bus is used to transfer the data between main memory and CPU.

Address Bus:
Address bus is used to access a particular memory location by putting the address of the memory
location.

Control Bus:
Control bus is used to provide the different control signal generated by CPU to different part of the
system. As for example, memory read is a signal generated by CPU to indicate that a memory read
operation has to be performed. Through control bus this signal is transferred to memory module to
indicate the required operation.

There are three basic components of CPU: register bank, ALU and Control Unit. There are several data
movements between these units and for that an internal CPU bus is used. Internal CPU bus is needed to
transfer data between the various registers and the ALU.

The internal organization of CPU in more abstract level is shown in the next two figures. Can you define
the word abstract?

13
 Figure: CPU with the system Bus

Figure: Internal Structure of the CPU

Registers

A computer system employs a memory hierarchy. At the highest level of hierarchy, memory is faster,
smaller and more expensive. Within the CPU, there is a set of registers which can be treated as a
memory in the highest level of hierarchy. The registers in the CPU can be categorized into two groups:

 User-visible registers: This enables the machine - or assembly-language programmer to

minimize main memory reference by optimizing use of registers. Used by
machine/assembly language programmer.

 Control and status registers: These are used by the control unit to control the
operation of the CPU. Operating system programs may also use these in privileged
mode to control the execution of program.

14
User-visible Registers:
The user-visible registers can be categorized as follows:
 General Purpose Registers
 Data Registers
 Address Registers
 Condition Codes

General-purpose registers can be assigned to a variety of functions by the programmer. In some cases,
general- purpose registers can be used for addressing functions (e.g., register indirect, displacement).

In other cases, there is a partial or clean separation between data registers and address registers.

Data registers may be used to hold only data and cannot be employed in the calculation of an operand
address.

Address registers may be somewhat general purpose, or they may be devoted to a particular addressing
mode. Examples include the following:

 Segment pointer: In a machine with segment addressing, a segment register holds the
address of the base of the segment. There may be multiple registers, one for the code
segment and one for the data segment.
 Index registers: These are used for indexed addressing and may be auto indexed.
 Stack pointer: If there is user visible stack addressing, then typically the stack is in
memory and there is a dedicated register that points to the top of the stack.

Condition Codes (also referred to as flags) are bits set by the CPU hardware as the result of the
operations. For example, an arithmetic operation may produce a positive, negative, zero or overflow
result. In addition to the result itself being stored in a register or memory, a condition code is also set.
The code may be subsequently tested as part of a condition branch operation. Condition code bits are
collected into one or more registers.

Register Organization

There are a variety of CPU registers that are employed to control the operation of the CPU. Most of
these, on most machines, are not visible to the user.

Different machines will have different register organizations and use different terminology. We will
discuss here the most commonly used registers which are part of most of the machines.

Four registers are essential to instruction execution:

Program Counter (PC): Contains the address of an instruction to be fetched. Typically, the PC is updated
by the CPU after each instruction fetched so that it always points to the next instruction to be executed.
A branch or skip instruction will also modify the contents of the PC.

Instruction Register (IR): Contains the instruction most recently fetched. The fetched instruction is
loaded into an IR, where the opcode and operand specifiers are analyzed (or decoded).

15
Memory Address Register (MAR): Contains the address of a location of main memory from where
information has to be fetched or information has to be stored. Content of MAR is directly connected to
the address bus.

Memory Buffer Register (MBR): Contains a word of data to be written to memory or the word most
recently read. A content of MBR is directly connected to the data bus. It is also known as Memory Data
Register (MDR).

Apart from these specific register, we may have some temporary registers which are not visible to the
user. As such, there may be temporary buffering registers at the boundary to the ALU; these registers
serve as input and output registers for the ALU and exchange data with the MBR and user visible
registers. Don’t forget that ALU is a combinational circuit as discussed in chapter two.

Processor Status Word

All CPU designs include a register or set of registers, often known as the processor status word (PSW)
that contains status information. The PSW typically contains condition codes plus other status
information. Common fields or flags include the following:

 Sign: Contains the sign bit of the result of the last arithmetic operation.
 Zero: Set when the result is zero.
 Carry: Set if an operation resulted in a carry (addition) into or borrow (subtraction) out
of a high order bit.
 Equal: Set if a logical compare result is equal.
 Overflow: Used to indicate arithmetic overflow.
 Interrupt enable/disable: Used to enable or disable interrupts.
 Supervisor: Indicate whether the CPU is executing in supervisor or user mode.
Certain privileged instructions can be executed only in supervisor mode, and certain
areas of memory can be accessed only in supervisor mode.

Apart from these, a number of other registers related to status and control might be found in a
particular CPU design. In addition to the PSW, there may be a pointer to a block of memory containing
additional status information (e.g. process control blocks which will be discussed in future courses).

Concept of Program Execution

The instructions constituting a program to be executed by a computer are loaded in sequential locations
in its main memory. To execute this program, the CPU fetches one instruction at a time and performs
the functions specified. Instructions are fetched from successive memory locations until the execution of
a branch or a jump instruction.

The CPU keeps track of the address of the memory location where the next instruction is located
through the use of a dedicated CPU register, referred to as the program counter (PC). After fetching an
instruction, the contents of the PC are updated to point at the next instruction in sequence.

For simplicity, let us assume that each instruction occupies one memory word. Therefore, execution of
one instruction requires the following three steps to be performed by the CPU:

16
 1. Fetch the contents of the memory location pointed at by the PC. The contents of this
location are interpreted as an instruction to be executed. Hence, they are stored in the
instruction register (IR). Symbolically this can be written as:
IR = [ [PC] ]

2. Increment the contents of the PC by 1. Why PC incremented by 1?

PC = [PC] + 1

3. Carry out the actions specified by the instruction stored in the IR.

The first two steps are usually referred to as the fetch phase and the step 3 is known as the execution
phase. Fetch cycle basically involves read the next instruction from the memory into the CPU and along
with that update the contents of the program counter. In the execution phase, it interprets the opcode
and performs the indicated operation. The instruction fetch and execution phase (including decode)
together known as instruction cycle. The basic instruction cycle is shown in the next figure.

Figure: Basic Instruction cycle

In cases, where an instruction occupies more than one word, step 1 and step 2 can be repeated as many
times as necessary to fetch the complete instruction. In these cases, the execution of an instruction may
involve one or more operands in memory, each of which requires a memory access. Further, if indirect
addressing is used, then additional memory access is required.

The fetched instruction is loaded into the instruction register. The instruction contains bits that specify
the action to be performed by the processor. The processor interprets (decodes) the instruction and
performs the required action. In general, the actions fall into four categories:

 Processor-memory: Data may be transferred from processor to memory or from

memory to processor. Called Data Storage.

 Processor-I/O: Data may be transferred to or from a peripheral device by transferring

between the processor and an I/O module. Called Data Movement.

 Data processing: The processor may perform some arithmetic or logic operation on
data. Called Data Processing.

 Control: An instruction may specify that the sequence of execution be altered. Called
Control.

17
The main line of activity consists of alternating instruction fetch and instruction execution activities.
After an instruction is fetched, it is examined to determine if any indirect addressing is involved. If so,
the required operands are fetched using indirect addressing.

The execution cycle of a particular instruction may involve more than one reference to memory. Also,
instead of memory references, an instruction may specify an I/O operation. With these additional
considerations the basic instruction cycle can be expanded with more details view in the next figure. The
figure is in the form of a state diagram.

Figure: Instruction cycle state diagram.

4.2.2. Processor Organization

There are several components inside a CPU, namely, ALU, control unit, general purpose register,
Instruction registers etc. Now we will see how these components are organized inside CPU. There are
several ways to place these components and interconnect them. One such organization is shown in the
next figure.

In this case, the arithmetic and logic unit (ALU), and all CPU registers are connected via a single common
bus. This bus is internal to CPU and this internal bus is used to transfer the information between
different components of the CPU. This organization is termed as single bus organization, since only one
internal bus is used for transferring of information between different components of CPU. We have
external bus or buses to CPU also to connect the CPU with the memory module and I/O devices. The
external memory bus is also shown in the next figure connected to the CPU via the memory data and
address register MDR and MAR. Remember this was discussed in chapter three.

The number and function of registers R0 to R(n-1) vary considerably from one machine to another. They
may be given for general-purpose for the use of the programmer. Alternatively, some of them may be
dedicated as special-purpose registers, such as index register or stack pointers.

In this organization, two registers, namely Y and Z are used which are transparent to the user. Do you
remember the meaning of transparent from chapter three? Programmer can’t directly access these two

18
registers. These are used as input and output buffer to the ALU which will be used in ALU operations.
They will be used by CPU as temporary storage for some instructions.

Figure: Single bus organization of the data path inside the CPU

For the execution of an instruction, we need to perform an instruction cycle. An instruction cycle
consists of two phase,

 Fetch cycle and

 Execution cycle.

Most of the operation of a CPU can be carried out by performing one or more of the following functions
in some pre-specified sequence:

1. Fetch the contents of a given memory location and load them into a CPU register.
2. Store a word of data from a CPU register into a given memory location.
3. Transfer a word of data from one CPU register to another or to the ALU.
4. Perform an arithmetic or logic operation, and store the result in a CPU register.

Now we will examine the way in which each of the above functions is implemented in a computer.

19
Fetching a Word from Memory:

Information is stored in memory location identified by their address. To fetch a word from memory, the
CPU has to specify the address of the memory location where this information is stored and request a
Read operation. The information may include both, the data for an operation or the instruction of a
program which is available in main memory.

To perform a memory fetch operation, we need to complete the following tasks:

The CPU transfers the address of the required memory location to the Memory Address Register (MAR).

The MAR is connected to the memory address line of the memory bus; hence the address of the
required word is transferred to the main memory.

Next, CPU uses the control lines of the memory bus to indicate that a Read operation is initiated. After
issuing this request, the CPU waits until it receives an answer from the memory, indicating that the
requested operation has been completed.

This is accomplished by another control signal of memory bus known as Memory-Function-Complete

(MFC).

The memory set this signal to 1 to indicate that the contents of the specified memory location are
available in memory data bus.

As soon as MFC signal is set to 1, the information available in the data bus is loaded into the Memory
Data Register (MDR) and this is available for use inside the CPU

As an example, assume that the address of the memory location to be accessed is kept in register R2 and
that the memory contents to be loaded into register R1. This is done by the following sequence of
operations:

1. MAR [R2] 2. Read

3. Wait for MFC signal 4. R1 [MDR]

The time required for step 3 depends on the speed of the memory unit. In general, the time required to
access a word from the memory is longer than the time required to perform any operation within the
CPU.

The scheme that is used here to transfer data from one device (memory) to another device (CPU) is
referred to as an asynchronous transfer.

This asynchronous transfer enables transfer of data between two independent devices that have
different speeds of operation. The data transfer is synchronized with the help of some control signals. In
this example, Read request and MFC signal are doing the synchronization task.

An alternative scheme is synchronous transfer. In this case all the devices are controlled by a common
clock pulse (continuously running clock of a fixed frequency). These pulses provide common timing
signal to the CPU and the main memory. A memory operation is completed during every clock period.

20
Though the synchronous data transfer scheme leads to a simpler implementation, it is difficult to
accommodate devices with widely varying speed. In such cases, the duration of the clock pulse will be
synchronized to the slowest device. It reduces the speed of all the devices to the slowest one. If CPU and
memory were communicating in synchronous mode, CPU would work with the speed of RAM.

Storing a word into memory

The procedure of writing a word into memory location is similar to that for reading one from memory.
The only difference is that the data word to be written is first loaded into the MDR, the write command
is issued.

As an example, assumes that the data word to be stored in the memory is in register R1 and that the
memory address is in register R2. The memory write operation requires the following sequence:

1. MAR [R2]
2. MDR [R1]
3. Write
4. Wait for MFC

In this case step 1 and step 2 are independent and so they can be carried out in any order. In fact, step
1 and 2 can be carried out simultaneously, if this is allowed by the architecture, that is, if these two data
transfers (memory address and data) do not use the same data path.

In case of both memory read and memory write operation, the total time duration depends on wait for
the MFC signal, which depends on the speed of the memory module.

There is a scope to improve the performance of the CPU, if CPU is allowed to perform some other
operation while waiting for MFC signal. During the period, CPU can perform some other instructions
which do not require the use of MAR and MDR.

Register Transfer Operation

Register transfer operations enable data transfer between various blocks connected to the common bus
of CPU. We have several registers inside CPU and it is needed to transfer information from one register
another. As for example during memory write operation data from appropriate register must be moved
to MDR.

Since the input output lines of all the register are connected to the common internal bus, we need
appropriate input output gating. The input and output gates for register R i are controlled by the signal Ri
in and Ri out respectively.

Thus, when Ri in set to 1 the data available in the common bus is loaded into Ri . Similarly when, Ri out is set
to 1, the contents of the register Ri are placed on the bus. To transfer data from one register to other
register, we need to generate the appropriate register gating signal. Remember from chapter two that
registers are made of D-flip flops, like SRAM. Registers are made of memory cell similar with those cells
that build main memory as discussed in chapter three.

For example, to transfer the contents of register R1 to register R2, the following actions are needed:

21
  Enable the output gate of register R1 by setting R1out to 1.
-- This places the contents of R1 on the CPU bus.
 Enable the input gate of register R2 by setting R2 in to 1.
-- This loads data from the CPU bus into the register R2

Performing the arithmetic or logic operation:

o Generally ALU is used inside CPU to perform arithmetic and logic operation. ALU is a
combinational logic circuit which does not have any internal storage as discussed in
chapter two.

Therefore, to perform any arithmetic or logic operation (say binary operation) both the input should be
made available at the two inputs of the ALU simultaneously. Once both the inputs are available then
appropriate signal is generated to perform the required operation.

We may have to use temporary storage (register) to carry out the operation in ALU.

The sequence of operations that have to carry out to perform one ALU operation depends on the
organization of the CPU. Consider an organization in which one of the operand of ALU is stored in some
temporary register Y and other operand is directly taken from CPU internal bus. The result of the ALU
operation is stored in another temporary register Z. This organization is shown in the next figure

Figure: Organization for Arithmetic & Logic Operation.

Therefore, the sequence of operations to add the contents of register R 1 to register R2 and store the
result in register R3 should be as follows:

22
 1. R1out, Yin
2. R2out, Add, Zin
3. Zout, R3in

In step 2 of this sequence, the contents of register R2 are gated to the bus, hence to input –B of the ALU
which is directly connected to the bus. The contents of register Y are always available at input A of ALU.
The function performed by the ALU depends on the signal applied to the ALU control lines. In this
example, the Add control line of ALU is set to 1, which indicate the addition operation and the output of
ALU is the sum of the two numbers at input A and B. The sum is loaded into register Z, since the input
gate is enabled (Zin). In step 3, the contents of register Z are transferred to the destination register R 3.

4.2.3. Execution of Complete Instruction

We have discussed about four different types of basic operations:
 Fetch information from memory to CPU
 Store information CPU register to memory
 Transfer of data between CPU registers.
 Perform arithmetic or logic operation and store the result in CPU registers.

To execute a complete instruction we need to take help of these basic operations and we need to
execute these operation in some particular order.

As for example, consider the instruction: "Add contents of memory location NUM to the contents of
register R1 and store the result in register R1." For simplicity, assume that the address NUM is given
explicitly in the address field of the instruction .That is, in this instruction, direct addressing mode is
used.
Execution of this instruction requires the following action:

1. Fetch instruction
2. Fetch first operand (Contents of memory location pointed at by the address
field of the instruction)
3. Perform addition
4. Load the result into R1.

Following sequence of control steps are required to implement the above operation for the single-bus
architecture that we have discussed in earlier section.

Steps Actions

1. PCout, MARin, Read, Clear Y, Set carry -in to ALU, Add, Zin
2. Zout, PCin, Wait For MFC
3. MDRout, Irin
4. Address-field- of-IRout, MARin, Read
5. R1out, Yin, Wait for MFC
6. MDRout, Add, Zin
7. Zout, R1in
8. END

23
Instruction execution proceeds as follows:

In Step 1:

The instruction fetch operation is initiated by loading the contents of the PC into the MAR and sending a
read request to memory

To perform this task first of all the contents of PC have to be brought to internal bus and then it is
loaded to MAR. To perform this task control circuit has to generate the PCout signal and MARin signal.

After issuing the read signal, CPU has to wait for some time to get the MFC signal. During that time PC is
updated by 1 through the use of the ALU. This is accomplished by setting one of the inputs to the ALU
(Register Y) to 0 and the other input is available in bus which is current value of PC.

At the same time, the carry-in to the ALU is set to 1 and an add operation is specified.

In Step 2:

The updated value is moved from register Z back into the PC. Step 2 is initiated immediately after issuing
the memory Read request without waiting for completion of memory function. This is possible, because
step 2 does not use the memory bus and its execution does not depend on the memory read operation.

In Step 3:

Step3 has been delayed until the MFC is received. Once MFC is received, the word fetched from the
memory is transferred to IR (Instruction Register), because it is an instruction. Step 1 through 3
constitutes the instruction fetch phase of the control sequence.

The instruction fetch portion is same for all instructions. Next step onwards, instruction execution phase
takes place.

As soon as the IR is loaded with instruction, the instruction decoding circuits interprets its contents. This
enables the control circuitry to choose the appropriate signals for the remainder of the control
sequence, step 4 to 8, which we referred to as the execution phase. To design the control sequence of
execution phase, it is needed to have the knowledge of the internal structure and instruction format of
the PU. Secondly, the length of instruction phase is different for different instruction.

In this example, we have assumed the following instruction format:

opcode M R

i.e., opcode: Operation Code

M: Memory address for source
R: Register address for source/destination

In Step 5:

24
The destination field of IR, which contains the address of the register R1, is used to transfer the contents
of register R1 to register Y and wait for Memory function Complete. When the read operation is
completed, the memory operand is available in MDR.

In Step 6:

The result of addition operation is performed in this step.

In Step 7:

The result of addition operation is transferred from temporary register Z to the destination register R1 in
this step.

In step 8:

It indicates the end of the execution of the instruction by generating End signal. This indicates
completion of execution of the current instruction and causes a new fetch cycle to be started by going
back to step 1

Branching

With the help of branching instruction, the control of the execution of the program is transferred from
one particular position to some other position, due to which the sequence flow of control is broken.
Branching is accomplished by replacing the current contents of the PC by the branch address, that is,
the address of the instruction to which branching is required.

Consider a branch instruction in which branch address is obtained by adding an offset X, which is given
in the address field of the branch instruction, to the current value of PC.

Consider the following unconditional branch instruction

JUMP X

i.e., the format is

op- code offset of jump

The control sequence that enables execution of an unconditional branch instruction using the single -
bus organization is as follows:
Steps Actions
1. PCout, MARin, Read, Clear Y, Set Carry-in to ALU, Add ,Zin
2. Zout, PCin, Wait for MFC
3. MDRout, IRin
4. PCout, Yin
5. Address field-of IRout, Add, Zin
6. Zout, PCin
7. End

25
Execution starts as usual with the fetch phase, ending with the instruction being loaded into the IR in
step 3. To execute the branch instruction, the execution phase starts in step 4.

In Step 4

The contents of the PC are transferred to register Y.

In Step 5

The offset X of the instruction is gated to the bus and the addition operation is performed.

In Step 6

The result of the addition, which represents the branch address, is loaded into the PC.

In Step 7

It generates the End signal to indicate the end of execution of the current instruction

Consider now the conditional branch instruction instead of unconditional branch. In this case, we need
to check the status of the condition codes, between step 3 and 4 i.e., before adding the offset value to
the PC content.

For example, if the instruction decoding circuitry interprets the contents of the IR as a branch on
Negative (BRN) instruction, the control unit proceeds as follows: First the condition code register is
checked. If bit N (negative) is equal to 1, the control unit proceeds with step 4 through step 7 of control
sequence of unconditional branch instruction.

If, on the other hand, N is equal to 0, and End signal is issued.

This in effect, terminates execution of the branch instruction and causes the instruction immediately
following in the branch instruction to be fetched when a new fetch operation is performed.

Therefore, the control sequence for the conditional branch instruction BRN can be obtained from the
control sequence of an unconditional branch instruction by replacing the step 4 by

4. If then End
If N then PCout, yin

Most commonly need conditional branch instructions are

BNZ : Branch on not Zero
BZ : Branch on positive
BP : Branch on Positive
BNP : Branch on not Positive
BO : Branch on overflow

4.3. Introduction to Control Unit (Reading Assignment)

26