Lecture 12

Synchronous Sequential Circuits (2)

TJLee
Fall, 2021
 Types of FSM
◼ Moore machine ◼ Mealy-type machine (or Mealy machine)
◼ The output values are generated based
Reset
on both the state of the circuit and the
w=1 present values of its input.
w=0 A z = 0 B z = 0
◼ Only two states are needed in this
w=0
example.
w=0 w=1
Reset
w = 1z = 0
C z = 1
w= 0z =0 A B w = 1z = 1

w=1 w = 0z = 0
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t 10
1 1
Clock Clock
0 0
1
w
1 0
w
0 1
y
0
1 1
y1 z
0 0

1
y2
0

1
z
0
 Detection of Input Sequence, 11 (Mealy Machine)
◼ Moore machine

Clockcycle: t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
w: 0 1 0 1 1 0 1 1 1 0 1
z: 0 0 0 0 0 1 0 0 1 1 0
Figure 6.2.

◼ Mealy machine
◼ The output z is equal to 1 in the same clock cycle when the second occurence
of w =1 is detected.

Clock cycle: t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10

w: 0 1 0 1 1 0 1 1 1 0 1
z: 0 0 0 0 1 0 0 1 1 0 0

Figure 6.22. Sequences of input and output signals.

 Detection of Input Sequence, 11 (Mealy-type)
◼ State diagram ◼ State table
Reset
w = 1z = 0
Present Next state Output z
w= 0z =0 A B w = 1z = 1 state w= 0 w= 1 w= 0 w= 1
w = 0z = 0 A A B 0 0
B A B 0 1

Figure 6.23. State diagram of an FSM that Figure 6.24. State table for the
realizes the task in Figure 6.22. FSM in Figure 6.23.

◼ State-assigned table

Present Next state Output

state w= 0 w= 1 w= 0 w= 1
y Y Y z z
A 0 0 1 0 0
B 1 0 1 0 1

Figure 6.25. State-assigned table for the

FSM in Figure 6.24.
 Detection of Input Sequence, 11 (Mealy-type)
◼ The greater flexibility of Mealy-type FSMs often leads to simpler circuit
realizations.
z

w D Q y
Clock Q

Resetn

(a) Circuit

t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
1
Clock
0
1
w
0
y 1
0
z 1
0

(b) Timing diagram

Figure 6.26. Implementation of FSM in Figure 6.25.

 Detection of Input Sequence, 11
◼ The difference between Fig 6.26 and Fig. 6.8 is a shift of one clock cycle in the output signal.
◼ If we wanted to produce exactly the same output using the Mealy approach, we could modify
the circuit by adding another flip-flop, as shown in Fig. 6.27.
z
D Q Z

w D Q Q
y

Clock
Resetn

(a) Circuit

t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t 10
1
Clock
0
1
w
0
1
y
0 Figure 6.27. Circuit that
1
z implements the specification
0
1
in Figure 6.2.
Z
0

(b) Timing diagram

 Detection of Input Sequence, 11 (Mealy-type)
module mealy (Clock, Resetn, w, z);
input Clock, Resetn, w;
output reg z;
reg y, Y;
parameter A = 1’b0, B = 1’b1;
// Define the next state and output combinational circuits
always @(w, y)
Reset case (y)
w = 1z = 0 A: if (w)
begin
w= 0z =0 A B w = 1z = 1 z = 0;
Y = B;
end
w = 0z = 0 else
begin
Figure 6.23. State diagram of an FSM that z = 0;
Y = A;
realizes the task in Figure 6.22. end
B: if (w)
begin
z = 1;
Y = B;
A change in w will immediately end
reflect itself in the value of z if else
begin
the machine is in state B, z = 0;
which meets the requirements Y = A;
end
of the Mealy-type FSM. endcase

// Define the sequential block

always @(negedge Resetn, posedge Clock)
if (Resetn = = 0) y <= A;
Figure 6.36. Verilog code for the Mealy else y <= Y;
machine of Figure 6.23.
endmodule
 Simulation Results

Figure 6.37. Simulation results for the Mealy machine.

 Example 6.4
◼ Mealy-type of the circuit in example 6.1.

w = 0

A Reset

w = 1  R2 = 1, R 3 = 1
out in

w = 0 R1 = 1, R 2 = 1
w = 1 out in

w = 0 R3 = 1, R 1 = 1 , Done = 1
w = 1 out in

Figure 6.28. State diagram for Example 6.4.

 Potential problem with asynchronous inputs to a Mealy FSM

z
1 0 1 1 0 1 1 1 0 0
w D Q
y
Clock Q

Resetn

A change in w will immediately Figure 6.37. Simulation results for the Mealy machine.
reflect itself in the value of z if
the machine is in state B,
which meets the requirements
of the Mealy-type FSM.

1 0 1 1 0
Figure 6.38. Potential problem
with asynchronous inputs to a
Mealy FSM.
An erroneous 50 ns pulse generated, if the input is not
synchronized with positive-edge of clock. Is that alright?
 Example: Serial Adder
◼ If speed is not of great importance, then a cost-effective option is to use a serial
adder, in which bits are added a pair at a time.
A

a
Shift register
s
Adder
FSM Shift register
Shift register
b
Sum = A + B
B
Clock
Figure 6.39. Block diagram for the serial adder.

a s
Full
b
adder Y y
D Q
carry-out

Clock Q

Figure 6.43. Circuit for the adder

Reset
FSM in Figure 6.39.
 Example: Serial Adder
◼ State diagram ◼ State diagram
Reset ( ab  s )
11  0 Present Next state Output s
state ab =00 01 10 11 00 01 10 11
00  0 01  0
01  1 G H 10  0 G G G G H 0 1 1 0
10  1 11  1 H G H H H 1 0 0 1

00  1 Figure 6.41. State table for the serial adder FSM.

G: carry-in = 0 ◼ State-assigned table
H: carry-in = 1

Figure 6.40. State diagram for the Next state Output

Present
serial adder FSM. state ab =00 01 10 11 00 01 10 11
y Y s
0 0 0 0 1 0 1 1 0
1 0 1 1 1 1 0 0 1

Figure 6.42. State-assigned table for

Figure 6.41.
s=a+b+y
 Example: Serial Adder (Moore-type)
◼ State diagram ◼ State diagram
Reset
Present Nextstate Output
state ab =00 01 10 11 s
11 01
00 G0  s = 0 H0  s = 0 10 G0 G0 G1 G1 H0 0
G1 G0 G1 G1 H0 1
00 H0 G1 H0 H0 H1 0
01 00 11 01
10 11 10 H1 G1 H0 H0 H1 1
Figure 6.45. State table for the Moore-type serial
01 G1  s = 1 H1  s = 1 11 adder FSM.
10 00 ◼ State-assigned table
Figure 6.44.
Nextstate
Present
state ab =00 01 10 11 Output
y 2y 1 s
Y2Y1
00 00 01 01 10 0
01 00 01 01 10 1
10 01 10 10 11 0
11 01 10 10 11 1

Figure 6.46. State-assigned table for

Figure 6.45.
 Example: Serial Adder (Moore-type)
◼ Circuit of the adder FSM (Moore-type) in Fig. 6.39.

Sum bit Y1 y1
a D Q s
Full
b
adder Carry-out
Q

Y2 y2
D Q

Clock Q

Reset

Figure 6.47. Circuit for the Moore-type serial adder FSM.

 Example: Serial Adder – Shift Register Sub-circuit
◼ Shift register subcircuit module shiftrne (R, L, E, w, Clock, Q);
A parameter n = 8;
a input [n-1:0] R;
Shift register
Adder
s input L, E, w, Clock;
FSM Shift register
output reg [n-1:0] Q;
Shift register
b
Sum = A + B
integer k;
B
Clock always @(posedge Clock)
if (L)
Q <= R;
else if (E)
begin
for (k = n-1; k > 0; k = k-1)
Q[k-1] <= Q[k];
Q[n-1] <= w;
end

endmodule

Figure 6.48. Code for a left-to-right shift

register with an enable input.
 module serial_adder (A, B, Reset, Clock, Sum);
input [7:0] A, B;

Example: Serial Adder input Reset, Clock;

output wire [7:0] Sum;
reg [3:0] Count;
reg s, y, Y;
◼ Serial adder wire [7:0] QA, QB;
wire Run;
A parameter G = 1’b0, H = 1’b1;

a shiftrne shift_A (A, Reset, 1’b1, 1’b0, Clock, QA);

Shift register shiftrne shift_B (B, Reset, 1’b1, 1’b0, Clock, QB);
s
Adder shiftrne shift_Sum (8’b0, Reset, Run, s, Clock, Sum);
FSM Shift register
Shift register
b // Adder FSM
Sum = A + B // Output and next state combinational circuit
B always @(QA, QB, y)
Clock case (y)
G: begin
s = QA[0] ^ QB[0];
if (QA[0] & QB[0]) Y = H;
else Y = G;
end
H: begin
s = QA[0] ~^ QB[0];
if (~QA[0] & ~QB[0]) Y = G;
else Y = H;
end
default: Y = G;
endcase

// Sequential block
always @(posedge Clock)
if (Reset) y <= G;
else y <= Y;

// Control the shifting process

always @(posedge Clock)
if (Reset) Count = 8;
else if (Run) Count = Count - 1;
assign Run = |Count;

Figure 6.49. Verilog code for the serial adder. endmodule

Synthesized serial adder
1 0 0 0

a7 a0 D3 D2 D1D0
L
E Counter
L
0 w Q3 Q2Q1Q0
1 E

b7 b0 Adder
FSM
Run
L 0 0
0 w
1 E
L
w
E
Clock
Reset
Sum7 Sum0

Figure 6.50. Synthesized serial adder.

 State Minimization
◼ Definition 6.1 Two states Si and Sj are said to be equivalent if and only if
for every possible input sequence, the same output sequence will be
produced regardless of whether Si or Sj is the initial state.

◼ Definition 6.2 A partition consists of one or more blocks, where each

block comprises a subset of states that may be equivalent, but the states in
a given block are definitely not equivalent to the states in other blocks.
 Example 6.6: State minimization
Present Next state Output Present Nextstate Output
state w = 0 w = 1 z state w= 0 w= 1 z

A B C 1 A B C 1
B D F 1 B A F 1
C F E 0 C F C 0
D B G 1 F C A 0
E F C 0
Figure 6.52. Minimized state table for
F E D 0
Example 6.6.
G F G 0
P3 = (ABD)(CEG)(F)
Figure 6.51. State table for Example 6.6. (ABD) 0-sucessors: (BDB) → in the same block
(ABD) 1-sucessors: (CFG) → not in the same block
(CEG) 0-sucessors: (FFF) → in the same block
(CEG) 1-sucessors: (ECG) → in the same block
P1 = (ABCDEFG) P4 = (AD)(B)(CEG)(F)
P2 = (ABD)(CEFG) P5 = (AD)(B)(CEG)(F)
(ABD) 0-sucessors: (BDB) → in the same block
(ABD) 1-sucessors: (CFG) → in the same block
(CEFG) 0-sucessors: (FFEF) → in the same block
(CEFG) 1-sucessors: (ECDG) → not in the same block
P3 = (ABD)(CEG)(F)
 Example 6.7: The Vending Machine
◼ The machine accepts nickels (5 cents) and dimes (10 cents).
◼ It takes 15 cents for a piece of candy to be released from the machine.
◼ If 20 cents is deposited, the machine will not return the change, but it will credit the buyer
with cents and wait for the buyer to make a second purchase.

Clock

senseN

senseD

(a) Timing diagram

N
senseN D Q D Q

Clock Q Q

Figure 6.53. Signals for the

vending machine. (b) Circuit that generates N
 Example 6.7: The Vending Machine
◼ State diagram ◼ State table
DN
Present Next state Output
Reset
DN state DN =00 01 10 11 z
DN S1  0 DN
S1 S1 S3 S2 – 0
DN DN
D N S2 S2 S4 S5 – 0
S3 S3 S6 S7 – 0
D
S4  1 S2  0 S3  0 S7  1 S4 S1 – – – 1
N
S5 S3 – – – 1
D N
DN S6 S6 S8 S9 – 0
S5  1 S6  0 DN DN
S7 S1 – – – 1
S8 S1 – – – 1
N D
S9 S3 – – – 1
Figure 6.55. State table for Example 6.7.
S8  1 S9  1
◼ Minimized state table

Figure 6.54. State diagram for Example 6.7. Present Next state Output
state DN =00 01 10 11 z
P1 = (S1, S2, S3, S4, S5, S6, S7, S8, S9)
P2 = (S1, S2, S3, S6)(S4, S5, S7, S8, S9) S1 S1 S3 S2 – 0
P3 = (S1)(S3)(S2, S6)(S4, S5, S7, S8, S9) S2 S2 S4 S5 – 0
P4 = (S1)(S3)(S2, S6)(S4, S7, S8)(S5, S9) S3 S3 S2 S4 – 0
P5 = (S1)(S3)(S2, S6)(S4, S7, S8)(S5, S9) S4 S1 – – – 1
S5 S3 – – – 1
Figure 6.56. Minimized state table for
Example 6.7.
 Example 6.7: The Vending Machine
DN DN  0

S1  0 S1

N N0 D1
DN
DN  0
S3  0
D
N1 S3 D0
DN N DN

D N0 D1
DN S2  0 S5  1

N S2
D
S4  1
DN  0
Figure 6.57. Minimized state diagram
for Example 6.7. Figure 6.58. Mealy-type FSM for
Example 6.7.
 Practice
◼ Problem 6.30 Write Verilog code for the FSM shown in Figure 6.57,
using the style of code in Figure 6.29.
◼ Problem 6.32 Write Verilog code for the FSM shown in Figure 6.58,
using the style of code in Figure 6.29.
 Incompletely Specified FSMs
◼ Completely Specified ◼ Incompletely Specified FSM
◼ In Example 6.7, the partitioning
scheme works well.
Present Next state Output ◼ But in general, the partitioning
state w = 0 w = 1 z scheme is less useful when
incompletely specified FSMs are
A B C 1
involved.
B D F 1
C F E 0 Next state
Present Output
D B G 1 state z
DN =00 01 10 11
E F C 0
F E D 0 S1 S1 S3 S2 – 0
S2 S2 S4 S5 – 0
G F G 0
S3 S3 S6 S7 – 0
S4 S1 – – – 1
Figure 6.51. State table for Example 6.6. S5 S3 – – – 1
S6 S6 S8 S9 – 0
S7 S1 – – – 1
S8 S1 – – – 1
S9 S3 – – – 1
Figure 6.55. State table for Example 6.7.
 Example 6.8: Incompletely Specified FSM

Present Next state Output z

Case 2: assume both unspecified
state w = 0 w = 1 w = 0 w = 1 outputs are 1.
A B C 0 0 P1 = (ABCDEFG)
B D – 0 – P2 = (AD)(BCEFG)
C F E 0 1 P3 = (AD)(B)(CEFG)
D B G 0 0 P4 = (AD)(B)(CEG)(F)
E F C 0 1 P5 = P4
F E D 0 1  Four states!
G F – 0 –
■The choice of values assigned to
Figure 6.59. Incompletely specified state table unspecified outputs is important.
for Example 6.8. ■ Reducing the number of states in a
Case 1: assume both unspecified outputs given FSM will not necessarily lead to
are 0. a simpler implementation.
P1 = (ABCDEFG)
P2 = (ABDG)(CEF)
P3 = (AB)(D)(G)(CE)(F)
P4 = (A)(B)(D)(G)(CE)(F)
P5 = P4
=> Six states!