National University of Sciences and Technology
College of Electrical and Mechanical Engineering
Department of Computer & Software Engineering
Midterm-Term Exam, Fall 2025
Subject Code: EC-220 Subject: Computer System Architecture
Date: 28th October 2025 Time: 1.5-hours
Instructor: Dr. Shahid Ismail Max Marks: 60
Student Name: Registration No: Deg/Synd:
NOTE:
Students should score 50% in OBE-specific questions to ensure their accumulated scores towards respective
PLOs are above 50%.
If you think something is wrong with any of the questions, make and state an appropriate assumption and use it to
solve the problem.
Write concisely and to the point. Manage your time wisely.
Marks will be deducted if your handwriting is not clear and legible.
Students can bring their RISC-V ISA card.
Q1. (2*6 = 12) (CLO-1/PLO-1)
1. Translate the factorial C code given below to RISCV assembly language
int fact (int n)
{
if (n < 1) return (1);
else return (n * fact(n − 1));
}
2. Illustrate a block diagram of stack for a 5 length Fibbonaci sequence
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Q2. (2+1+2+7=12) (CLO-2/PLO-2)
Analyze the Table given below to
Instruction Type Fetch Register ALU Memory Write Register Total
Read Operation Access
Load 200 100 200 200 100 800
Store 200 100 200 200 700
R-Format 200 100 200 100 600
Branch 200 100 200 500
1. Calculate,
Time duration for single cycle for all instructions
Time duration for all instructions will be same as the time duration is selected w.r.t to slowest
instruction which in present case is 800.
Time duration for multicycle for all instructions
Time duration for all instructions will vary as per instruction, hence, above table can be used
as reference for different instructions.
The percentage save in case of individual instructions as well as overall saving
Instruction Type Multi Single Individual Percentage save
Cycle Cycle save
Load 800 800 0 MC = 2600
Store 700 800 100 SC = 3200
R-Format 600 800 200 Total Save = 600
Branch 500 800 300 % save = 18.75
2. Design a circuit for Immediate generation in case of Multicycle using load word, store word, r-type
and beq.
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Q3. (3*4=12) (CLO3/PLO-3)
Examine the Table given below to design a memory as lookup table
Input Output
2 0
128 0
65 0
32767 1
4000 1
500 1
200 0
107 0
220 0
335 0
1. For the numbers (Unsigned) in the Table,
Calculate the minimum number of bits which are required to represent a cell which includes
input and output
Minimum bits per cell (input + output)
Largest input = 32767.
Find bits needed for unsigned 32767:
o 214 = 16384(too small)
o 215 = 32768
⇒ 15 bits required to represent the input.
Output is binary ⇒ 1 bit.
Total bits per cell = 15 + 1 = 16 bits.
Calculate size of total memory for cells (input and output)
Size of total memory for the 10 cells
Bits: 10 × 16 = 160bits.
Bytes: 160/8 = 20bytes.
So 160 bits = 20 bytes.
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Calculate the number of address lines to read a cell containing a number and binary output.
Number of address lines to read one cell
Need enough addresses to index 10 cells: address lines = ⌈log 2 10⌉.
log 2 10 ≈ 3.3219⇒ ⌈3.3219⌉ = 4.
Address lines = 4 (since 24 = 16cover 10 entries).
2. Now consider that instead of 10 numbers, we have 32767 numbers, calculate the number of address line
to read a cell containing a number and binary output. Also give the total memory in bytes/kilobytes etc.
(whichever seems more appropriate)
We have 32,767 numbers
Number of address lines = ⌈log 2 32767⌉.
215 = 32768and 32767 = 215 − 1⇒ need 15 address lines.
Answer: 15 address lines.
Q4. (4+2+6 = 12)
add x9, x5, x6
addi x9, x9, -3
ori x9, x9,1
li x1,0x0000FFFF
and x9, x9, x1
For the set of instructions, consider a single cycle computer
Machine encoding in binary and hex
Instruction Binary Hex
add x9, x5, x6 00000000011000101000010010110011 0x006282B3
addi x9, x9, -3 11111111110101001000010010010011 0xFFD48493
ori x9, x9, 1 00000000000101001110010010010011 0x0014E493
li x1, 0x0000FFFF → expands to:
• lui x1, 0x1 00000000000000000001000010110111 0x000010B7
• addi x1, x1, -1 11111111111100001000000010010011 0xFFF08093
and x9, x9, x1 00000000000101001111010010110011 0x0014C4B3
Highlight the part of processor which will be used. General solution will be given 0 marks
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Make ori to flow through circuit generating all control signals.
Signal Value for ori x9,x9,1 Explanation
opcode 0010011 instruction field
funct3 110 OR immediate
RegWrite 1 write ALU result into rd
ALUSrc 1 second ALU operand = immediate
ImmSel I use I-type immediate generator (12-bit sign-extend)
ALUOp / ALUControl OR derived from opcode+funct3
MemRead 0 no load
MemWrite 0 no store
MemToReg 0 writeback uses ALU result not memory
Branch 0 not a branch
Jump / Jal / Jalr 0 not a jump
PCSrc PC+4 sequential PC update
RF read ports used rs1 (x9) read; rs2 not used because ALUSrc=1
RF write port rd = x9 set by RegWrite & rd field
Immediate value used 0x00000001 (sign-extended) imm[11:0] → 32-bit 1
ALU inputs A = RF[x9], B = 0x00000001 ALU does A OR B
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Q5. (3+3+3+3 = 12)
Consider x5 and x6 as {2,1} for the set of instructions given Q4 to flow through a single cycle computer to
Report value of x9 at the end of sequence?
add x9, x5, x6 X9 = 3=2+1
addi x9, x9, -3 X9 = 0=3-3
ori x9, x9,1 X9 = 1
li x1,0x0000FFFF lui x1, 0x1 # load upper 20 bits (0x1 << 12 = 0x1000)
addi x1, x1, -1 # subtract 1 to get 0x0000FFFF
and x9, x9, x1 X9 = 1&1 = 1
Discuss, why is li being used?
To load 0x0000FFFF which can not be loaded into x1 as maximum value can be -2048-2047
Extend the code to include conditional/ unconditional jump where appropriate
add x9, x5, x6 X9 = 3=2+1
addi x9, x9, -3 X9 = 0=3-3
ori x9, x9,1 X9 = 1
li x1,0x0000FFFF lui x1, 0x1 # load upper 20 bits (0x1 << 12 = 0x1000)
addi x1, x1, -1 # subtract 1 to get 0x0000FFFF
and x9, x9, x1 X9 = 1&1 = 1
Detail the types of extension in RISCV
There are 5 extensions (RV32M, RV32A, RV32F, and RV32C)
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