Solid State Sciences 13 (2011) 294e305

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Solid State Sciences

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Source/drain technologies for the scaling of nanoscale CMOS device

Yi Song*, Huajie Zhou, Qiuxia Xu
Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China

a r t i c l e i n f o a b s t r a c t

Article history: Continuous shrinking CMOS device into 21 nm technology node is facing fundamental challenges. The
Received 12 October 2010 International Technology Roadmap for Semiconductors (ITRS) forecasts specific requirements to realize
Accepted 2 December 2010 acceptable CMOS performance for the semiconductor industry. The innovations of various source/drain
Available online 13 December 2010
technologies are considered to be indispensable for the continuous scaling of CMOS device due to the
requirements of high-performance and effective suppression of short channel effects. One of the key
Keywords:
points is to realize ultra-shallow junction with steep concentration profile and low resistivity. There are
Nanoscale CMOS device
many innovative solutions including advanced doping technologies and annealing technologies for ultra-
Ultra-shallow junction
Raised source/drain
shallow junction formation. Additionally, new source/drain structures such as raised source/drain and
Schottky barrier source/drain Schottky barrier metal source/drain, and advanced silicidation technologies also serve as the important
options. The state-of-the-arts of these new technologies are extensively discussed from the view point of
technical innovation and performance gain. Source/drain technologies are promising and active areas of
device research down to 21 nm technology node and even beyond.
Ó 2010 Elsevier Masson SAS. All rights reserved.

1. Introduction thermal budget, high Schottky barrier, poor phase control and
interface quality and so on [3]. The dopants activation concentra-
As MOSFET feature dimension shrinks down to 21 nm range, tion is limited by its solid solubility. Moreover, the fast diffusion of
nanoscale processes encounter tremendous difficulties, for instance, boron makes ultra-shallow source/drain junction of pMOS more
severe short channel effects, degraded driving ability, boron pene- challenging. Intensive investigations such as ultra-low energy ion
tration and poly-silicon depletion, high-field effects, direct gate implantation with large beam current, surface pre-amorphous [4]
tunneling current and high series resistance etc. Keeping Moore’s and laser annealing technology [5], make it possible to obtain
law valid encounters unprecedented difficulties. Table 1 gives the abrupt and uniform ultra-shallow junction. Moreover, raised
main projected targets for high-performance logic technology at source/drain and metal Schottky barrier source/drain also serve as
21 nm technology node proposed by ITRS [1]. The 21 nm technology potential solutions. These innovative technologies are extensively
node will be realized in 2015 with the physical gate length only discussed below.
17 nm. Tremendous technical innovations in new material, new
process techniques, new device architectures are required to 2. Ultra-shallow junction formation
promote CMOS device ahead towards 21 nm technology node.
Source/drain region as a key component in MOSFET structure Source/drain junction depth scales continuously together with
receives considerable attentions. Fig. 1 summarizes the main diffi- the gate lengths in order to suppress short channel effects. The
cult challenges with source/drain in the scaling of traditional planar formation of ultra-shallow junction with abrupt doping profile and
bulk MOSFET. The key of source/drain (S/D) engineering is to form low sheet resistance is pre-requisite. However, there are tremen-
abrupt and ultra-shallow junction, however, the ultra-shallow dous technical challenges such as the transient-enhanced diffusion
source/drain junction brings about extremely high parasitic resis- [6] and solid solubility limitation [7] for achieving ultra-shallow
tance and contact resistance [2]. Significant challenges exist in junctions using the conventional doping strategies by the combi-
silicides as device scaling, such as high sheet resistance, Fermi level nation of ion implantation and spike annealing. Advanced doping
pinning, linewidth effects, agglomeration for thinner silicides, high technologies to obtain shallow doping profiles such as C co-
implantation, heavier implantation dopant sources (cluster ion),
plasma doping and molecular monolayer doping, and advanced
* Corresponding author. annealing techniques to activate the dopants without causing
E-mail address: songyi@[Link] (Y. Song). significant diffusion such as flash and laser annealing are explored.

1293-2558/$ e see front matter Ó 2010 Elsevier Masson SAS. All rights reserved.
doi:10.1016/[Link].2010.12.002
 Y. Song et al. / Solid State Sciences 13 (2011) 294e305 295

Table 1
High-performance Logic Technology Requirements for extended planar bulk at 21 nm technology node proposed by ITRS 2009 edition.

MPU physical Junction depth or Electrical Equivalent Oxide Effective parasitic S/D
gate length (nm) body thickness (nm) Thickness in inversion (Å) series resistance (U mm)
17 7.3 8.2 110

Average Vdd (V) Maximal Ion/Ioff (mA/mm) Saturated threshold voltage (V) Intrinsic delay (ps)
0.81 1680/0.1 (nmos), 1377/0.1 (pmos) j0.302j 0.45 (nmos)/0.55 (pmos)

The junction uniformity, metal contamination, reliability and activated carrier concentration for a BF2 implanted device (left) and
repeatability, dosimetry, junction leakage and subsequent process a C co-implanted device (right) after spike annealing.
integration of these advanced doping and annealing techniques As for C co-implanted case, the boron vertical diffusion is
should be well considered. The main issues and recent progresses significantly reduced as the SDE vertical junction depth is
on these advanced technologies are discussed below. dramatically reduced from 38 to 14 nm and the heavily doped drain
junction depth is decreased from 90 to 82 nm. In addition, C co-
2.1. Advanced doping technologies implant also strongly suppresses the boron lateral diffusion such
that the gate/SDE overlap is shrunk from 22 to 10 nm. The overlap
Co-implantation which include phosphorous (P) or arsenic (As) capacitance is reduced due to shallower junction depths and
together with low energy carbon (C) implantation into crystalline Si reduced lateral diffusion. The higher Ion is the reflection of lower
is used for 45 nm nMOS ultra-shallow junction formation [8]. C co- series resistance due to improved dopant activation.
implantation gives more abrupt, shallow and well activated junc- It is more difficult to fabricate ultra-shallow pþn junction
tions than dopant-only cases. because of the lowmolecular weight and fast diffusion velocity of
A known drawback of this kind of co-implantation is junction Boron. High-mass dopant species such as B18Hþ x ion implantation is
leakage caused by Carbon deep levels, therefore, it is necessary to another attracting solution for ultra-shallow source/drain forma-
optimize the location and amount of Carbon with respect to Si tion [12]. B18Hþ þ
x shows the same or better characteristics than B in
interstitials [9]. High energy silicon pre-amorphous process and junction depth and sheet resistance. Post-processing electrical
fast anneal step are necessary to locate the C atoms in substitutional measurements of the pMOS implanted with B18Hþ x show that they
sites. The role of C in reducing enhanced diffusion of dopants performed with nearly identical characteristics as ones implanted
implanted in pre-amorphous Si is to trap Si interstitials that with Bþ. B18Hþ x implantation could be used to produce ultra-
responsible of dopants diffusion [10]. Abrupt and well activated shallow junctions for MOSFET fabrication at production-worthy
doping (P) profiles are realized by localizing the C profile at an throughputs with less energy contamination.
optimum position. The junction with 20.5 nm in depth, Rs ¼ 318 U/ Pulsed plasma doping (P2LAD) is another doping technique for
, and a 3 nm/dec trailing slope is achieved. the formation of ultra-shallow junctions in silicon wafers [13,14]. In
Intensive efforts have been made to extend the co-implantation the P2LAD technique, a pulsed negative voltage applied to the
scheme into sub45 nm gate length devices [11]. The key of this silicon substrate creates plasma containing the desired dopant
scheme is the combination of co-implantation of a diffusion- species and accelerates the positive dopant ions from the plasma
retarding species (i.e. Carbon) and Bþ for pMOS or Pþ for nMOS toward the substrate, where they are implanted. BF3 plasmas are
with a high temperature, millisecond annealing process after the used to form pþn junctions, while AsH and PH plasmas are used for
conventional spike annealing. Thus reduced junction depths with the formation of nþp junctions. The wafer bias and implant dose
abrupt profiles and improved dopant activation are achieved. determine the junction depth and sheet resistance. Good sheet
Submelt laser annealing would further improve junction activation resistance uniformity, charging performance, structural quality,
and reduce gate depletion. Fig. 2 shows the two-dimensional and photoresist integrity are observed. The P2LAD process is
scanning spreading resistance microscopy (SSRM) images of compatible with CMOS device processing, and do not generate

Fig. 1. Difficult challenges with source/drain in CMOS device at 21 nm technology node.

296 Y. Song et al. / Solid State Sciences 13 (2011) 294e305

Fig. 2. The SSRM images of activated carrier concentration for a BF2 implanted device (left) and a C co-implanted device (right) after spike annealing [11].

much sources of damage. Silicon-on-insulator (SOI) nMOS with [18]. The junctions formed by this process which show a minimal
a 50 nm-length metal gate are fabricated [15], which the source and junction leakage current of less than 1 mA/cm2, indicating no
drain extensions (SDE) are formed by such plasma doping tech- defects was generated during the process.
nique. A laterally abrupt source/drain junction with low sheet As shown in Fig. 4, the key of monolayer doping (MLD) process is
resistance is obtained without additional activation annealing. the formation of self-assembled dopant-containing monolayer on
In-situ Helium pre-amorphization (He-PA) combined with the crystalline silicon surfaces, followed by the diffusion of dopants
flash-lamp annealing or laser annealing could be introduced to from the surface into the lattice by a thermal annealing step.
plasma doping (PD) method [16]. High dose and ultra-shallow as- In detail, 4 in. p-type Si wafers are first treated with dilute
doped profiles are optimized by adjusting B2H6 PD conditions. The hydrofluoric acid (1%) to remove the native SiO2. The Si surface is
junction depth and optical absorption rate in the amorphous layer then reacted with diethyl-propylphosphonate and mesitylene as
are controlled by the He-PA conditions. Good abruptness of a solvent (25:1, v/v) at 120  C for 2.5 h to assemble a P-containing
1.5e2.4 nm/decade at Xj of around 10 nm and 750 U/, sheet
resistance are achieved by this method.
It is necessary to utilize conformal doping to form the extension
on the sidewalls of fins in advanced CMOS multi-gate device. Good
conformal projection could be achieved by plasma doping.
However, the process controllability and sputter erosion need to be
carefully addressed.
A self-regulatory plasma doping (SRPD) technique with B2H6/
Helium gas plasma has been developed that provide conformal
doping for fins and precisely controllable ultra-shallow doping for
planar FET [17]. As shown in Fig. 3, a zero degree angle of ion’s
incidence to the wafer surface from the plasma occurs with random
radicals.
Boron ion implantation, sputtering and boron radical adsorption
are simultaneously occurred at the top surface of fin while the
boron radical adsorption is the main process at the side surface. The
ion density is extremely low because of low pressure, consequently,
ion implantation and sputtering at the top surface is drastically
suppressed compared to conventional plasma doping process.
Therefore, conformal doping is achieved.
Recently, the combination of molecular monolayer doping
(phosphorus or boron atoms) and conventional spike annealing is Fig. 3. The schematic of the mechanism of the new conformal plasma doping method
developed for the formation of sub-5 nm ultra-shallow junctions [17].
 Y. Song et al. / Solid State Sciences 13 (2011) 294e305 297

Fig. 4. Process schematic for the wafer-scale monolayer doping approach [18].

monolayer for nþp junction, while allylboronic acid pinacol ester as lamp is suitable for heating Si as the heat sources, and the lumi-
a solvent (25:1, v/v) at 120  C for 2.5 h to enable a B-containing nescence spectra are white light.
monolayer for pþn junction. Then the substrate is capped with SiO2 Fig. 5 shows the schematic of the FLA apparatus. This apparatus
followed by spike anneal in Ar ambient to enable the formation of is composed of Xe flash lamps and W halogen lamps for assistant
ultra-shallow junction. The junction uniformity is determined by heating. The front of the substrate is heated by e Xe flash lamps and
the temperature homogeneity of the spike anneal tool. the back of the substrate is heated by W halogen lamps. The assist
This technology utilizes the crystalline nature and self-limiting heating temperature is set at 200e500  C using the W halogen
surface reaction properties of silicon to form self-assembled dopant lamps. After 30 s, the Xe flash lamps are used for irradiation with an
monolayers, combining with conventional spike annealing for the incident radiant energy density above 20 J/cm2. The temperature at
diffusion of dopants. The transient-enhanced diffusion effect is the Si surface reaches 1000  C or above due to the Xe flash lamp.
minimized and sub-5 nm depth of nþp and pþn junctions with low FLA is found to be an excellent technology for the activation of
sheet resistivity are demonstrated, even for fast diffusing dopants As, B, and In. The dopants activity using FLA is 4e5 times larger than
such as phosphorus. This surface-doping technology is not only that using RTA. Sub-15 nm ultra-shallow junction could be formed
useful for the nanoscale controlled doping for the contact extension by extremely high-rate ramp-up and ramp-down thermal process.
of planar MOSFETs, but also may be applicable for the conformal Flash annealing combined with solid phase epitaxial (SPE)
and deterministic doping of nonplanar nanoscale device structures, regrowth could further improve the activation of B at high
such as FinFETs or nanowire-FETs. temperature. The SPE is carried in nitrogen ambient anneals at
a furnace (450  C for 17 h) and a flash annealing tool for two step
2.2. Advanced annealing technologies annealing. An active concentration of 6.5  1020/cm3 which is well
above the electrical solubility limit of B is obtained [21].
Millisecond anneal (MSA), such as Flash-Lamp Annealing (FLA) The leakage in one step flash annealing SPE regrowth junction is
and Laser Spike Annealing (LSA) are considered to be the promising caused by the end-of-range (EOR) damage left beyond the amor-
candidates to substitute for spike rapid thermal annealing (RTA) as the phousecrystalline interface. A second Flash anneal at higher peak
source/drain dopant activation technology for sub-45 nm node [19]. temperatures anneals out the EOR defects while causing minimal
Flash-lamp annealing (FLA) technology which reduces the time diffusion and deactivation of B, consequently, results in nearly two
of the heating cycle to within the millisecond range is used to orders of magnitude reduction in leakage currents compared to
achieve abrupt profiles by strictly controlled diffusion of dopants a single Flash SPE [22].
[20]. The annealing time of FLA is 1e3 ms, about three orders of There are three major concerns related to flash-lamp annealing:
magnitude shorter than that of RTA. The dopant concentration can process controllability, source/drain activation, and silicidation [23].
exceed the maximum carrier concentration obtained by conven- Even though non-equilibrium process of FLA, thermal status will
tional RTA or furnace annealing. saturate after some dummy wafer processing, and it is possible to
The waver length in the Xe flash lamp is shorter than the create the stable condition at standby stage without wafer
wavelength at the absorption edge of Si. Therefore, the Xe flash proceeding. S/D activation with longer pulse FLA results in no
298 Y. Song et al. / Solid State Sciences 13 (2011) 294e305

Laser annealing, in which a laser melts a pre-amorphous surface

layer and causes the dopants to be distributed throughout the
region of melted silicon, is another promising candidate for the
formation of ultra-shallow junctions.
Higher laser fluence could increase the degree of activation,
however, results in deeper junction. Using multiple-pulse laser
annealing with moderate density of laser power can achieve
a defect-free pþ/n junction with a good degree of activation of
boron without compromising the junction depth [25].
The fabrication process starts with pre-amorphous implantation
of Siþ ions to n-type (100) silicon wafers, then Bþ ion implantation
is carried out, followed by an irradiation by a KrF excimer laser with
a wavelength of 248 nm. The laser pulses are produced at a repe-
tition frequency of 1 Hz and the pulse duration employed is 23 ns.
The laser fluence is carefully adjusted to melt amorphous silicon
layer but not monocrystalline silicon. The junction depth could be
easily controlled by varying the pre-amorphous layer depth.
The melt laser process may cause deformation of fine patterns
Fig. 5. Schematic of FLA apparatus [20]. by melting the gate stack and Si substrate under the isolating oxide.
Moreover, it seems complicated because it requires forming an
absorber layer and pre-amorphous implantation (PAI) prior to
dopants diffusion and small thermal stress annealing. Ge pre-
annealing to maintain the physical integrity.
amorphous step could enhance the flash spectra absorption, there-
A non-melt laser spike annealing which keeps the peak temper-
fore resulting in 2e3 times activation enhancement [24]. Also, FLA
ature below the Si melt temperature is developed to activate source/
has a capability to achieve very flat and thin NiSi layer for silicidation
drain junction [26]. Unlike the conventional laser annealing, no
process. Therefore, FLA has a large capability to be a standard
additional layers are formed and good heating uniformity is achieved,
annealing technology for future generation device manufacturing.
therefore, completely compatible with conventional CMOS process
There are also some significant challenges with flash-lamp
flow. The process suppresses the transient-enhanced diffusion and
annealing, for example, the mechanical stresses generated by
avoids dopants to reach the end of the damage range of the amor-
almost instantaneous heating of the wafer surface to very high
phous layer by keeping the junction profile inside the PAI region
temperatures. These stresses are considered to be the sources of
during the re-growth of the Si from amorphous/crystalline interface.
high levels of slip defects which resulting in high leakage currents.
The fabricated 50 nm device by this method shown in Fig. 6
Some of these stresses could be tempered through preheating the
demonstrates 10% IoffeIon improvement and no appreciable
wafer and controlling heat energy through flash pulse width
degradation of gate oxide integrity and junction leakage comparing
adjustment and pulse shaping. The pattern-related temperature
to control devices by conventional RTA.
non-uniformities are also severe issues due to insufficient heat
It is attracting to lower the annealing temperature and enlarge
diffusion.
the process window of laser spike annealing (LSA). A novel junction
profile engineering technique that uses LSA is implemented to
modulate the junction profile with lower temperatures and wider
process window [27]. Dramatic reduction of source-drain parasitic
resistance with low sensitivity to LSA temperature is achieved,
consequently, resulting in enhanced Ion.
Laser-only annealing has been integrated into high-k/metal gate
process to limit defect creation, reduce pre-doped poly-silicon resis-
tance, and obtain good capping/high-k intermixing due to low
thermal budget. Less oxide re-growth results in EOT reduction and less
work function roll off comparing with traditional spike annealing [5].
Low temperature MSA at source/drain activation is effective to
assist the activation of halo impurities with co-implant for nMOS, and
it is also effective for pMOS with elevated SiGe S/D [28] to avoid the
strain relaxation. Low temperature MSA and co-implant for nMOS
and tilt-and-twist extension implantation with MSA and co-implant
for pMOS are developed to improve device performance [29]. Fig. 7
shows the concept of tilt-and-twist extension ion implantation.
With this configuration, an overlapped shallow (A) and a highly
concentrated (B) (twice as high as (A)) extension profile are obtained
and high overlap controllability and reduction of parasitic resistance
could be achieved. High-performance 34 nm gate length bulk CMOS
transistors with drive currents of 1282 (nMOS)/835 (pMOS) mA/mm
and 100 nA/mm off-current at Vd ¼ 1 V are demonstrated.

3. Optional source/drain structures

Fig. 6. Cross-sectional TEM image of fabricated MOSFET: activated by LSA at 1.45 kW Optional source/drain structures provide other means to satisfy
(1300  C) in 80 ms [26]. the requirements for high-performance application. Raised source/
 Y. Song et al. / Solid State Sciences 13 (2011) 294e305 299

Fig. 8. Device structure of raised source/drain MOSFET [31].

Another problem with the conventional-order source/drain

formation is the difficulty to control xj,eff due to the sensitivity to
SEG process time [33].
To achieve such eS/D structure and precisely controlled xj,eff,
a reverse-order source/drain (ReS/D) with a self-limited SEG-Si
film which is stuffed into a narrow slit underneath a SiN sidewall is
developed to improve both the SCE and parasitic resistance [34].
Fig. 10 shows the schematic figures of conventional and reverse-
Fig. 7. Concept of tilt-and-twist extension ion implantation. (A) shallow and (B) high
order source/drain formations with both elevated source/drain
concentration extension profile can be achieved [29].
extension (eSDE) and eS/D. After STI formation and channel doping,
the gate insulator of SiON film is formed. After a notched gate
drain or metal Schottky barrier source/drain are promising candi- electrode formation, the offset liners and dummy sidewall were
dates that may provide with both low resistance and suppressed formed. Then, after an isotropic wet etching process of the liner
short channel effects simultaneously. film, the tunneling SEG-Si film with the thickness of only 4 nm is

3.1. Elevated source/drain

To aggressively suppress the short channel effect (SCE), it is

required to reduce an effective junction depth (xj,eff ), however, the
parasitic resistance increases. The elevated source/drain (eS/D)
technique as shown in Fig. 8 is one of the solutions to this problem.
Advanced multi-gate device such as FinFETs are in pressing need for
this technique because the narrow extension regions impose large
parasitic resistance [30].
Silicon selective-epitaxial growth (SEG) decreases overall para-
sitic resistance by providing more silicon for the source/drain sili-
cide formation. However, it complicates the CMOS integration
process as the deposition rate dependent on crystallographic
direction and doping. Moreover, it suffers from severe problem of
increased fringe capacitance.
A ultra-high vacuum-CVD technology accomplish with selective
epi-growth raised source/drain extension (RSD,ext) process is devel-
oped to reduce parasitic resistance and fringe capacitance simulta-
neously [32]. Elaborate facet-structure-control is explored. Selective
epi-growth only on S/D-extension crystalline surface while no
growth onto gate-poly sidewall is done by utilizing different incu-
bation times for poly-Si and mono-Si as shown in Fig. 9.
The advanced millisecond annealing with limited additional-
slight-diffusion is precisely controlled by pre-heat/post-heat
temperature TPRE. A relatively high TPRE is benefit for significant
reduction of the sheet resistance and junction leakage. Multi-ion-
species are applied for tailoring S/D profiles as slightly deeper in
depth direction while enhancing lateral-steepness. This careful
source/drain design enables further reducing halo-dose, reducing
junction leakage at the bottom region and increasing dopant Fig. 9. Cross-sectional TEM image after selective-epitaxial growth upon SDext. The
concentration near the NiSi interface that contributes to further on selective growth is done by utilizing different incubation times for poly-Si and mono-Si
current enhancements. [32].
300 Y. Song et al. / Solid State Sciences 13 (2011) 294e305

Fig. 10. Schematic figures of process flow for (a) conventional- and (b) reverse-order source/drain formations with both eSDE and eS/D [34].

achieved for the eSDE regions, in which a fringing capacitance another way to achieve both low parasitic resistance and low
could be almost negligible. Ion implantation is carried out to dope junction leakage.
the impurities into a simultaneously-formed 25-nm-thick SEG-Si Carbon cluster co-implantation enables to enhance SDE boron
film for the eS/D regions. After the removal of dummy sidewall film, concentration at the silicide interface and reduce deep halo dosage as
the SEG-Si films are doped by various ion-implantation doses. After well as junction leakage. Pre-amorphous of source/drain region by C
a final sidewall formation, a spike annealing is carried out with the or Ge implantation could control the extension doping depth profile
high temperature at 1050  C. Finally, interconnects are imple- and reduce Schottky barrier height between silicide and source/drain
mented after the NiSi formation. extension. The combination of these technologies achieves improved
The fabricated sub-10 nm CMOS devices show improved Ioff/CV/I Ion/Ioff characteristics for CMOS device with an aggressively reduced
characteristics due to the suppressions of both the short channel silicide position down to 5 nm from the gate edge [35].
effect and parasitic resistance. Elevated S/D could also be achieved by epitaxial growth SiGe
Accompanying Co-implantation and/or pre-amorphous of (for pmos) [36] or SiC (for nmos) [37] to induce compressive and
source/drain region with raised source/drain technology would be tensile stress respectively, for additional performance benefits.

Fig. 11. Schematic outline of a typical Schottky barrier pMOS transistor fabrication process [47].
 Y. Song et al. / Solid State Sciences 13 (2011) 294e305 301

SBMOS could provide high driving current as well as low

leakage current if the intrinsic Schottky barrier is sufficiently low.
Therefore, it is urgent to find proper metal with low Schottky
barrier for nMOS and pMOS respectively. So far, the most promising
material for nMOS includes ErSix [42e44], YbSi2-x [45] and DySix
[46] while PtSi [42] for pMOS.
The typical fabrication process for Schottky barrier MOSETs is
much simplified comparing with traditional pn junction S/D
MOSFETs [47]. Fig. 11 shows the schematic outline of a Schottky
Barrier pMOS fabrication process. After LOCOS isolation formation,
the lithography and etch of gate stack are performed. Then thin
oxide spacers and Pt-silicide with a low barrier (0.23 eV) for pMOS
source/drain junction are formed. No implantation is used in this
process. The fabricated pMOS device with gate length less than
Fig. 12. Process flow and XTEM image of NiSi SB nMOS featuring gate length of 39 nm 30 nm exhibits a cut off frequency of 280 GHz.
and ultra-thin gate oxide of 1.2 nm [49]. The manufactured 20 nm gate length Er/Pt silicide n/p type
SBMOS show enhanced short channel characteristics due to the low
Schottky Barrier (SB) between source and drain, giving very low
Low-field mobility enhancement of 140% is observed with the leakage current and high on current (550 mA/mm at Vg ¼ 3 V and
longitudinal compressive stress in the channel exceeding 1 GPa [38]. Vd ¼ 2 V) [33]. N2 annealing is beneficial for eliminating the
While 35% electron mobility improvement at tensile stress of interface traps in the erbium silicide thus improves subthreshold
615 MPa is observed for SiC S/D nmos [39]. The robust improvement characteristics. Er-silicide formation with W capping smoothes the
is explained by band repopulation and transverse mass modulation. ErSi2-x film without any pinhole or pyramidal defect and reduces
Besides local strain for enhanced mobility, this technique electron barrier height to 0.41 eV [48].
features superiorities such as high dopants activation and small YbSi2-x is even more suitable for N-SBMOS as it provides
barrier height for low-contact resistivity, low-temperature pro- a higher drive current and a lower leakage current (Ion/Ioff ratio ∼107
cessing for compatibility with high-k dielectrics and metal gate and Ss 75 mV/dec). This is attributed to lower electron barrier
electrodes, and abrupt Junctions for small overlap resistance. height (0.27 eV) and higher hole barrier height (0.82 eV) of the
YbSi2-x/Si Schottky contact and smooth YbSi2-x/Si interface [45].
3.2. Schottky barrier source/drain Using rare earth metal silicide materials with low SBH could
achieve an inherent improvement in transistor drive current.
As mentioned previously, serious challenges in the source/drain However, the rare earth metal is not suitable to implement into
are high leakage current, junction punch through, and high para- mass production due to its high price, and it also sophisticates the
sitic resistance/capacitance. Traditional pn junction source/drain CMOS integration due to the requirement of dual rare earth metal
have some inevitable deficiencies, such as complicated process, silicide formation. Mid-gate material such as NiSi [49] which has
large parasitic capacitors and tight compromises between thermal low resistivity, linewidth effect, Si consumption and temperature of
budgets and parasitic resistance [40]. Another critical problem with formation is more attracting to fulfill CMOS application as it makes
traditional p-n junction source/drain is the high activation the fabrication process less cost and simplified.
temperature which is not well compatible with metal gate/high-k NiSi is inappropriate for directly being as the source/drain sili-
integration, thus prohibits further scaling. cidation material due to large Schottky barrier between NiSi and
Schottky Barrier MOSFET (SBMOS) offers an alternative tech- both n and p substrate. Varies technologies are explored to reduce
nology in which the source and drain are formed using Schottky the effective SB barrier height, such as by introducing an interfacial
Barrier contacts, usually implemented with metal silicides, resulting layer of doping or a thin insulator between the metal S/D and the
in low parasitic resistance and high transconductance [41]. Mean- channel region.
while, Schottky barrier source/drain process features low annealing MOSFETs with fully NiSi source/drain contacts and ultra-short
temperature. It becomes promising solution as long as the thermal and defect-free source/drain extension (SDE) show that arsenic/
and phase stability issues are well solved. boron segregation during silicidation lead to strongly improved

Fig. 13. Id-Vg (a) and Id-Vd (b) characteristics of PSS CMOS with 39 nm gate length [49].
302 Y. Song et al. / Solid State Sciences 13 (2011) 294e305

Fig. 15. Band diagram illustrating the high-k dipole for (a) AlOx and (b) LaOx con-
taining diodes. Dipole at the high-k/SiO2 interface can tune the SBH more p-type (a) or
n-type (b) [62].
Fig. 14. (a) Process sequence for fabricating an N-FET with Sb segregated S/D regions
as well as a control N-FET. Cross-section schematic of (b) control N-FET and (c) N-FET
with Sb segregation in the nickel silicided S/D regions [61].
suppress the formation of active deep-level defects [54]. Therefore,
incorporating C into NiSi silicide could improve the morphological
device characteristics. This could be attributed to a strong and phase stability of NiSi:C contacts. Moreover, incorporating C in
conduction/valence band bending at the contact interface induced combination with B or As in Si could influence the effective SBH of
by a very thin, highly doped silicon layer formed during the silici- NiSi [55]. Carbon would inhibit B from diffusion and keep B
dation. The SB width between source/channel would be effectively assembling at interface which yield desired high values of 4bn
thinned out during on-state while the one between drain/channel (>0.9 eV) as long as the anneal temperature is above 600  C, while
would be broadened and elevated during off state, therefore, ach- C also increases As segregation at the silicide/Si interface which
ieve excellent on and off state. results in an effective tuning of 4bp above 1.0 eV.
The Schottky barrier modulation effects by dopants segregation An amazing conclusion is that an arbitrary kind of elements
could be explained by dipoles which generate at the mid-gap metal which are of no use as dopants in Si technology such as group II
silicide/silicon interface, through both first principles calculations elements may be promising candidates for modulating Schottky
and experimental methods [50]. barrier as long as it can generate a large dipole at the interface.
Ion implantation before (IBS for nMOS) [51] and after (IAS for Other elements are also feasible for modulating Schottky Barrier
nMOS and pMOS) [52] silicidation are two ways to modulate NiSi/Si by dopant segregation. Implantation of S or Se prior to silicidation
Schottky junction. Scheme IBS is relatively simple in processing, but (IBS) could also lead to effective reduction of contact resistance and
the silicidation process is dopant-dependent, while scheme IAS SB height (as low as 0.12e0.13 eV) at the NiSi/n-Si interface [56]. Se
addresses the adverse effects of dopants on silicidation by sepa- is more robust to withstand high temperature annealing than S to
rating silicidation from dopant incorporation [53]. restrict the outdiffusion.
In the IBS process which uses silicidation to induce dopant Incorporating Antimony (Sb) as the solid dopant segregation
segregation, most B atoms remain in the bulk NiSi layer after sili- source into Ni silicide on Si (100) is attractive to achieve low contact
cidation, while in the IAS process in which silicide used as the resistance by tuning Schottky barrier as low as 0.074 eV [57]. The
diffusion source, many B atoms migrate to the Si side resulting in fabrication flow of nickel silicide source/drain nMOS with Sb
a higher B concentration at the interface after a post-implantation incorporation is shown in Fig. 14. A thin solid Sb layer is deposited
drive-in anneal. Therefore, significant SBH changes occur in the IAS beneath a metallic nickel layer prior to source-drain silicidation.
process as B atoms replace Si atoms on the silicon side of the The very high concentration of Sb at the NiSi/Si interface reduces
interface, generating dipoles to comfort SBH. the effective SB height and parasitic series resistance, leading to
As atoms preferentially stay on the silicon side of the interface enhanced drive current performance without degradation in the
due to lower total energy, therefore, in both IAS and IBS processes, leakage current.
As atoms can migrate into the Si layer and pileup at the interface, Fluorine pre-silicidation implantation (IBS) is proved to be effec-
resulting in lager SBH modulation compared with the B doped case. tive to reduce leakage current and electron Schottky barrier of NiSi/Si
Fig. 12 shows the typical process flow and XTEM image of NiSi to 0.12 eV. More importantly, the lateral source/drain extension
SBNMOS by IBS dopants segregation. Fig. 13 shows the Id-Vg (a) and junction depth as well as SCE are reduced due to F segregation at the
Id-Vd (b) characteristics of SB process strained Si (PSS) CMOS with NiSi/Si interface [58,59]. Incorporation NiSi with metallic elements
39 nm gate length, indicating excellent performances are obtained. may also contribute to parasitic resistance reduction. It was found that
Carbon at the NiSi:C grain boundaries and NiSi:C/Si interface the NiAl-alloy silicide provides an effective Schottky Barrier height
could modify the grain-boundary and interfacial energies and lowering (250 meV) on n-Si(001) substrates [60].

Table 2
State of the art of Schottky barrier lowering by dopants segregation, the data are collected from the typical values reported recently.

Electron Hole
Element Al As In P S Se Sb F As & C B B&C
Schottky barrier (eV) 0.25 0.27 0.36 0.22 0.12 0.13 0.074 0.12 0.12 0.16 0.14
Ref [60] [62] [62] [62] [56] [56] [57] [59] [55] [62] [55]
 Y. Song et al. / Solid State Sciences 13 (2011) 294e305 303

Fig. 16. Schematics of (a) DSS-nFETs with N modulated NiSi2 and bulk NiSi. Inset shows the N diffusion barrier resulting in phase modulation of NiSi and (b) DSS-pFETs with
conventional NiSi [63].

Table 2 summaries the state of the art of modulating Schottky temperature RTA1 and a spike anneal RTA2 combining within suit
barrier between NiSi/Si by dopants segregation. As shown in Table chemical dry clean improves electrical properties and thermal
2, most researches focus on electron Schottky barrier for nmos. The stability of NiSi [68].
best result is obtained by Sb segregation (0.074 eV), indicating The activation energy for NiSi agglomeration is lower on single-
a promising application of Sb for SB nmos. C co-implantation with B crystal SOI than on annealed poly-Si, and agglomeration becomes
segregation benefits both from the reduction of Schottky barrier of severe when thickness of NiSi getting smaller. Pre-annealing the
NiSi/p-Si and the improvement of thermal stability. poly-Si would delay the agglomeration of the NiSi films. Indicating
An arbitrary kind of elements as long as it can generate a large that pre-amorphization of source/drain region may be a meaning-
dipole at the interface may be suitable for SB modulation as ful method for suppress NiSi from agglomeration.
mentioned previously. Therefore, the SB height modulation by using Various additive alloying elements are studied their effects on
single metal (TaN) and dual interfacial layer of SiO2/high-k (AlOx or formation and morphological stability of nickel monosilicide [69].
LaOx) dipoles resulting in SBH < 0.1 eV from the conduction band- Mo, Re, Ta and W are most efficient to retard NiSi agglomeration
edge (CBE) and SBH < 0.2 eV from the valence band-edge (VBE) has while Pd, Pt and Rh are most efficient to retard the formation of
been reported [62]. Fig. 15 illustrates the SBH dipole-tuning effects. NiSi2. Among them, Pt produces the most promising results that
AlOx and LaOx generate complementary dipole at the higk-k/ raise the silicidation temperature as high as 750  C [70]. Pt incor-
SiO2 interface that can be thought of as modulating the depletion poration not only improves thermal stability of NiSi but also ach-
region field or the metal work function. The band-edge SBH ieves low contact resistance (RC) at silicide/Si interface below
reduction with a minimal increase in process complexity enables 108Ucm2 [71]. For pMOS, Ni1-xPtxSi films enable RC reduction due
Cu metallization directly to the source/drain region. to the segregated Pt and B at silicide/Si interface. First principles
In addition, dual phase-modulated Ni silicide is effective for SB calculation indicates that RC reduction could also be explained by
and series resistance reduction in dopant segregated source/drain higher boron activation beyond solubility limit at silicide/Si inter-
(DSS) nMOS [63]. As shown in Fig. 16, selectively form interfacial face [72]. For nMOS, the gradual RC reduction could be explained by
epitaxial Si-rich NiSi2 by pre-silicide Nþ2 implant could reduce the the increased silicide granularity or Pt-As bond creation [73].
electron Schottky Barrier from 0.7 eV to 0.34 eV, while maintaining Thermal stability could also be improved by non-metal
a low resistive bulk NiSi at the same silicide formation temperature. elements incorporation such as high dose Ge ion implantation for
Devices using dual phase-modulated NiSi show enhanced thermal NiSi on poly-silicon [74] or silicon [75]. A very smooth NiSi/Si
stability and saturation gm as well as low series resistance. The interface with low interface energy is obtained due to Ge atom
process features low cost and CMOS compatibility, thus is prom- pileup at the NiSi/Si interface. A drawback of this method is the
ising for CMOS integration. slightly increased leakage due to Ni diffusion and dissolution
The DSS MOSFET suffers its bottle-neck of tunneling through the enhancement caused by Ge ion implantation induced extra defects.
SDE regions and band-to-band tunneling that limits the design space. Carbon ion implantation with high dose would also achieve good
The eS/D MOSFETs provide a considerable increase in contact area and thermal stability of NiSi as mentioned previously [76]. However,
allow one to use both high doping and low doping in different a balance between thermal stability and junction leakage is needed
portions of the S/D regions to reduce both the leakage flow and because the implanted C may result in crystal defects due to the low
specific contact resistivity. Therefore, the eS/D structure ends up solid-state solubility. Another drawback is the slightly increased
prevailing both in terms of leakage design space and on-state sheet resistance owing to the C segregation at the grain boundaries.
performance for meeting low-standby-power leakage specifications. Additional Pt on epi-Si:C source/drain could greatly enhances
For high performance (HP) design, the performances of optimized thermal stability of Ni(Pt)Si:C, thus raises the silicidation tempera-
DSS and eS/D MOSFETs are shown to be very similar [64]. Thus, the ture and achieves low sheet resistance of Ni-Pt/Si0.998C0.012 [77].
optimal source/drain design for HP is more likely to be decided by Recently, nickel nitride (NiNx) is found to be a possible substi-
practical considerations such as integration compatibility. tute for pure Ni to improve the thermal stability of NiSi [78]. The
As the linewidth and thickness of NiSi scales continuously, amorphous Si-N layer at the nickel nitride/Si interface retards Ni
thermal stability such as agglomeration and NiSi2 nucleation diffusion into the Si substrate, thus keeping the sustain tempera-
becomes a critical issue [65] among other challenges mentioned ture as high as 700  C.
previously. There exists a critical thickness (3.7 nm) below which
forms epitaxylike nickel-silicide layer on Si (100) with low resis- 4. Conclusions
tivity and good thermal stability [66]. However, such thin NiSi is not
applicable due to extremely large total resistance. Traditional two- Continuous scaling of CMOS device according to Moore’s law
step RTA encounters problems of excessive silicidation due to needs to boost on current, lower off current, suppress the short
oxygen contamination [67]. An optimized RTA scheme of a higher channel effects and increase the uniformity and reliability of device
304 Y. Song et al. / Solid State Sciences 13 (2011) 294e305

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