8085 Microprocessor
Introduction
● Microprocessor is a semi Cond vector component design by using VLSI
technology & it contains ALU, Cu & registers of a CPU in a single
package.
● For a microprocessor, Memory is connected externally
● The registers inside the processor can not be treated as memory as they
are used to hold the data temporary.
● Bit → Binary digit (0 or 1)
● Nibble → 4 - bits
● Byte → 8 bits
● Word length → depend on type of processor
History of Microprocessors
𝑠𝑡
● 1 microprocessor, 1971 → Intel 4004 → 4 bit
𝑛𝑑
● 2 microprocessor, 1972 → Intel 8008 → 8 bit
𝑟𝑑
● 3 microprocessor, 1974 → Intel 8080 → 8 bit
𝑡ℎ
● 4 microprocessor, 1977 → Intel 8085 → 8 bit
𝑡ℎ
● 5 microprocessor, 1978 → Intel 8086 → 16 bit
Note
Microprocessor Word length Memory capacity
Intel 4004 (PMOS) 4 - bit 640 B
Intel 8008 8 -bit 16 kB
Intel 8080 (NMOS) 8 -bit 64 KB
Intel 8085 (NMOS) 8 − 𝑏𝑖𝑡 64𝐾𝐵
Intel 8086 (HMOS) 16-bit 1 MB
Intel 8088 8/16-bit 1 MB
Intel 80186 16-bit 1 MB
Intel 80286 16-bit 16 MB real 44 B virtual
Intel 80386 32 − 𝑏𝑖𝑡 44 B real, 4 GB virtual
Intel 80486 32 − 𝑏𝑖𝑡 4 GB real 64 TB virtual
Pentium - Il 64 - bit 64 GB real
Z-80 8 -bit 64𝐾𝐵
Z-800 8-bit 500 KB
● Most of the general purpose Microprocessors used in the modern world
computers are the family of 8086 .
Difference between Microprocessors & Microcontroller
Microprocessor Microcontroller
It contains ALU, CU & resistors It contains ALU, CU & resistors
No internal memory It has interfacing circuit
No interfacing circuits i.e, timer /
Has interfacing circuit
counters
Used for general purpose Used for specific Purpose
Application EX: Intel Ex: Intel 8051, 8031 PIC - 8 bit/Is bit
8085, 8086, 𝑀6800, 𝑖3, 𝑖7 AT89C5
Micro-controller
Microprocessor Architecture
● Program & data are stored in a memory & it is responsible to operate
microprocessor
● Depending on how programmers & data are stored in the memory. They
are of two types of Architecture.
Von - Neumann or Princeton Architecture
Harvard Architecture
Program & data are separately present is different
Program & data both are present in same memory Program & Data Ex: Intel
8085, Intel 8086
Memory
Program
Memory
Data
Ex: Intel 8051 (MC)
Basic Operation
● Opcode fetch → Reading or accessing instruction i.e, opcode from
memory into the processor.
● Memory read → Reading or accessing data from memory
● Memory write → Sending or transferring data to memory
● I/O read → Reading or accessing data from input device or port Here, part
indicates connection of am I/O device.
● I/O write → Transferring data to output part or device.
Note:- The above 5 operations are called machine cycle or time processing
System Bus
● Bus is a group of conductor or wires used for communication between
processor, Memory & input output devices.
Three types of Bus →
(i) Address Bus
● It is used to transfer the address of either memory or input & output
devices from the processor.
● It defines the maximum memory that can be connected for as processor
given by the relation.
𝑛
Where, 2 = 𝑁
𝑛 = number of address line
𝑁 = number of address memory location.
● It is of 16 bit in length for 8085 microprocessor
● It is unidirectional.
(ii) Data Bus
● If is used to transfer data between processor, memory and I/O devices.
● It is of 8 bit in a length for 8085 .
● It is bidirectional.
● There is not separate date bus in 8085 . The Lower ' 8 ' address line can
be used either as address or data bus with the help of signal known as.
ALE (Address Latch Enable).
ALE
If all high : All i6 lines is Address bus
If one is zero or low:
𝐴15 − 𝐴8 is Address bus
𝐴𝐷7 − 𝐴𝐷0 is Date bus
𝐴15 − 𝐴8 𝐴𝐷7 − 𝐴𝐷0
ALE → 1: Higher order address bus Lower order Address bus
ALE → 0: Address bus Date bus
(iii) Control Bus
● It is a group of different control signals required for various operations of
the processor.
● It is partially unidirectional & partially bi - directional.
● ALE, 𝑅𝐷, 𝑊𝑅
Note:- If partially unidirectional & partially bi - directional is not given in the
options than prefer unidirectional.
Memory
● Memory is a group of register, a register is a group of flip-flap, a flip-flap is
a memory cell which can store a bit.
● Most of the memories are designed to store or hold 8 bits per each
registers or memory location or Address location.
● Memory is represented in terms of bits.
● Maximum memory that can be connected to 8085 is 64 KB
● Relationship between address line & memory-
𝑛
2 = 𝑁
Where,
𝑛 = number of address line 𝑁 = number of address or memory location.
Note - Address of the memory locations are not stored in memory. It stored in
processor.
● Memory has separate address line & separate data lines.
● Processor does not have separate address & reports data lines.
● The lower eight lines are multiplexed.
𝐿𝐴𝑇𝐶𝐻 →
● Latch is an interfacing component as the data is present on the bus for
very few microsounds.
● It is used to hold the value for some time such that output units like
display, Memory etc. can recognize the data. Ex :- 7415373
Representation of a Memory Chip
𝑚×𝑛
Where,
𝑀 = 𝑁𝑜 𝑜𝑓 𝑎𝑑𝑑𝑟𝑒𝑠𝑠 𝑜𝑟 𝑚𝑒𝑚𝑜𝑟𝑦 𝑙𝑜𝑐𝑎𝑡𝑖𝑜𝑛 𝑁 = 𝑛𝑜 𝑜𝑓 𝑏𝑖𝑡𝑠 𝑜𝑟 𝑙𝑜𝑐𝑎𝑡𝑖𝑜𝑛.
Internal Architecture
Register Unit
● There are two types of registers
1. General purpose registers - There are six 8 - bit general purpose register.
● They can also be used as 16 bit register i.e., register pair.
● They are three register pair namely - BC, DE, & HL
● Any of the register pair can be used to point to the memory but 'HL' pain
Ps known as default memory or data pointer.
● EX. MOV C, M
● Here, ' M ' indicates memory contained or resistor whose address is
present in HL pair only.
Accumulator (A)
1. Accumulator is a 8-bit multipurpose register by which almost all Arithmetic
& logic operational ore preferred.
The result of an operation is stored in the accumulator.
2. Special purpose registers- There are two 18-bits special purpose register
called program counter. (pc) & stock pointer (sp).
(i) Program Counter (PC) -
● It is a 16 - bit special purpose register used to sequence the execution of
programmer.
● The function of the program counter is to point to the memory address
from which the next byte is to be fetched.
● When the microprocessor is reset, the PC sets to Zero.
● Instruction register- It is a 8 - bit register which contain op - code of
present instruction. It does not contain data.
● After the op-code is fetched into Instruction register, it is forwarded into
decoder
● Op-code is decoded with the help of micro-program.
(ii) Stack Pointer (SP)-
● It is a 16-bit special purpose register which contains the address of data
present at top of the sock or it points to top of stock memory.
● Stock is a part of read, write memory which is used to store temporary
data & also the content of program counter when subroutines are used.
● Stock grows from bottom to top following LIFO (Last In First out) structure
& the SP contains keep decreasing as the stack grows.
● When data is stored or into stack memory stack pointer is decremented.
● When data is access from stack memory stack pointer is incremented.
● A single register data cannot be stored is stock memory.
Flag Register
● Flag register is a 8 - bit register.
● There are five Hag in 8085 which indicate the status after an Arithmetic &
logic operation.
● Hags are affected by the content of accumulator for most of the ALU
operation in some instructions they only also be modified for general
purpose registers.
● Flags are affected or modified only for operations.
● Example: Increment & Decrement.
Rules
● In signed operations;
𝑆 → 0; (+ )𝑣𝑒 result
𝑆 → 1; (− )𝑣𝑒 result
● If
𝑍 → 1; if result in ' A ' = 𝑂𝑂𝐻
𝑍 → 0; otherwise
● If 𝐴𝐶 → 1; If there is a carry from 𝐷4 bit ← 𝐷3 bit or Higher nibble ← lower
nibble 𝐴𝐶 → 𝑜; otherwise
● If 𝑃 → 1; if no of binary ' 1 ' in 𝐴 is even 𝑝 − 0; if no of binary ' 1 ' in 𝐴 is
odd.
● If 𝑐𝑦 → 1; if these is a carry i.e, out of 𝐷7 bit
𝑐𝑦 → 0; otherwise
Program status word (PSW)
● PSW is a combination of accumulator and Hag register together where
accumulator is high ' 𝐹 ' byte.
Temporary Register-
● The temporary registers W&Z are used to store data/address temporarily.
● They are two 8-bit temporary registers which are not accessible by the
user.
● This register is also called Invisible register because they are not available
for user during programmer.
Time & Control Unit
● It is responsible for generating various control timing & status signal
required for operating for the processor.
● Two pins ( 𝑥1, &𝑋2 ) a crystal oscillator (provide stable oscillation)
connected between these pins to provide reference fervency for the
processor.
● Crystal is used as it produces stable oscillations compared to RC & LC
oscillators, which are temperature dependent
𝑓𝑜𝑟𝑦𝑠𝑡𝑎𝑙
𝐹𝑐𝑙𝑘 = 2
●
𝑓𝑐𝑙𝑘 = 3𝑀𝐻3 (operating frequency)
Range = 3 to 6𝑀𝐻3
Address Latch Enable (ALE)
● ALE is used to make 𝐴𝐷7 − 𝐴𝐷0 either as a address or data bus.
● ALE 1 ; A11 16 lines → Address bus, 0; 𝐴15 − 𝐴8 Address bus,
𝐴𝐷7 − 𝐴𝐷0 → Data bus.
● 𝑅𝐷 = Read control signal
0 → Active
1 → Inactive
𝑊𝑅 = Write control signal
0 → Active
1 → Inactive
IO/M = status signal which indicates memory of I/O operation
𝐼𝑂/𝑀‾ = 0; memory operation, 1 ; IO operation
Control
10/𝑀 𝑅𝐷 𝐷𝑅 Operation
signal
Memory
0 0 1 M/M Read
Read
Memory
0 1 0 M/M write
write
1 0 1 I/OR I/O Read
1 1 0 I/ O W I/O write
𝑆 𝑆0 status line - There give the status of bus cycle for operation
1
𝐼𝑂/𝑀 S1 S2 States
𝑍 0 0 Halt
0 0 1 Memory write
0 1 0 Memory Read
0 1 1 Fetch
1 0 1 I/O write
1 1 0 I/O Read
1 1 1 INIA
𝑍 𝑋 𝑋 Hold
𝑍 𝑋 𝑋 Reset
Where, Z is High impedance state
HOLD
● This indicates if any other device is requesting the use of address & data
bus. Then microprocessor transfers the control to the requesting device as
soon as the current cycle is over.
● After the process of requesting deceive is over, the control is transferred
black to the microprocessor.
HLDA
● HLODA is the acknowledgement signal for HOLD.
● It indicates whether the HOLD signal is received or not.
● After The execution of HOLD request, HLDA goes low.
● Purpose of DMA → when more data is to be transferred between memory
& 1/0 at a faster rate, direct memory Access (DMA) operation is used with
the help of DMA controls.
● Modes of DMA →
1. Burst mode - Hold signal remain High unless until total data transfer.
During there period, the processor is present in WAIT/IDLE state. Therefore,
interference is more.
2. Cycle stealing technique / short burst mode-
The total data to be transferred is divided into blocks. Blocks are transferred in a
sequence of intervals of time.
The processor is interrupted only when true is a data transfer.
Interference is less.
EX: - Audio & file transfer application in a computer.
3. Inter leaved DMA → In both burst & cycle stealing techniques, the processor is
present in wait state.
Reset - in - Low active input signal to reset the processor & PC is initializing to
oooH
Reset - Out - Output signal which indicates that processor is reset. It can be used
to reset IO devices.
Clock - Out -Output pin on which the same operating frequency of the processor
is available It can be connected to clock input for a synchronous operation.
Ready - High Active input signal to the processor from a slow speed I/O If ready
is high, then only the processor will either transmit data to or receive data from
I/O device.
Interrupts of 8085
Interrupts is a method by which the I/O device informs the processor that it
requires the service of the processor.
Classification of Interrupts
● Hardware interrupts - 8085 has 5 hardware interrupts or external interrupts
Non-Vectored Interrupt
Software interrupts
● Their interrupts are available in the form of instruction.
● 8085 has 8 software interrupts.
Mask able Interrupts
Interrupts which can be ignored or avoided even if they are triggered are
mask-able.
Now - Mask able interrupts
Interrupts which cannot be ignored or avoided when triggered.
Note: - TRAP is the only non - mask-able interrupt in 8085 It must be connected
to highly prioritized events in practical applications.
Vectored interrupts
Interrupts which have specific address location in the memory are vectored.
Non - Vectored Interrupts
Interrupts which do not have specific address location in the memory are non -
vectored.
EX: - INTR is the only Non - vectored interrupt in 8085.
Note
Type of
Priority Interrupts Vector Address
triggering
Level & edge
1 TRAP 0024 H
triggering
Only edge
2 RST 7.5 003 CH
triggering
Only level
3 RST 6.5 0034 H
triggering
Only level
4 RST 5.5 002 CH
triggering
Only level
5 INTR -
triggering
Interrupt Service Routines (ISR)
● It is a program that is executed in response to an interrupt
● Every vectored Interrupt is assigned 8 bytes in a memory to store the
corresponding ISR.
● If the length of ISR is more than 8 bytes or when both Hardware &
software interrupts are required an unconditional jump instruction can be
used such that the program may be continued fretter.
TRAP -
● TRAP is both edge & level triggered.
● It may respond quickly.
● It differentiate original signal from practical application & error signal due
to noise.
INTER - 𝐼𝑁𝑇𝑅
● 𝐼𝑁𝑇𝑅 Generates the pulse only to recognize the INTR interrupt.
● 𝐼𝑁𝑇𝑅 is required only for INTR not for vectored interrupt.
● In order to use INTR, the programmer most select one of the software
interrupt address to store ISR of I/O device.
Instructions Related to Interrupt -
● El (Enable interrupt) - Used to enable Mask able interrupt
● DI (Disable interrupt) - Used to disable mask able interrupt
● SIM (Set Interrupt mask) - Use to mask the interrupts or make then
available.
RIM (Read Interrupt Mask) - Used to know the states of pending Interrupts.
NOTE: the above instruction are valid only for mask able interrupts. TRAP cannot
be Enable or disable.
PROGRAMMING MODEL
● Program is a set of instruction.
● Instruction is command given to computer to perform specific task.
● Machine level language is a binary medium of communication with a
computer through a design set of instructions.
● Assembly level language in which instructions are written in separate
words known as ‘Mnemonics’
● Both Assembly & Machine level languages are together known as Two -
level language which are machine dependent.
● Overall cycle of writing the program till execution.
● Op - code fetch, Decode & Execute are the basic steps of execution of an
Instruction.
● Monitor program is similar to operating system software. It is used in
microprocessor based system.
Instruction Format
Op - code Operands
Where,
● Op - code indicates the type of operation to be performed for an
instruction.
● Operand is data on which operation is to be performed.
Length of an Instruction
● Number of bytes occupied by the instruction in the memory
● Three are three types of instruction classified according to length.
(i) 1 - Byte instruction :
Ex:
● Mov-Op-code
● A, C - Operands
(ii) 2 - Byte instruction :
Ex.
● MVI B, 77H
(iii) 3 - Byte instruction :
Ex:
● LXI H - Opcode (1 Byte)
● 9080 H - Operands (2 - Byte)
Memory Rule
● In all memory related operations, the data present in lower byte of register
is transferred to the lower address location.
● Higher byte or higher register content is transferred to higher address
location or vice - versa.
Standard Codes
𝐵 → 000
𝐶 → 001
𝐷 → 010
𝐸 → 011
𝐻 → 100
● L → 101
𝐴 → 111
Memory (M) → 10
𝐵𝐶 → 00
● DE → 01
𝐻𝐿 → 10
𝑆𝑃 → 11
Addressing Modes
These are various formats specify the operands or they indicate how data is
accessed for instructions. There are five type of Addressing mode.
i. Immediate Addressing mode - Data is present in the instruction itself.
ii. Direct Adorning mode - Address of the data is present in the instruction.
iii. Indirect Addressing mode - Address of the data is present as the content of
another register pair.
iv. Register addressing mode - Data is transferred between registers.
v. Implicit / Implied addressing mode - No operand or data is preset in an
instruction but some kind of operation is performed by the instruction.
Timing diagram →
● Timing diagram is pictorial representation of execution of an instruction
with the help of various timing control and status signal.
● T-state is one sub - division of an operation performed in 1 clock period.
● Machine cycle - It is defined as the time required to access either memory
& I/O.
● 1 Machine cycle may have 3-6T-State.
● Instruction cycle - It is defined as the time required to complete the
execution of an instruction. one instruction cycle may have one to five
Machine cycles.
Note :- The maximum 𝑇 - state possible for execution of an instruction in 8085 is
18
● Steps of execution is (i) Fetch (ii) Decode (iii) Execute
Diagram
Instruction Set Classification
Type of operation Length of instruction
(i) Data transfer (copy) instruction (i) 1 Byte instruction
(ii) Arithmetic instruction (ii) 2 Byte instruction
(iii) Logical instruction (iii) 3 Byte instruction
(iv) Branching instruction
(v) Machine Control instruction
Data transfer or copy instruction
● In this group, the data is transferred from one location i. e., Source to
another location i.e destination.
● It may be between -
a. Register to register
b. Register to Memory
c. Register to I/O
d. Register to data
Terminology used in data transfer instructions -
𝑀 → Move
I → Immediate
𝑅𝑃 → Register pair
𝑋 → Operation on 𝑅𝑃
[ ] → Content of
[[ ]] → Reference or content
𝐿 → Load
𝑠 = Store
IN 8 bit port address, [A] data I/P device (I/O Read)
Out 8 bit port address, [A] O/P device
[ ]
Push 𝑅𝑝 : 𝑅𝑝 Stack Memory
POP 𝑅𝑝: [𝑅𝑝] data from stack
Syntax Operation
MVI r, data B 𝑟 <= data 8
𝐿 × 𝐼𝑟𝑝, NUM 16 (𝑟𝑝) < NUM 16
MVP M, data 8 ((𝐻𝐿)) <= data 8
MOV rd 𝑟𝑠 (𝑟𝑑) <= (𝑟𝑠)
SPHL (𝑆𝑃) <= (𝐻𝐿
PCHL (𝑃𝐶) <= (𝐻𝐿)
XCHG (DE) <=> (𝐻𝐿)
OUT Add 8 (Add 8) <= (𝐴)
IN Add 8 (A) < = (Add 8)
MOV M,r ((𝐻𝐿)) <= (𝑟)
MOV r,M (𝑟) <= ((𝐻𝐿))
STAX 𝑟𝑝 ((𝑟𝑝)) <= (𝐴)
LDAX 𝑟𝑝 (A) <= ((𝑟𝑝))
LDA Add 16 (A) (Add 16)
STA Add 16 (Add 16) < = (A)
( 𝐴𝑑𝑑 16) <= (𝐿) ( 𝐴𝑑𝑑 16 + 1) <= (𝐻
SHLD Add 16
2 memory write operation.
(𝐿) = ( 𝐴𝑑𝑑 16) (𝐻) = ( 𝐴𝑑𝑑 16 + 1)
LHLD Add 16
2 Memory Read operation
PUSH 𝑟𝑝
( )
((𝑠𝑝) − 1) = 𝑟𝐻 ((𝑠𝑝) − 2) = 𝑟𝐿 ( )
(SP) decremented by 2
(𝑟𝐿) = ((𝑠𝑝)) (𝑟𝐻) = ((𝑠𝑝) + 1)
POP 𝑟𝑝 (𝑠𝑝)
incremented by 2
(𝑇𝑜𝑠) <=> (𝐻𝐿) 𝑇𝑜𝑠 = 𝑇𝑜𝑝 𝑜𝑓 𝑡ℎ𝑒 𝑠
𝑠𝑝
XTHL
is unchanged after execution PoPh
followed by PUSH H
Remember:-
● In almost all data transfer operation the contain of source is unchanged
after the execution
● Flags are not affected for execution of data transfer group of instruction,
since ALU is not involved.
Arithmetic instruction:
● There is no multiplexer or division operation is supported by 8085
● 8085 microprocessor has accumulator based ALU
(a) Addition; ADD C
(b) Subtraction; SVB M
(c) Increment; INX H
(d) Decrement; DCR M
Syntax Operation
Add r (𝐴) = (𝐴) + (𝑟)
DAA Decimal adjust after addition
DAD 𝑟𝑝 ( )
(𝐻𝐿) + 𝑟𝑝 = (𝐻𝐿)
ADC r (𝐴) = (𝐴) + (𝑟) + (𝐶𝑌)
ADD M (𝐴) <= (𝐴) + ((𝐻𝐿))
ADC M (𝐴) <= (𝐴) + ((𝐶𝐻𝐿)) + (𝐶𝑌)
ADI data 8 (𝐴) <= (𝐴) + data 8
ACI data 8 (𝐴) <= (𝐴) + data 8 + (𝑐𝑦)
SUB r (𝐴) <= (𝐴) − (𝑟)
SUB r (𝐴) <= (𝐴) − (𝑟) − (𝑐𝑦)
SUB M (𝐴) <= (𝐴) − ((𝐻𝐿))
SUB M (𝐴) <= (𝐴) − ((𝐻𝐿)) − (cy)
SUI data 8 (𝐴) <= (𝐴) - data 8
SBI data 8 (𝐴) <= (𝐴) − data − (𝐶𝑌)
INR r (𝑟) <= (𝑟) + 1
INX 𝑟𝑝 (𝑟𝑝) <= (𝑟𝑝) + 1
INR M (𝑀) <= ((𝐻𝐿)) + 1
DCR r (𝑟) <= (𝑟) − 1
DCR 𝑟𝑝 (𝑟𝑝) <= (𝑟𝑝) − 1
DCR M (𝑀) <= ((𝐻𝐿)) − 1
Note:
● DAD instruction is a special instruction for performing 16 bit addition
● Microprocessor uses 2's compliment technique for subtraction operation
● After subtraction operation carry flag is to be complemented
● If 𝐶𝑌 = 1 then result in accumulator is positive
● If 𝐶𝑌 = 0 then result in accumulator is negative
● INR & DCR instruction effects all flags except CY flag
● For DAD Accumulator is unchanged after the operation IF there is carry
out of 16 − 6π carry flag is affected remaining flags are unchanged.
Logical Instruction:
Syntax Operation
AND accumulator with 𝑟
ANA r
(𝐴) <= (𝐴) ∧ (𝑟)
ANA M (𝐴) <= (𝐴) ∧ ((𝐻𝐿) )
ANI data 8 (𝐴) <= (𝐴) ∧ data 8
ORA r (A) <= (𝐴) ∨ (𝑟)
ORA M (𝐴) <= (𝐴) ∨ ((𝐻𝐿) )
ORI data 8 (𝐴) <= (𝐴) ∨ data
XRA r (𝐴) <= (𝐴) ∨ (𝑟)
XRA M (𝐴) <= (𝐴) ∨ ((𝐻𝐿) )
XRA data 8 (A) <= (A) ∨ data 8
CMP r (A) - (r)
CMP M (A) - ((HL))
CPI data 8 (A) - data 8
CMA Complement contents of accumulator
CMC 𝐶𝑌 <= 𝐶𝑌
STC 𝐶𝑌 <= 1
RLC Rotate accumulator left
RAL Rotate accumulator left through carry
RRC Rotate accumulator right
Rotate accumulator right through
RAR
carry.
Note:
● For CMP M operation result are not stored in ' 𝑀 ' it differs from SUB
instruction. Ned to check status from flags.
● CMA instruction is used for 1's compliment performing.
● Rotate operations include only change of carry flag. No other flags are
affected using rotate operation.
● For any AND operation; 𝐴𝐶 = 1&𝐶𝑌 = 0
● For any 𝑂𝑅 operation; 𝐴𝐶 = 0&𝐶𝑌 = 0
𝑍 𝐶𝑌 (𝐴) − (𝐵) Result
1 0 Zero (𝐴) = (𝐵)
0 0 Positive (𝐴) > (𝐵)
0 1 Negative (𝐴) < (𝐵)
● Sign flag depends on the subtraction of (𝐴) − (𝐵)
Rotate:-
● Only possible with ' A ' content
● Only 'CY' is affected
RLC: - Rotate the content of Accumulator one bit left without carry.
RAL: - Rotate the content of Accumulator one bit left with carry
RRC: - Rotate the content of Accumulator one right without carry
RAR: - Rotate the content of accumulator one right with carry
Application:
● They are used to find (+) ve and (-) ve, even & odd number, multiplication
& division & also for serial communication
Branching Instruction:
● In this group, the control of program is transferred from one location to
another conditionally or unconditionally
Conditional Instruction:
● They depend on status of flags effected for previous ALU operation
(except Auxiliary) carry flag (AC)
True condition:
● Control of the program is transferred to 16 bit address & execution
continues.
False condition:
● Control of the program is transferred to very next instructions
Unconditional instructions:
● Control of the program is transferred to 16 bit address unconditional. E.g.
Jump, call, Return.
Jump instruction:
● They are used to transfer the control of program from one location to
another conditionally or unconditionally.
Conditional Jump Instruction:
● True condition: Three machine cycle i.e IOT states are required
● False condition: Two machine cycle i.e 7 T-state are required.
Note: - (For only false) = one machine cycle is wasted even the condition is false.
● There are 9 Jump instruction (8-conditional & 1 -unconditional) and each
instruction require 3 - machine cycle Hence, total machine cycle required
to execute all 9 − jump instruction = 9 × 3 = 27 machine cycles.
● If the content of register ' c ' is ' 𝑛 ' the load executes for 𝑛-times where the
condition is true for ( 𝑛 − 1 ) times & false only once.
● If ' 𝑐 ' has ' 𝐹𝐹 ' the loop runs for 255 times
● IF ' 𝑐 ' has 'oo' the loop runs for 256 times
● The length of the program is 7 bytes.
Total execution time ( T )
𝑇 = 𝑇𝑂𝐿 + 𝑇𝑊𝐿
●
where,
𝑇𝑜𝐿 = 𝑡𝑖𝑚𝑒 𝑓𝑜𝑟 𝑖𝑛𝑠𝑡𝑟𝑢𝑐𝑡𝑖𝑜𝑛 𝑜𝑢𝑡 𝑜𝑓 𝑙𝑜𝑜𝑝
𝑇𝑤𝐿 = time for instruction within the loop
1
𝑇𝑜𝐿 = 𝐹𝑐𝑙𝑘
× (𝑇 − state ) × ( count value )
