Basic Computer Organization & Design 1

BASIC COMPUTER ORGANIZATION AND DESIGN

Instruction Codes

Computer Registers

Computer Instructions

Timing and Control

Instruction Cycle

Memory Reference Instructions

Input-Output and Interrupt

Complete Computer Description

Design of Basic Computer

Design of Accumulator Logic

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INTRODUCTION
Every different processor type has its own design (different
registers, buses, microoperations, machine instructions, etc)
Modern processor is a very complex device
It contains
Many registers
Multiple arithmetic units, for both integer and floating point calculations
The ability to pipeline several consecutive instructions to speed execution
Etc.
However, to understand how processors work, we will start with
a simplified processor model
This is similar to what real processors were like ~25 years ago
M. Morris Mano introduces a simple processor model he calls
the Basic Computer
We will use this to introduce processor organization and the
relationship of the RTL model to the higher level computer
processor

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THE BASIC COMPUTER

The Basic Computer has two components, a processor and

memory
The memory has 4096 words in it
4096 = 212, so it takes 12 bits to select a word in memory
Each word is 16 bits long

CPU RAM
0

15 0

4095

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INSTRUCTIONS

Program
A sequence of (machine) instructions
(Machine) Instruction
A group of bits that tell the computer to perform a specific operation
(a sequence of micro-operation)
The instructions of a program, along with any needed data
are stored in memory
The CPU reads the next instruction from memory
It is placed in an Instruction Register (IR)
Control circuitry in control unit then translates the
instruction into the sequence of microoperations
necessary to implement it

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INSTRUCTION FORMAT
A computer instruction is often divided into two parts
An opcode (Operation Code) that specifies the operation for that
instruction
An address that specifies the registers and/or locations in memory to
use for that operation
In the Basic Computer, since the memory contains 4096 (=
212) words, we needs 12 bit to specify which memory
address this instruction will use
In the Basic Computer, bit 15 of the instruction specifies
the addressing mode (0: direct addressing, 1: indirect
addressing)
Since the memory words, and hence the instructions, are
16 bits long, that leaves 3 bits for the instructions opcode

Instruction Format
15 14 12 11 0
I Opcode Address

Addressing
mode

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ADDRESSING MODES
The address field of an instruction can represent either
Direct address: the address in memory of the data to use (the address of the
operand), or
Indirect address: the address in memory of the address in memory of the data
to use
Direct addressing Indirect addressing

22 0 ADD 457 35 1 ADD 300

300 1350

457 Operand
1350 Operand

+ +
AC AC

Effective Address (EA)

The address, that can be directly used without modification to access an
operand for a computation-type instruction, or as the target address for a
branch-type instruction
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PROCESSOR REGISTERS
A processor has many registers to hold instructions,
addresses, data, etc
The processor has a register, the Program Counter (PC) that
holds the memory address of the next instruction to get
Since the memory in the Basic Computer only has 4096 locations, the PC
only needs 12 bits
In a direct or indirect addressing, the processor needs to keep
track of what locations in memory it is addressing: The
Address Register (AR) is used for this
The AR is a 12 bit register in the Basic Computer
When an operand is found, using either direct or indirect
addressing, it is placed in the Data Register (DR). The
processor then uses this value as data for its operation
The Basic Computer has a single general purpose register
the Accumulator (AC)

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PROCESSOR REGISTERS
The significance of a general purpose register is that it can be
referred to in instructions
e.g. load AC with the contents of a specific memory location; store the
contents of AC into a specified memory location
Often a processor will need a scratch register to store
intermediate results or other temporary data; in the Basic
Computer this is the Temporary Register (TR)
The Basic Computer uses a very simple model of input/output
(I/O) operations
Input devices are considered to send 8 bits of character data to the processor
The processor can send 8 bits of character data to output devices
The Input Register (INPR) holds an 8 bit character gotten from an
input device
The Output Register (OUTR) holds an 8 bit character to be send
to an output device

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Basic Computer Organization & Design 9 Registers

BASIC COMPUTER REGISTERS

Registers in the Basic Computer

11 0
PC
Memory
11 0
4096 x 16
AR
15 0
IR CPU
15 0 15 0
TR DR
7 0 7 0 15 0
OUTR INPR AC

List of BC Registers
DR 16 Data Register Holds memory operand
AR 12 Address Register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction Register Holds instruction code
PC 12 Program Counter Holds address of instruction
TR 16 Temporary Register Holds temporary data
INPR 8 Input Register Holds input character
OUTR 8 Output Register Holds output character
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COMMON BUS SYSTEM

The registers in the Basic Computer are connected using a

bus
This gives a savings in circuitry over complete
connections between registers

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COMMON BUS SYSTEM

S2
S1 Bus
S0
Memory unit 7
4096 x 16
Address
Write Read
AR 1

LD INR CLR
PC 2

LD INR CLR

DR 3

LD INR CLR
E
ALU AC 4

LD INR CLR

INPR
IR 5
LD
TR 6
LD INR CLR
OUTR
Clock
LD
16-bit common bus

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COMMON BUS SYSTEM

Read
INPR
Memory Write
4096 x 16
Address E ALU

AC

L I C

L I C L

L I C DR IR L I C

PC TR

AR OUTR LD

L I C

7 1 2 3 4 5 6

16-bit Common Bus

S0 S1 S2

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COMMON BUS SYSTEM

Three control lines, S2, S1, and S0 control which register the
bus selects as its input
S2 S1 S0 Register
0 0 0 x
0 0 1 AR
0 1 0 PC
0 1 1 DR
1 0 0 AC
1 0 1 IR
1 1 0 TR
1 1 1 Memory

Either one of the registers will have its load signal

activated, or the memory will have its read signal activated
Will determine where the data from the bus gets loaded
The 12-bit registers, AR and PC, have 0s loaded onto the
bus in the high order 4 bit positions
When the 8-bit register OUTR is loaded from the bus, the
data comes from the low order 8 bits on the bus

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Basic Computer Organization & Design 14 Instructions

BASIC COMPUTER INSTRUCTIONS

Basic Computer Instruction Format

Memory-Reference Instructions (OP-code = 000 ~ 110)

15 14 12 11 0
I Opcode Address

Register-Reference Instructions (OP-code = 111, I = 0)

15 12 11 0
0 1 1 1 Register operation

Input-Output Instructions (OP-code =111, I = 1)

15 12 11 0
1 1 1 1 I/O operation

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BASIC COMPUTER INSTRUCTIONS

Hex Code
Symbol I=0 I=1 Description
AND 0xxx 8xxx AND memory word to AC
ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load AC from memory
STA 3xxx Bxxx Store content of AC into memory
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and save return address
ISZ 6xxx Exxx Increment and skip if zero

CLA 7800 Clear AC

CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instr. if AC is positive
SNA 7008 Skip next instr. if AC is negative
SZA 7004 Skip next instr. if AC is zero
SZE 7002 Skip next instr. if E is zero
HLT 7001 Halt computer

INP F800 Input character to AC

OUT F400 Output character from AC
SKI F200 Skip on input flag
SKO F100 Skip on output flag
ION F080 Interrupt on
IOF F040 Interrupt off

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INSTRUCTION SET COMPLETENESS

A computer should have a set of instructions so that the user can
construct machine language programs to evaluate any function
that is known to be computable.

Instruction Types
Functional Instructions
- Arithmetic, logic, and shift instructions
- ADD, CMA, INC, CIR, CIL, AND, CLA
Transfer Instructions
- Data transfers between the main memory
and the processor registers
- LDA, STA
Control Instructions
- Program sequencing and control
- BUN, BSA, ISZ
Input/Output Instructions
- Input and output
- INP, OUT

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CONTROL UNIT

Control unit (CU) of a processor translates from machine

instructions to the control signals for the microoperations
that implement them

Control units are implemented in one of two ways

Hardwired Control
CU is made up of sequential and combinational circuits to generate the
control signals
Microprogrammed Control
A control memory on the processor contains microprograms that
activate the necessary control signals

We will consider a hardwired implementation of the control

unit for the Basic Computer

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Basic Computer Organization & Design 18 Timing and control

TIMING AND CONTROL

Control unit of Basic Computer

Instruction register (IR)

15 14 13 12 11 - 0 Other inputs

3x8
decoder
7 6543 210
D0
I Combinational
D7 Control Control
logic signals

T15
T0

15 14 . . . . 2 1 0
4 x 16
decoder

4-bit Increment (INR)

sequence Clear (CLR)
counter
(SC) Clock

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TIMING SIGNALS
- Generated by 4-bit sequence counter and 416 decoder
- The SC can be incremented or cleared.

- Example: T0, T1, T2, T3, T4, T0, T1, . . .

Assume: At time T4, SC is cleared to 0 if decoder output D3 is active.
D3T4: SC
T0 0 T1 T2 T3 T4 T0
Clock

T0

T1

T2

T3

T4

D3

CLR
SC

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INSTRUCTION CYCLE

In Basic Computer, a machine instruction is executed in the

following cycle:
1. Fetch an instruction from memory
2. Decode the instruction
3. Read the effective address from memory if the instruction has an
indirect address
4. Execute the instruction

After an instruction is executed, the cycle starts again at

step 1, for the next instruction

Note: Every different processor has its own (different)

instruction cycle

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FETCH and DECODE

Fetch and Decode T0: AR PC (S0S1S2=010, T0=1)
T1: IR M [AR], PC PC + 1 (S0S1S2=111, T1=1)
T2: D0, . . . , D7 Decode IR(12-14), AR IR(0-11), I IR(15)

T1 S2

T0 S1 Bus

S0
Memory
7
unit
Address
Read

AR 1

LD
PC 2

INR

IR 5

LD Clock
Common bus

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DETERMINE THE TYPE OF INSTRUCTION

Start
SC 0

T0
AR PC
T1
IR M[AR], PC PC + 1
T2
Decode Opcode in IR(12-14),
AR IR(0-11), I IR(15)

(Register or I/O) = 1 = 0 (Memory-reference)

D7

(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)

I I

T3 T3 T3 T3
Execute Execute AR M[AR] Nothing
input-output register-reference
instruction instruction
SC 0 SC 0 Execute T4
memory-reference
instruction
SC 0

D'7IT3: AR M[AR]
D'7I'T3: Nothing
D7I'T3: Execute a register-reference instr.
D7IT3: Execute an input-output instr.
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REGISTER REFERENCE INSTRUCTIONS

Register Reference Instructions are identified when
- D7 = 1, I = 0
- Register Ref. Instr. is specified in b0 ~ b11 of IR
- Execution starts with timing signal T3

r = D7 IT3 => Register Reference Instruction

Bi = IR(i) , i=0,1,2,...,11
r: SC 0
CLA rB11: AC 0
CLE rB10: E0
CMA rB9: AC AC
CME rB8: E E
CIR rB7: AC shr AC, AC(15) E, E AC(0)
CIL rB6: AC shl AC, AC(0) E, E AC(15)
INC rB5: AC AC + 1
SPA rB4: if (AC(15) = 0) then (PC PC+1)
SNA rB3: if (AC(15) = 1) then (PC PC+1)
SZA rB2: if (AC = 0) then (PC PC+1)
SZE rB1: if (E = 0) then (PC PC+1)
HLT rB0: S 0 (S is a start-stop flip-flop)

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Basic Computer Organization & Design 24 MR Instructions

MEMORY REFERENCE INSTRUCTIONS

Operation
Symbol Symbolic Description
Decoder
AND D0 AC AC M[AR]
ADD D1 AC AC + M[AR], E Cout
LDA D2 AC M[AR]
STA D3 M[AR] AC
BUN D4 PC AR
BSA D5 M[AR] PC, PC AR + 1
ISZ D6 M[AR] M[AR] + 1, if M[AR] + 1 = 0 then PC PC+1

- The effective address of the instruction is in AR and was placed there during
timing signal T2 when I = 0, or during timing signal T3 when I = 1
- Memory cycle is assumed to be short enough to complete in a CPU cycle
- The execution of MR instruction starts with T4
AND to AC
D0T4: DR M[AR] Read operand
D0T5: AC AC DR, SC 0 AND with AC
ADD to AC
D1T4: DR M[AR] Read operand
D1T5: AC AC + DR, E Cout, SC 0 Add to AC and store carry in E

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MEMORY REFERENCE INSTRUCTIONS

LDA: Load to AC
D2T4: DR M[AR]
D2T5: AC DR, SC 0
STA: Store AC
D3T4: M[AR] AC, SC 0
BUN: Branch Unconditionally
D4T4: PC AR, SC 0
BSA: Branch and Save Return Address
M[AR] PC, PC AR + 1
Memory, PC, AR at time T4 Memory, PC after execution
20 0 BSA 135 20 0 BSA 135
PC = 21 Next instruction 21 Next instruction

AR = 135 135 21
136 Subroutine PC = 136 Subroutine

1 BUN 135 1 BUN 135

Memory Memory
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MEMORY REFERENCE INSTRUCTIONS

BSA:
D5T4: M[AR] PC, AR AR + 1
D5T5: PC AR, SC 0

ISZ: Increment and Skip-if-Zero

D6T4: DR M[AR]
D6T5: DR DR + 1
D6T4: M[AR] DR, if (DR = 0) then (PC PC + 1), SC 0

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FLOWCHART FOR MEMORY REFERENCE INSTRUCTIONS

Memory-reference instruction

AND ADD LDA STA

D0 T 4 D1 T 4 D2 T 4 D 3T 4
DR M[AR] DR M[AR] DR M[AR] M[AR] AC
SC 0

D0 T 5 D1 T 5 D2 T 5
AC AC DR AC AC + DR AC DR
SC 0 E Cout SC 0
SC 0

BUN BSA ISZ

D4 T 4 D5 T 4 D6 T 4
PC AR M[AR] PC DR M[AR]
SC 0 AR AR + 1

D5 T 5 D6 T 5

PC AR DR DR + 1
SC 0
D6 T 6
M[AR] DR
If (DR = 0)
then (PC PC + 1)
SC 0

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Basic Computer Organization & Design 28 I/O and Interrupt

INPUT-OUTPUT AND INTERRUPT

A Terminal with a keyboard and a Printer
Input-Output Configuration
Input-output Serial Computer
terminal communication registers and
interface
flip-flops
Receiver
Printer interface OUTR FGO

AC

Transmitter
Keyboard interface INPR FGI
INPR Input register - 8 bits
OUTR Output register - 8 bits Serial Communications Path
FGI Input flag - 1 bit Parallel Communications Path
FGO Output flag - 1 bit
IEN Interrupt enable - 1 bit

- The terminal sends and receives serial information

- The serial info. from the keyboard is shifted into INPR
- The serial info. for the printer is stored in the OUTR
- INPR and OUTR communicate with the terminal
serially and with the AC in parallel.
- The flags are needed to synchronize the timing
difference between I/O device and the computer
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Basic Computer Organization & Design 29 I/O and Interrupt

PROGRAM CONTROLLED DATA TRANSFER

-- CPU -- -- I/O Device --
/* Input */ /* Initially FGI = 0 */ loop: If FGI = 1 goto loop
loop: If FGI = 0 goto loop
INPR new data, FGI 1
AC INPR, FGI 0

/* Output */ /* Initially FGO = 1 */ loop: If FGO = 1 goto loop

loop: If FGO = 0 goto loop consume OUTR, FGO 1
OUTR AC, FGO 0

FGI=0 FGO=1
Start Input Start Output

FGI 0
AC Data
yes yes
FGI=0
FGO=0
no
no
AC INPR
OUTR AC

yes More FGO 0

Character
yes More
no Character
END no
END
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INPUT-OUTPUT INSTRUCTIONS

D7IT3 = p
IR(i) = Bi, i = 6, , 11

p: SC 0 Clear SC
INP pB11: AC(0-7) INPR, FGI 0 Input char. to AC
OUT pB10: OUTR AC(0-7), FGO 0 Output char. from AC
SKI pB9: if(FGI = 1) then (PC PC + 1) Skip on input flag
SKO pB8: if(FGO = 1) then (PC PC + 1) Skip on output flag
ION pB7: IEN 1 Interrupt enable on
IOF pB6: IEN 0 Interrupt enable off

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