CMOS Inverter: DC Analysis
By
Dr.S.Rajaram,
Thiagarajar College of Engineering
Courtesy : Prof Andrew Mason
CMOS Inverter: DC Analysis
• Analyze DC Characteristics of CMOS Gates
by studying an Inverter
• DC Analysis
– DC value of a signal in static conditions
• DC Analysis of CMOS Inverter
– Vin, input voltage
– Vout, output voltage
– single power supply, VDD
– Ground reference
– find Vout = f(Vin)
• Voltage Transfer Characteristic (VTC)
– plot of Vout as a function of Vin
– vary Vin from 0 to VDD
– find Vout at each value of Vin
Courtesy : Prof Andrew Mason
Inverter Voltage Transfer Characteristics
• Output High Voltage, VOH
– maximum output voltage
• occurs when input is low (Vin = 0V)
• pMOS is ON, nMOS is OFF
• pMOS pulls Vout to VDD
– VOH = VDD
• Output Low Voltage, VOL
– minimum output voltage
• occurs when input is high (Vin = VDD)
• pMOS is OFF, nMOS is ON
• nMOS pulls Vout to Ground
– VOL = 0 V
• Logic Swing
– Max swing of output signal
• VL = VOH - VOL
• VL = VDD
Courtesy : Prof Andrew Mason
Inverter Voltage Transfer Characteristics
• Gate Voltage, f(Vin) •Drain Voltage, f(Vout)
– VGSn=Vin, VSGp=VDD-Vin –VDSn=Vout, VSDp=VDD-Vout
+
• Transition Region (between VOH and VOL) VSGp
– Vin low -
• Vin < Vtn
– Mn in Cutoff, OFF +
– Mp in Triode, Vout pulled to VDD VGSn
• Vin > Vtn < ~Vout -
– Mn in Saturation, strong current
– Mp in Triode, VSG & current reducing
– Vout decreases via current through Mn
– Vin = Vout (mid point) ≈ ½ VDD
– Mn and Mp both in Saturation
– maximum current at Vin = Vout
– Vin high Vin < VIL
• Vin > ~Vout, Vin < VDD - |Vtp|
– Mn in Triode, Mp in Saturation
input logic LOW
• Vin > VDD - |Vtp|
– Mn in Triode, Mp in Cutoff Vin > VIH
Error in Fig : Replace VOH to VOL
input logic HIGH
Courtesy : Prof Andrew Mason
Transistor operating regions
VDD
A B
Vout
C
D
E
0 Vtn VDD/2 VDD+Vtp
VDD
Region nMOS pMOS Vin
A Cutoff Linear
B Saturation Linear
C Saturation Saturation
D Linear Saturation
E Linear Cutoff
Courtesy : Prof Andrew Mason
Noise Margin
• Input Low Voltage, VIL
– Vin such that Vin < VIL = logic 0
– point ‘a’ on the plot
• where slope, Vin 1
Vout
• Input High Voltage, VIH
– Vin such that Vin > VIH = logic 1
– point ‘b’ on the plot
• where slope =-1
• Voltage Noise Margins Error in Fig : Replace VOH to VOL
– measure of how stable inputs are with respect to signal interference
– VNMH = VOH - VIH = VDD - VIH
– VNML = VIL - VOL = VIL
– desire large VNMH and VNML for best noise immunity
Courtesy : Prof Andrew Mason
Switching Threshold
• Switching threshold = point on VTC where Vout = Vin
– also called midpoint voltage, VM
– here, Vin = Vout = VM
• Calculating VM
– at VM, both nMOS and pMOS in Saturation
– in an inverter, IDn = IDp, always!
– solve equation for VM
nCOX W n p
I Dn (VGSn Vtn ) 2 (VGSn Vtn ) 2 (VSGp Vtp ) 2 I Dp
2 L 2 2
– express in terms of VM Error in Fig : Replace VOH to VOL
n p n
(V Vtn ) VDD VM Vtp
2
(VM Vtn )2
2
(VDD VM Vtp )2 p M
– solve for VM n
VDD Vtp Vtn
p
VM
n
1
p
Courtesy : Prof Andrew Mason
Effect of Transistor Size on VTC
• Recall W
k 'n VDD Vtp Vtn
n
n L n p
n k 'n
W VM
p W n
L k'p 1
L p p
• If nMOS and pMOS are same size
– (W/L)n = (W/L)p W
nCoxn
n L n n
– Coxn = Coxp (always) p
W
p
2or 3
W pCoxp
L p
n L p
• If
p W
, then n 1
p
since L normally min. size for all tx,
can get betas equal by making Wp larger than Wn
L n
• Effect on switching threshold
– if n p and Vtn = |Vtp|, VM = VDD/2, exactly in the middle
• Effect on noise margin
– if n p, VIH and VIL both close to VM and noise margin is good
Courtesy : Prof Andrew Mason
