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4-Bit Parallel Adder/Subtractor Design

This document describes the design of a 4-bit parallel adder cum subtractor circuit. It explains that subtraction can be performed by adding the 2's complement of the number to be subtracted. The circuit uses XOR gates on the input bits of the number to be subtracted (Y) to generate the 1's complement based on a control signal S. It also connects S to the carry in of a 4-bit parallel adder, allowing the circuit to perform either addition (S=0) or subtraction (S=1) on the input numbers X and Y.

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0% found this document useful (0 votes)
773 views17 pages

4-Bit Parallel Adder/Subtractor Design

This document describes the design of a 4-bit parallel adder cum subtractor circuit. It explains that subtraction can be performed by adding the 2's complement of the number to be subtracted. The circuit uses XOR gates on the input bits of the number to be subtracted (Y) to generate the 1's complement based on a control signal S. It also connects S to the carry in of a 4-bit parallel adder, allowing the circuit to perform either addition (S=0) or subtraction (S=1) on the input numbers X and Y.

Uploaded by

LEGENDARY GAMER
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd

Outline

 Block-Level Design
 4-bit Parallel Adder
4-bit Parallel Adder (1/4)

 Consider a circuit to add two 4-bit numbers together and a carry-


in, to produce a 5-bit result:

X4 X3 X2 X1 Y4 Y3 Y2 Y1

4-bit
C5 C1
Parallel Adder

Black-box view of 4-bit


S4 S3 S2 S1 parallel adder

 5-bit result is sufficient because the largest result is:


(1111)2+(1111)2+(1)2 = (11111)2
4-bit Parallel Adder (2/4)

 SSI design technique should not be used.


 Truth table for 9 inputs very big, i.e. 29=512 entries:

X4X3X2X1 Y4Y3Y2Y1 C1 C5 S4S3S2S1


0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 0 0 0 0 1
0 0 0 0 0 0 0 1 0 0 0 0 0 1
... ... ... ... ...
0 1 0 1 1 1 0 1 1 1 0 0 1 1
... ... ... ... ...
1 1 1 1 1 1 1 1 1 1 1 1 1 1

 Simplification very complicated.


4-bit Parallel Adder (3/4)

 Alternative design possible.

 Addition formulae for each pair of bits (with carry in),


Ci+1Si = Xi + Yi + Ci

has the same function as a full adder.


Ci+1 = Xi .Yi + (Xi  Yi ) .Ci
Si = Xi  Yi  Ci
4-bit Parallel Adder (4/4)

 Cascading 4 full adders via their carries, we get:

Y4 X4 Y3 X3 Y2 X2 Y1 X1
C4 C3 C2

C5 FA FA FA FA C1

S4 S3 S2 S1
Input
Output
Parallel Adders

 Note that carry propagated by cascading the carry from one full
adder to the next.
 Called Parallel Adder because inputs are presented
simultaneously (in parallel). Also, called Ripple-Carry Adder.
Outline
 Block-Level Design
 4-bit Parallel Adder
 BCD-to-Excess-3 Code Converter
 16-bit Parallel Adder
 4-bit Parallel Adder cum Subtractor
BCD-to-Excess-3 Code Converter (1/2)
 Excess-3 code can be converted BCD Excess-3
from BCD code using truth table: A B C D W X Y Z
0 0 0 0 0 0 0 1 1
1 0 0 0 1 0 1 0 0
2 0 0 1 0 0 1 0 1
 Gate-level design can be used 3
4
0
0
0 1
1 0
1
0
0 1 1 0
0 1 1 1
since only 4 inputs. 5 0 1 0 1 1 0 0 0
6 0 1 1 0 1 0 0 1
 However, alternative design 7 0 1 1 1 1 0 1 0
possible. 8 1 0 0 0 1 0 1 1
9 1 0 0 1 1 1 0 0
 Use problem-specific formulae: 10 1 0 1 0 X X X X
11 1 0 1 1 X X X X
Excess-3 Code 12 1 1 0 0 X X X X
13 1 1 0 1 X X X X
= BCD Code + (0011)2 14 1 1 1 0 X X X X
15 1 1 1 1 X X X X
BCD-to-Excess-3 Code Converter (2/2)

Excess-3 Code = BCD Code + (0011)2

 Block-level circuit: unused

Cout
X4
BCD X3

4-bit Parallel
code X2
S4

Adder
X1
S3 Excess-3
S2
0 Y4 code
S1
0 Y3
1 Y2
1 Y1
Cin
A BCD-to-Excess-3
Code Converter 0
Outline
 Block-Level Design
 4-bit Parallel Adder
 BCD-to-Excess-3 Code Converter
 16-bit Parallel Adder
 4-bit Parallel Adder cum Subtractor
16-bit Parallel Adder (1/2)

 Larger parallel adders can be built from smaller ones.


 Example: a 16-bit parallel adder can be constructed from four 4-
bit parallel adders:

X16..X13 Y16..Y13 X12..X9 Y12..Y9 X8..X5 Y8..Y5 X4..X1 Y4..Y1


4 4 4 4 4 4 4 4

C17 4-bit // C13 4-bit // C9 4-bit // C5 4-bit // C1


adder adder adder adder
4 4 4 4

S16..S13 S12..S9 S8..S5 S4..S1

A 16-bit parallel adder


16-bit Parallel Adder (2/2)

 Shortened notation for multiple lines.

4 is a shortened
notation for
S4 .. S1 S4 S3 S2 S1

16-bit parallel adder ripples carry from one 4-bit block to the next.

Such ripple-carry circuits are “slow” because of long delays


needed to propagate the carries.
Outline
 Block-Level Design
 4-bit Parallel Adder
 BCD-to-Excess-3 Code Converter
 16-bit Parallel Adder
 4-bit Parallel Adder cum Subtractor
4-bit Parallel Adder cum Subtractor (1/4)

 Subtraction can be performed through addition using 2s-


complement numbers.
 Hence, we can design a circuit which can perform both
addition and subtraction, using a parallel adder.

X4 X3 X2 X1 Y4 Y3 Y2 Y1

4-bit adder
S: control signal
cum subtractor for add/subtract

Result: either X+Y or X-Y


4-bit Parallel Adder cum Subtractor (2/4)

 The control signal S=0 means add


S=1 means subtract
 Recall that:
X-Y = X + (-Y)
= X + (2’s complement of Y)
= X + (1’s complement of Y) +1
X+Y = X + (Y)
4-bit Parallel Adder cum Subtractor (3/4)

 Design requires:

(i) XOR gates:

Y Y Y Y'
S=0 S=1

such that: output = Y when S=0


= Y' when S=1

(ii) S connected to carry-in.


4-bit Parallel Adder cum Subtractor (4/4)
 Adder cum subtractor circuit:
Y4 Y3 Y2 Y1
S
X4 X3 X2 X1

C Cout 4-bit Cin


parallel adder Analysis:
If S=1, then
X + (1's complement of Y) +1
S4 S3 S2 S1 appears as the result.
A 4-bit adder cum subtractor If S=0, then X+Y appears as
the result.

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