ARM Processor Core
Features
A load-store architecture;
Fixed-length 32-bit instructions;
3-address instruction formats.
Simplicity.
Most of Single cycle execution of most of instructions.
The ARM programmer's model
Registers
Register r13 is traditionally used as the stack pointer
(sp) and stores the head of the stack in the current
processor mode.
Register r14 is called the link register (lr) and is where
the core puts the return address whenever it calls a
subroutine.
Register r15 is the program counter (pc) and contains
the address of the next instruction to be fetched by the
processor.
The Current Program Status Register
(CPSR)
• The Jazelle J and Thumb T bits in the cpsr reflect the
state of the processor. When both J and T bits are 0, the
processor is in ARM state and executes ARM instructions.
•The ARM designers introduced a third instruction set
called Jazelle.
•Jazelle executes 8-bit instructions and is a hybrid mix of
software and hardware designed to speed up the execution
of Java byte codes.
Instruction Features
Cont...
Role of SPSR in mode change
The memory system (Little Endian
format)
Load-store architecture
ARM employs a load-store architecture
The instruction set will only process (add, subtract,
and so on) values which are in registers, and will
always place the results of such processing into a
register.
Therefore all ARM instructions fall into one of the
following three categories:
1. Data processing instructions.
2. Data transfer instructions.
3. Control flow instructions.
Supervisor mode
The ARM processor supports a protected supervisor
mode.
The protection mechanism ensures that user code
cannot gain supervisor privileges without appropriate
checks being carried out to ensure that the code is not
attempting illegal operations.
The ARM instruction set
All ARM instructions are 32 bits wide(except 16-bit Thumb)
Features:
The load-store architecture;
3-address data processing instructions (that is, the two source
operand registers and the result register are all independently
specified);
conditional execution of every instruction;
the inclusion of very powerful load and store multiple register
instructions;
the ability to perform a general shift operation and a general ALU
operation in a single instruction that executes in a single clock
cycle;
open instruction set extension through the coprocessor instruction
set, including adding new registers and data types to the
programmer's model;
a very dense 16-bit compressed representation of the instruction set
in the Thumb architecture.
The I/O system
The ARM handles I/O (input/output) peripherals
(such as disk controllers, network interfaces, and so
on) as memory-mapped devices with interrupt
support.
Peripherals may attract the processor's attention by
making an interrupt request using either the normal
interrupt (IRQ) or the fast interrupt (FIQ) input.
Both interrupt inputs are level-sensitive and maskable.
ARM exceptions
The ARM architecture supports a range of interrupts,
traps and supervisor calls, all grouped under the
general heading of exceptions
The general way these are handled is the same in all
cases:
The current state is saved by copying the PC into rl4_exc
and the CPSR into SPSR_exc (where exc stands for the
exception type).
The processor operating mode is changed to the
appropriate exception mode.
The PC is forced to a value between 0016 and 1C16, the
particular value depending on the type of exception.
ARM development tools
Since the ARM is widely used as an embedded
controller where the target hardware will not make a
good environment for software development, the tools
are intended for cross-development.
5-stage pipeline ARM organization
The time,T , required to execute a given program is
given by:
where Ninst is the number of ARM instructions
executed in the course of the program,
CPI is the average number of clock cycles per
instruction and fclk is the
processor's clock frequency
Cont..
There are only two ways to increase performance:
Increase the clock rate, fclk.
This requires the logic in each pipeline stage to be
simplified and, therefore, the number of pipeline stages
to be increased.
Reduce the average number of clock cycles per
instruction, CPI.
The 5-stage pipeline
The ARM processors which use a 5-stage pipeline have
the following pipeline stages:
Fetch: the instruction is fetched from memory and
placed in the instruction pipeline.
Decode: the instruction is decoded and register
operands read from the register file.
Execute: an operand is shifted and the ALU result
generated.
Buffer/data: data memory is accessed if required.
Write-back: the results generated by the instruction are
written back to the register file, including any data
loaded from memory.
Figure 4.4 ARM9TDMI 5-stage pipeline organization
ARM datapath Timing
The minimum datapath cycle time is therefore the
sum of:
the register read time;
the shifter delay;
the ALU delay;
the register write set-up time;
the phase 2 to phase 1 non-overlap time.
ARM Dataflow model
Exceptions, Interrupts, and the Vector Table
Exception and Interrupt Handling in ARM
Here are the steps that the ARM processor does to handle
an exception :
Preserve the address of the next instruction.
Copy CPSR to the appropriate SPSR, which is one of the
banked registers for each mode of operation.
Force the CPSR mode bits to a value depending on the raised
exception.
Force the PC to fetch the next instruction from the exception
vector table.
Now the handler is running in the mode associated with the raised
exception.
When handler is done, the CPSR is restored from the saved
SPSR.
PC is updated with the value of (LR – offset) and the offset
value depends on the type of the exception.
Cont..
And when deciding to leave the exception handler, the
following steps occurs:
Move the Link Register LR (minus an offset) to the
PC
Copy SPSR back to CPSR, this will automatically
changes the mode back to the previous one.
Clear the interrupt disable flags (if they were set).
Interrupts
There are two types of interrupts available on ARM
processor. The first type is the interrupt caused by
external events from hardware peripherals and the
second type is the SWI instruction.
The ARM core has only one FIQ pin, that is why an
external interrupt controller is always used so that the
system can have more than one interrupt source which
are prioritized with this interrupt controller and then
the FIQ interrupt is raised and the handler identifies
which of the external interrupts was raised and handle
it.
How are interrupts assigned?
There is a standard design for assigning interrupts
adopted by system designers:
SWIs are normally used to call privileged operating
system routines.
IRQs are normally assigned to general purpose
interrupts like periodic timers.
FIQ is reserved for one single interrupt source that
requires fast response time, like DMA or any time
critical task that requires fast response.
IRQ and FIQ exceptions
The ARM processor will continue executing the
current instruction in the pipeline before handling the
interrupt.
The processor changes to a specific mode depending on
the received interrupt.
The previous mode CPSR is saved in SPSR of the new
mode.
The PC is saved in the LR of the new mode.
Interrupts are disabled, either IRQ or both IRQ and
FIQ.
The processor branches to a specific entry in the vector
table.
Non-nested interrupt handling
Non-nested interrupt handling
Advantages of Non-nested interrupt handling
Handle and service individual interrupts sequentially.
High interrupt latency.
Relatively easy to implement and debug.
Not suitable for complex embedded systems.
Nested interrupt handling
In this handling scheme handling more than one
interrupt at a time is possible.
This is achieved by re-enabling interrupts before the
handler has fully served the current interrupt.
The goal of nested handling is to respond to interrupts
quickly and to execute periodic tasks without any
delays.
The main disadvantage of this interrupt handling
scheme is that it doesn’t differ between interrupts by
priorities, so lower priority interrupt can block higher
priority interrupts.
Prioritized simple interrupt handling
