Digital Integrated
Circuits
A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic
Designing Sequential
Logic Circuits
November 2002
© Digital Integrated Circuits2nd
Sequential Circuits
Sequential Logic
Inputs Outputs
COMBINATIONAL
LOGIC
Current State
Next state
Registers
Q D
CLK
2 storage mechanisms
• positive feedback
• charge-based
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Sequential Circuits
Timing Metrics for Sequential Circuits
• Set-up time (tsu): It is the time that the data inputs (D
input) must be valid before the clock transition (this is,
the 0 to 1 transition for a positive edge-triggered
register)
It is the time the data input must remain
valid after the clock edge
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Timing parameters for the registers
• Propagation Delay (tcq): Data at D is copied to
Q after the worst case propagation delay (tplogic)
• Minimum propagation delay (contamination
delay)
tcd
• Minimum clock period T >= tcq + tplogic + tsu
• Also, tcdregister + tcdlogic >= thold
• The min propagation delay of the register tcdregister
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Sequential Circuits
Latches
Positive Latch Negative Latch
In D Q Out In D Q Out
G G
CLK CLK
clk clk
In In
Out Out
Out Out Out Out
stable follows In stable follows In
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Sequential Circuits
Static Latches and Registers: Bistability
• A circuit having two stable states that represent 0 and 1
• Only three possible operating points: A, B and C
• If the gain of the inverter in the transient region is larger
than 1, only A and B are stable operation points,
• C is a metastable operation point
Voltage
transfer
Cascaded Inverters Characteristics
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Sequential Circuits
Metastability: Positive feedback
Gain should be
greater than 1
in the transition
region
• If the gain around the loop being larger than 1, A small
deviation d is applied to Vi1 (biased in C) amplified by
the gain of the inverter
• C is an unstable operation point: bias point moves
away from C until one of the operation points A or B is
reached
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Sequential Circuits
Mux-Based Latches
Negative latch
Positive latch
(transparent when CLK= 0)
(transparent when CLK= 1)
Q 0 Q
1
D 0 D 1
CLK CLK
Q Clk Q Clk D Q Clk Q Clk D
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Sequential Circuits
Mux-Based Latch
CLK
CLK
CLK
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Sequential Circuits
Mux-Based Latch
CLK
QM
CLK
QM
CLK
CLK
NMOS only Non-overlapping clocks
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Sequential Circuits
Master-Slave (Edge-Triggered)
Register
Slave
Master
0 Q D
1 QM
1
QM
D 0 Q
CLK
CLK
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Sequential Circuits
Master-Slave Register
Multiplexer-based latch pair
I2 T2 I3 I5 T4 I6 Q
QM
D I1 T1 I4 T3
CLK
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Sequential Circuits
Timing properties of MUX based
Master slave reg
Holdtime =0
Propagation Delay = tinv+tpd_tx
Set up time=(3 X tinv_pd )+ tpd_tx
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Sequential Circuits
Reduced Clock Load
Master-Slave Register
CLK CLK
D T1 I1 T2 I3 Q
I2 I4
CLK CLK
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Sequential Circuits
Reduced Clock Load
Master-Slave Register
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Sequential Circuits
Non ideal clock signal
CLK X CLK
Q
A
D
B
CLK CLK
(a) Schematic diagram
CLK
CLK
(b) Overlapping clock pairs
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Sequential Circuits
Avoiding Clock Overlap
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Sequential Circuits
Circuit to generate two phase non
overlapping clock
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Sequential Circuits
Overpowering the Feedback Loop ─
Cross-Coupled Pairs
NOR-based set-reset
S R Q Q
S
Q
S Q 0 0 Q Q
1 0 1 0
R Q
0 1 0 1
Q
R 1 1 0 0
Forbidden State
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Sequential Circuits
Added clock
VDD
M2 M4
Q
Q
CLK M6 M8 CLK
M1 M3
S M5 M7 R
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Sequential Circuits
End of Static Latches and registers
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Sequential Circuits
Storage Mechanisms
Static Dynamic (charge-based)
CLK
CLK
D Q
Q
CLK
CLK
D
CLK
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Sequential Circuits
Dynamic Latches and registers
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Sequential Circuits
Dynamic edge triggered reg
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Sequential Circuits
Race condition
• Clock overlap is an important concern for registers.
(two types of overlaps)
Overlap Transmission Transmission Effects
gate T1 gate T2
0-0 NMOS PMOS Direct path from
1-1 PMOS NMOS input to output
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Sequential Circuits
Race condition
Preventive measures
•The data must be stable during the high-high overlap
period.
•Enough delay between the D input and node 2 ensuring
that new data sampled by the master stage does not
propagate through to the slave stage.
•Overlap constrains
– T_overlap 0-0– < tT1 + tI1 + tT2
– Thold > Toverlap1-1
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Sequential Circuits
Other Latches/Registers: C2MOS
VDD VDD
M2 M6
CLK M4 CLK M8
X
D Q
CL1 CL2
CLK M3 CLK M7
M1 M5
Master Stage
“Keepers” can be added to make circuit pseudo-static
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Sequential Circuits
Insensitive to Clock-Overlap
VDD VDD VDD VDD
M2 M6 M2 M6
0 M4 0 M8
X X
D Q D Q
1 M3 1 M7
M1 M5 M1 M5
(a) (0-0) overlap (b) (1-1) overlap
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Dual-edge Registers
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True Single Phase Clocked latch
VDD VDD VDD VDD
Out
In CLK CLK In CLK CLK
Positive latch Negative latch
(transparent when CLK= 1) (transparent when CLK= 0)
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Sequential Circuits
Including Logic in TSPC
VDD VDD VDD VDD
In1 In2
PUN
Q Q
In CLK CLK CLK CLK
In1
PDN
Example: logic inside the latch
AND latch
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Sequential Circuits
Simplified TSPC latch
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Sequential Circuits
TSPC Register
VDD VDD VDD
CLK Q
M3 M6 M9
Y
Q
D CLK X CLK
M2 M5 M8
CLK
M1 M4 M7
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Sequential Circuits
Pipelining
REG
REG
a a
REG
REG
REG
REG
log Out CLK log Out
CLK
REG
REG
b CLK b CLK CLK CLK
CLK CLK
Reference Pipelined
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Sequential Circuits
Pipelining Approach -Latch- vs. Register- Based Pipelines
• Mater-slave Latch-based systems give significantly more
flexibility and offers performance in implementing a
pipelined system, compared to edge triggered registers.
•Whe the clocks
n and CLK C̅ L̅ K̅
overlapping, are
correctnon-
pipeline
operation is Obtained.
•When overlap exists
between CLK and C̅ L̅
K̅ , a race develops
between the previous
input and the current
© Digital Integrated Circuits2nd one.
Sequential Circuits
Pipelining Approach –NORA CMOS Logic
• Latch-based pipeline circuit can also be implemented using
C2MOS latches for race free operation.
• A C2MOS-based pipelined circuit is race-free as long as all
the logic functions F (implemented using static logic)
between the latches are non-inverting
• During a (0-0) overlap between CLK and ̅C̅LK̅ ̅, all
C2MOS latches, simplify to pure pull-up networks
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Sequential Circuits
Pipelining Approach –NORA CMOS Logic
When the logic function F
is inverting (F is replaced
by a static inverter) race
condition during (0-0)
overlap in C2MOS-based
design is avoided.
• NORA-CMOS combines C2MOS pipeline registers and
NORA dynamic logic function blocks.
• Each module consists of a block of combinational logic
that can be a mixture of static and dynamic logic,
followed by a C2MOS latch.
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Sequential Circuits
NORA- CLK- NORA-CMOS C̅ L̅ K̅ -module
CMOS module
• Text
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Sequential Circuits
Timing issues in sequential circuits
Clock skew
Clock jitter
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Clock skew
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Positive clock skew
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Negative clock skew
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Clock skew elimination
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Clock jitter
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Techniques to reduce clock skew
and clock jitter
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