Chapter 7

Microprogrammed Control
Third year, ECE Department 2019-2020
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Microprogrammed Control 2

MICROPROGRAMMED CONTROL

• Control Memory

• Sequencing Microinstructions

• Microprogram Example

• Design of Control Unit

• Microinstruction Format

Computer Architectures
Microprogrammed Control 3

Control Unit
• Initiate sequences of microoperations by control signals
• Two major types of Control Unit
» Hardwired Control
The control logic is implemented with gates, F/Fs, decoders, …
+ Fast operation.
- Wiring change(if the design has to be modified)
» Microprogrammed Control
The control information is stored in a control memory, and the
control memory is programmed to initiate the required sequence
of microoperations
+ Any required change can be done by updating the
microprogram in control memory.
- Slow operation
Computer Architectures
Microprogrammed Control 4 Implementation of Control Unit
COMPARISON OF CONTROL UNIT IMPLEMENTATIONS
Hard-wired CU

Control Data
Instruction from main Memory IR Status F/Fs

Control Unit's State

Timing State
Combinational Control CPU
Logic Circuits Points
Ins. Cycle State

Microprogramme CU
CW: Control Word
SW: Sequence Word
Instruction Control Data
from main IR Status F/Fs
Memory
CDR

C Control CW
Next Address Memory Control CPU
Generation A D points
(-program ------
Logic R memory)
SW }

Computer Architectures
Microprogrammed Control 5

TERMINOLOGY
• Microprogram: Sequence of micorinstructions stored in control
memory that generates all the control signals required to execute the
instruction set correctly
• Dynamic Microprogramming
 RAM can be used for writing
 Microprogram is loaded initially from an auxiliary memory

• Static Microprogramming
 Control words in ROM are made permanent during the hardware
production.
• Microinstruction
- Contains a control word and a sequencing word
Control Word - control information required for one clock cycle
Sequencing Word - Information needed to decide the next
microinstruction address
Computer Architectures
Microprogrammed Control 6

Microprogrammed Control Organization

Control
External word
Next-address Control Control Control
input
generator address memory data
(sequencer) register (ROM) register

Next-address information

• Main Memory: for storing user program

(Machine instruction/data)
• Control Memory: part of control unit for
storing microprogram (Microinstruction)

Computer Architectures
Microprogrammed Control 7

Microprogrammed Control Organization

Control Address Register (CAR): Specify address of the
microinstruction
Sequencer
» Determine the address sequence read from control memory
» Next address of the next microinstruction can be specified several
way depending on the sequencer input.

Sequencing Capabilities Required in a Control Storage

1. Incrementing of the control address register
2. Unconditional and conditional branches
3. A mapping process from the bits of the machine instruction to an
address for control memory
4. A facility for subroutine call and return

Computer Architectures
Microprogrammed Control 8 Microprogram

7-3 MICROPROGRAM EXAMPLE

Computer Configuration

MUX
10 0 Memory
AR 2048 x 16
Address
10 0
PC

MUX
15 0
6 0 6 0 DR
SBR CAR

Control memory Arithmetic

128 x 20 logic and
shift unit
Control unit
15 0
AC

Computer Architectures
Microprogrammed Control 9 Microprogram

MACHINE INSTRUCTION FORMAT

Machine instruction format

15 14 11 10 0
I Opcode Address

Sample machine instructions

Symbol OP-code Description

ADD 0000 AC AC + M[EA]
BRANCH 0001 if (AC < 0) then (PC  EA)
STORE 0010 M[EA]  AC
EXCHANGE 0011 AC  M[EA], M[EA]  AC

EA is the effective address

Computer Architectures
Microprogrammed Control 10 Sequencing

MAPPING OF INSTRUCTIONS
Address Control Memory
Each instruction
OP-codes of Instructions 0 0000 00 0 routine occupies
ADD Routine four locations
ADD 0000
BRANCH 0001 0 0001 00 4
BRANCH Routine
STORE 0010
EXCHANGE 0011 0 0010 00 8
STORE Routine
0 0011 00 12
EXCHANGE Routine
Mapping 0 xxxx 00
Bits

1000000 64
Fetch Routine

• Control Storage: 128, 20-bit words

• The first 64 words: Routines for the 16 machine instructions
• The last 64 words: for other purpose (e.g., fetch routine and other subroutines)
Computer Architectures
Microprogrammed Control 11 Microprogram

Instruction Execution
1. Fetch routine gets the
instruction from main
memory to DR.
Address Memory
2048 x 16
2. Opcode mapped to address
of the first microinstruction
of the routine and stored in
CAR.
MUX
3. The microinstruction
6 0 6 0
15 0 executed and the next
DR
SBR CAR address generated
4. Repeat 3 until all
Control memory
128 x 20
Arithmetic
logic and microinstructions of the
shift unit instruction routine
Control unit
15 0 executed.
AC 5. Go to 1

Computer Architectures
Microprogrammed Control 12 Microprogram

MICROINSTRUCTION FORMAT

Microinstruction Format
3 3 3 2 2 7
F1 F2 F3 CD BR AD

Sequencer

F1, F2, F3: Microoperation fields

CD: Condition for branching
BR: Branch field
AD: Address field

Computer Architectures
Microprogrammed Control 13 Microprogram

MICROINSTRUCTION FIELD DESCRIPTIONS - F1,F2,F3

F1 Microoperation Symbol F2 Microoperation Symbol

000 None 000 None NOP
NOP 001 AC  AC - DR SUB
001 AC  AC + DR 010 AC  AC  DR OR
ADD 011 AC  AC  DR AND
010 AC  0 100 DR  M[AR] READ
CLRAC 101 DR  AC ACTDR
011 AC  AC + 1 110 DR  DR + 1 INCDR
INCAC 111 DR(0-10)  PC PCTDR
100 AC  DR
DRTAC F3 Microoperation Symbol
000 None NOP
101 AR  DR(0-10)
001 AC  AC  DR XOR
DRTAR
010 AC  AC’ COM
110 AR  PC
011 AC  shl AC SHL
PCTAR
100 AC  shr AC SHR
111 M[AR]  DR
101 PC  PC + 1 INCPC
WRITE
110 PC  AR ARTPC
111 Reserved
Computer Architectures
Microprogrammed Control 14 Microprogram

MICROINSTRUCTION FIELD DESCRIPTIONS - CD, BR

CD Condition Symbol Comments

00 Always = 1 U Unconditional branch
01 DR(15) I Indirect address bit
10 AC(15) S Sign bit of AC
11 AC = 0 Z Zero value in AC

BR Symbol Function
00 JMP CAR  AD if condition = 1
CAR  CAR + 1 if condition = 0
01 CALL CAR  AD, SBR  CAR + 1 if condition = 1
CAR  CAR + 1 if condition = 0
10 RET CAR  SBR (Return from subroutine)
11 MAP CAR(2-5)  DR(11-14), CAR(0,1,6)  0

Computer Architectures
Microprogrammed Control 15 Microprogram
SYMBOLIC MICROINSTRUCTIONS
• Symbols are used in microinstructions as in assembly language
• A symbolic microprogram can be translated into its binary equivalent by a
microprogram assembler.
• Sample Format, five fields:
[ label : ] micro-ops CD BR address

Label: may be empty or specify a symbolic address terminated with a colon

Micro-ops: consists of one, two, or three symbols separated by commas

CD: one of {U, I, S, Z}, where U: Unconditional Branch

I: Indirect address bit
S: Sign of AC
Z: Zero value in AC

BR: one of {JMP, CALL, RET, MAP}

AD: one of {Symbolic address, NEXT, empty}

Computer Architectures
Microprogrammed Control 16 Microprogram

SYMBOLIC MICROPROGRAM - FETCH ROUTINE

During FETCH, Read an instruction from memory

and decode the instruction and update PC

Sequence of microoperations in the fetch cycle:

AR  PC
DR  M[AR], PC  PC + 1
AR  DR(0-10), CAR(2-5)  DR(11-14), CAR(0,1,6)  0

Symbolic microprogram for the fetch cycle:

ORG 64
FETCH: PCTAR U JMP NEXT
READ, INCPC U JMP NEXT
DRTAR U MAP

Binary equivalents translated by an assembler

Binary
address F1 F2 F3 CD BR AD
1000000 110 000 000 00 00 1000001
1000001 000 100 101 00 00 1000010
1000010 101 000 000 00 11 0000000

Computer Architectures
Microprogrammed Control 17 Microprogram

SYMBOLIC MICROPROGRAM
Label Microops CD BR AD
ORG 0
ADD: NOP I CALL INDRCT
READ U JMP NEXT
ADD U JMP FETCH
ORG 4
BRANCH: NOP S JMP OVER
NOP U JMP FETCH
OVER: NOP I CALL INDRCT
ARTPC U JMP FETCH
ORG 8
STORE: NOP I CALL INDRCT
ACTDR U JMP NEXT
WRITE U JMP FETCH
ORG 12
EXCHANGE: NOP I CALL INDRCT
READ U JMP NEXT
ACTDR, DRTAC U JMP NEXT
WRITE U JMP FETCH
ORG 64
FETCH: PCTAR U JMP NEXT
READ, INCPC U JMP NEXT
DRTAR U MAP
INDRCT: READ U JMP NEXT
DRTAR U RET

Computer Architectures
Microprogrammed Control 18 Microprogram

BINARY MICROPROGRAM
Address Binary Microinstruction
Micro Routine Decimal Binary F1 F2 F3 CD BR AD
ADD 0 0000000 000 000 000 01 01 1000011
1 0000001 000 100 000 00 00 0000010
2 0000010 001 000 000 00 00 1000000
3 0000011 000 000 000 00 00 1000000
BRANCH 4 0000100 000 000 000 10 00 0000110
5 0000101 000 000 000 00 00 1000000
6 0000110 000 000 000 01 01 1000011
7 0000111 000 000 110 00 00 1000000
STORE 8 0001000 000 000 000 01 01 1000011
9 0001001 000 101 000 00 00 0001010
10 0001010 111 000 000 00 00 1000000
11 0001011 000 000 000 00 00 1000000
EXCHANGE 12 0001100 000 000 000 01 01 1000011
13 0001101 001 000 000 00 00 0001110
14 0001110 100 101 000 00 00 0001111
15 0001111 111 000 000 00 00 1000000

FETCH 64 1000000 110 000 000 00 00 1000001

65 1000001 000 100 101 00 00 1000010
66 1000010 101 000 000 00 11 0000000
INDRCT 67 1000011 000 100 000 00 00 1000100
68 1000100 101 000 000 00 10 0000000

This microprogram can be implemented using ROM

Computer Architectures
Microprogrammed Control 19 Design of Control Unit

MICROPROGRAM SEQUENCER
External form opcode
field of DR (MAP) Figure 7-8

L F1, F2, F3: Microoperation fields

I0
Input
3 2 1 0
Load CD: Condition for branching
I1 logic S1 MUX1 SBR
T S0
BR: Branch field
AD: Address field

1 Incrementer
I MUX2 Test
S
Z Select
Clock CAR

Control memory
Microops CD BR AD
... ...

Computer Architectures
Microprogrammed Control 20 Design of Control Unit
MICROPROGRAM SEQUENCER
- NEXT MICROINSTRUCTION ADDRESS LOGIC -
Branch, CALL Address
External
(MAP) RETURN form Subroutine
In-Line
S 1S 0 Address Source
00 CAR + 1, In-Line 3 2 1 0 L
S1 MUX1 SBR Subroutine
01 CS(AD), Branch or CALL S0
10 SBR RETURN Address CALL
11 MAP
source
selection Incrementer

Clock CAR

Control Storage

MUX-1 selects an address from one of four sources and routes it into a CAR
- In-Line Sequencing  CAR + 1
- Branch, Subroutine Call  CS(AD)
- Return from Subroutine  Output of SBR
- New Machine instruction  MAP
Computer Architectures
Microprogrammed Control 21 Design of Control Unit
MICROPROGRAM SEQUENCER
- CONDITION AND BRANCH CONTROL -

1 L
L(load SBR with PC) for subroutine
From I MUX2 Test Call
CPU S T
Select Input
Z BR field I0 logic S0
of CS I1 for next address selection
S1

CD Field of CS

Input Logic
I1 I0 T Meaning Source of Address S1 S0 L
000 JMP, condition 0 CAR+1 0 0 0
001 JMP, condition 1 CS(AD) 0 1 0
010 CALL, condition 0 CAR+1 0 0 0
011 CALL, condition 1 CS(AD), SBR <- CAR+1 0 1 1
10x RET SBR 1 0 0
11x MAP DR(11-14) 1 1 0

S1 = I1
S0 = I1 I0 + I1’ T
L = I1’ I0T
Computer Architectures
Microprogrammed Control 22 Design of Control Unit
DESIGN OF CONTROL UNIT
- DECODING ALU CONTROL INFORMATION -

Computer Architectures
 Homework
Solve problems: 7.7, 7.11, 7.14,