CS3510
BUS Structures
Connecting Paths
All the units/components of a system must be connected Different types of connections are needed for different types of unit
Memory Input/Output CPU
The collection of paths connecting the various modules is called the interconnection structure
General System Components
Op Sys
CPU
Main Mem
Secondary Store Disk Bus
I/O Dev
Computer Modules
Memory Connection
Receives and sends data Receives addresses (of locations) Receives control signals
Read Write Timing
Input/Output Connection(1)
Similar to memory from computers viewpoint Output
Receive data from computer Send data to peripheral Receive data from peripheral Send data to computer
Input
Input/Output Connection(2)
Receive control signals from computer Send control signals to peripherals
e.g. spin disk
Receive addresses from computer
e.g. port number to identify peripheral
Send interrupt signals (control)
CPU Connection
Reads instruction Reads data Writes out data (after processing) Sends control signals to other units Sends addresses to other units Receives (& acts on) interrupts
Bus Structure
A communication pathway connecting two or more devices Usually allow broadcast transfers Often grouped
A number of channels in one bus e.g. 32 bit data bus is 32 separate single bit channels
Power lines may not be shown
Buses
There are a number of possible interconnection systems Single and multiple BUS structures are most common e.g. Control/Address/Data bus (PC) e.g. Unibus (DEC)
Basic Structure
Data Lines Address Lines Control Lines
11
Bus Interconnection Scheme
Data Bus
Carries data
Remember that there is no difference between data and instruction at this level
Bus width is a key determinant of performance
8, 16, 32, 64 bit
Address Bus
Identify the source or destination of data or instruction Address Bus width determines maximum memory capacity of system
e.g. 8080 microprocessor has 16 bit address bus giving 64k address space e.g. 8086 microprocessor has 20 bit address bus giving 1M address space Modern microprocessors have more bits for address bus
Control Bus
Control and timing information Memory read/write signal Interrupt request Clock signals
Physical Aspects of a Bus
What do buses look like?
Parallel lines on circuit boards Ribbon cables Strip connectors on mother boards
e.g. PCI
Sets of wires
Operation of a Bus
If a module needs to send data to another module, it must:
1. 2.
Obtain the use (access) of the bus Transfer data via the bus
If a module needs to request data from another module, it must:
1. 2. 3.
Obtain the use of the bus Transfer the request to the other module Wait for the second module to send the data
Single Bus Problems
Lots of devices on one bus leads to propagation delays
Long data paths mean that co-ordination of bus use can adversely affect performance If aggregate data transfer approaches bus capacity, the bus may become the bottleneck of the system
Most systems use multiple buses to overcome these problems
Traditional (ISA) (with cache)
High Performance Bus
Bus Types
Dedicated
Separate data & address lines Shared lines (address and data) Address valid or data valid control line Advantage - fewer lines Disadvantages
Multiplexed
More complex control Ultimate performance
Bus Arbitration
Allows more than one module to control the bus e.g. CPU and DMA controller Only one module may control bus at one time Arbitration may be:
Centralized Distributed
One module is designated as the master, which then initiates data transfer with a slave module
Bus Centralized Arbitration
Single hardware device controlling bus access
Bus Controller Arbiter
May be part of CPU or separate
Bus Distributed Arbitration
Each module may claim the bus Control logic on all modules
Timing
Co-ordination of events on bus Synchronous timing
Events determined by clock signals Control Bus includes clock line A single 1-0 is a bus cycle All devices can read clock line Usually sync on leading edge Usually a single cycle for an event
Synchronous Timing Diagram
Asynchronous Timing Read Diagram
Asynchronous Timing Write Diagram
PCI Bus
Peripheral Component Interconnection Intel released to public domain 32 or 64 bit 50 lines
PCI Bus Lines
Systems lines
Including clock and reset
32 time mux lines for address/data Interrupt & validate lines
Address & Data
Interface Control Arbitration
Not shared Direct connection to PCI bus arbiter
Error lines
PCI Bus Lines (Optional)
Interrupt lines
Not shared
Cache support 64-bit Bus Extension
Additional 32 lines Time multiplexed 2 lines to enable devices to agree to use 64-bit transfer For testing procedures
JTAG/Boundary Scan
PCI Commands
Transaction between initiator (master) and target Master claims bus Determine type of transaction
e.g. I/O read/write
Address phase One or more data phases
PCI Read Timing Diagram
PCI Bus Arbitration
